bootblock et al were listed twice, which shouldn't happen.
Change-Id: I3e6077d70e064ebe74bd4e5e3156f87d548c2fcb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10097
Tested-by: build bot (Jenkins)
The name is more consistent with what we have elsewhere,
and the callsite didn't build at all (with vboot enabled)
Change-Id: I3576f3b8f737d360f68b67b6ce1683199948776d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10096
Tested-by: build bot (Jenkins)
It's not used at all.
Change-Id: I97bf02a9277f6ca348443c6886f77b4dfc70da78
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10095
Tested-by: build bot (Jenkins)
The vboot mechanism will be implemented within the program loader
subsystem to make it transparent to mainboards and chipsets.
Change-Id: Icd0bdcba06cdc30591f9b25068b3fa3a112e58fb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10094
Tested-by: build bot (Jenkins)
On current Danger boards, VCC_LCD is gated by BL_EN. Thus we
need to enable BL_EN in order to power on the display so that
we can read the EDID and set things up.
Later board revisions may change this ordering, but for now it
doesn't seem to be causing a significant issues (no noticable
"snow" or other corruption using Pepto display).
BUG=none
BRANCH=none
TEST=booted on Danger, saw dev mode screen come up
Change-Id: I70aab8c1f6da2d0fce310d59073026eef0f67821
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a918824e747600a2f3a88602320f4f563ce17b7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Iaf17cc4682bd3c46f62cba789e3ecf8d5a474362
Original-Reviewed-on: https://chromium-review.googlesource.com/266913
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10089
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This patch initializes the GPIO for the Chrome EC interrupt line on
Veyron boards and passes its description through the coreboot table, so
that payloads with keyboard support can use it to detect pending key
presses.
BRANCH=none
BUG=chrome-os-partner:39514
TEST=Booted Jerry, confirmed that it could still detect keypresses.
Confirmed that EC log does not show a huge amount of MKBP polls.
Change-Id: I4de35ef411c3acc02282ebf8e764785a1e7bf6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ad95d667ef3af3fb217e3c370468dc1d6ec36c9
Original-Change-Id: I8b426621af088460929cfff0a4b46618e2a86725
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/267344
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/10088
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
When CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is set, this
function is now linked into the ramstage as well as the romstage,
since the former makes calls to it in panther builds.
With this commit, it's possible to build panther using the config file
from the Chromium OS project[1] if you supply the appropriate Intel
descriptor and ME binary blobs and manually set
CONFIG_VBOOT_VERIFY_FIRMWARE=n, CONFIG_BUILD_WITH_FAKE_IFD=n, and
CONFIG_HAVE_ME_BIN=y. The resulting image is at least able to load a
payload, although I only tested with depthcharge, which immediately
complained, "vboot handoff pointer is NULL" and gave up the ghost.
[1] https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/master/sys-boot/coreboot/files/configs/config.panther
Change-Id: Id3bb510fa60129a4d36a0117dc33e7aa62d6c742
Signed-off-by: Sol Boucher <solb@chromium.org>
Reviewed-on: http://review.coreboot.org/10046
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Once a bridge window resource is allocated, it becomes the base and limit
for any resource on the secondary bus. Upper limit was incorrectly
reported in the log while assigning secondary resources.
Change-Id: I69f0a02aae6d13f77aaa2dace924b8970b23edad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I19af5f36a55d6c2906d603e940b3aadd2ca97140
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8317
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The 'A' indicates the production process(64 nm). All other chips from
the same family leave this out.
TEST=Build and booted on Minnowboard Max
Change-Id: I21e6c01de5d547bbc2252e679a001948e7ab752c
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10078
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
'.op_erase' was not specified for this chip. Set it to sub sector
erase(CMD_M25PXX_SSE). Adjust page/sector size for sub sector erase
to work.
TEST=Untested, due to lack of hardware.
Change-Id: Icc2748fbd3afeb56693e1c17d97eb490fba67064
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10077
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
N25Q064 is similar to N25Q128.
TEST=Build and booted twice on Minnowboard Max
Change-Id: Iec105f8b81f619846cf40b40042cc59150b81149
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10076
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix compiler error's due to type mismatch. This is broken since commit
bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to
pointer).
TEST=Build with CONFIG_DEBUG_SPI_FLASH=y and booted on Minnowboard Max
Change-Id: Id3d448e219716135897f381a73d416ff34036118
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10075
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
What is described by the comment has already been fixed in f0d038f4
(flash: use two bytes of device ID to identify stmicro chips).
This also means that STM_ID_N25Q128 doesn't have to be at the top of
stmicro_spi_flash_table anymore.
TEST=Untested, due to lack of hardware
Change-Id: I7a9e9a0cdfdb1cf34e914e186fc6957c1d9b5ca6
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10068
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The log message says 'page size' while actually the sector size is
printed. This is confusing since for stmicro page size != sector size.
Also add '0x' prefix to numbers to make it clear they are in hex.
TEST=Build and booted on Minnowboard Max
Change-Id: I795a4b7c1bc8de2538a87fd4ba56f5a78d9ca2ac
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10067
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
None of the sockets has actual configuration options, so the source
for them is only cosmetical boilerplate. Hence, drop it. This reduces
the sockets to be selectors for certain CPU types, which will be dropped
in future commits, and mainboards will select their CPUs directly rather
than through an additional layer of indirection (sockets)
Change-Id: I0f52a65838875a73531ef8c92a171bb1a35be96e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9797
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Fix up commit c13ad6c6 (driver/intel/fsp: Correct the fastboot data (MRC
data) printing length) unintentionally making the changed files
executable.
Change-Id: I909c323023a9ccfb0c20094d9085ae90043b9e04
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10060
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
The Rangeley chipset has the MMIO PCI config space feature
enabled at 0xe0000000-0xefffffff. This is a 256MB space
which covers all of config space. The ACPI table for
this space only defines it as being 64MB. This change
fixes that setting.
Change-Id: I8205a9b89ea6633ac6c4b0d5a282cd2745595b2e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/10047
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Several of the intel platforms define the region reserved
for PCI memory resources in a location where it overlaps
with the MMIO (MCFG) region.
Using the memory map from mohon_peak as an example:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000007fbcffff: RAM
4. 000000007fbd0000-000000007fbfffff: CONFIGURATION TABLES
5. 000000007fc00000-000000007fdfffff: RESERVED
6. 00000000e0000000-00000000efffffff: RESERVED
7. 00000000fee00000-00000000fee00fff: RESERVED
8. 0000000100000000-000000017fffffff: RAM
The ACPI table describing the space set aside for PCI memory
(not to be confused with the MMIO config space) is defined
as the region from BMBOUND (the top of DRAM below 4GB) to
a hardcoded value of 0xfebfffff. That region would overlap
the MMIO region at 0xe0000000-0xefffffff. For rangeley
the upper bound of the PCI memory space should be set
to 0xe0000000 - 1.
The MCFG regions for several of the affected chipsets are:
rangeley 0xe0000000-0xefffffff
baytrail 0xe0000000-0xefffffff
haswell 0xf0000000-0xf3ffffff
sandybridge 0xf8000000-0xfbffffff
TEST = intel/mohonpeak and intel/bayleybay.
Change-Id: Ic188a4f575494f04930dea4d0aaaeaad95df9f90
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/9972
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Commit e2c2bb9 (dmp/vortex86: move PLL config to cpu Kconfig)
failed to properly restrict the PLL config selection to that cpu,
resulting in the selection option being present/required for all CPUs.
Fix by guarding the Kconfig options with if/endif.
Change-Id: Ifecf291b985ab9d0d13d6b1264d3bc9a314b8546
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10038
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
As the first step in adding support for FSP 1.1, add common header files
for EDK2. Internally FSP is based upon EDK2 and uses the defines and
data structures within these files for its interface.
These files come from revision 16227 of the open source EDK2 tree at
https://svn.code.sf.net/p/edk2/code/trunk/edk2. These files are
provided in an EDK2 style tree to allow direct comparison with the EDK2
tree.
Updates may be done manually to these files but only to support FSP 1.1
on UEFI 2.4. A uefi_2.5 tree should be added in the future as FSP
binaries migrate to UEFI 2.5.
Note: All the files were modified to use Linux line termination.
BRANCH=none
BUG=None
TEST=Build for Braswell or Skylake boards using FSP 1.1.
Change-Id: Ide5684b7eb6392e12f9f2f24215f5370c2d47c70
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/9943
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Remove dependency of Haswell on cpu/intel/socket_rpga989 code,
which is a carry-over from Sandy Bridge/Ivy Bridge and older
coreboot conventions where features were structured around socket types.
Add CPU-specific options to Kconfig and required subdirs to
Makefile.inc which are curently included with socket_rpga989.
TEST=successfully built and booted on google/panther
Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10037
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
So don't try to use it elsewhere.
Change-Id: Ia600ba654bde36d3ea8a0f3185afae00fe50bfe9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10030
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The build system includes a bunch of files into verstage that
also exist in romstage - generic drivers etc.
These create link time conflicts when trying to link both the
verstage copy and romstage copy together in a combined configuration,
so separate "stage" parts (that allow things to run) from "library" parts
(that contain the vboot specifics).
Change-Id: Ieed910fcd642693e5e89e55f3e6801887d94462f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10041
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
That's a Haswell exclusive, used nowhere else, but confusing
when hunting for the monotonic timer used on that SoC.
Change-Id: I60ec523e54e5af0d2a418bcb9145de452a3a4ea9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10034
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SPI flash drivers need it.
Change-Id: I63d79472d70d75f7907e7620755c228d5a4918e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10033
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Builds with CHROMEOS fail due to missing includes.
Change-Id: I8c88bca8f8cc3247d3f3311777f794c4fdfee3c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10029
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The ChromeOS machines employing vboot verfication require
different combinations of support:
1. When vboot verification starts.
2. Is the vboot code a separate stage or program?
3. If a separate stage, does the that vboot program (verstage) return
to the stage that loaded the verstage?
For the above, #1 is dependent on when to load/run vboot logic which
is orthogonal to #2. However, #3 is dependent on #2. The logic
to act on the combinations follows in subsequent patches.
Change-Id: I39ef7a7c2858e7de43aa99c38121e85a57f1f2f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With vboot1 out of the way place all the associated Kconfig
options in vboot2's Kconfig file (excluding main vboot verify
option). More options will be added to accomodate vboot's various
combinations of use cases.
Change-Id: I17b06d741a36a5e2fefb2757651a61bfed61ae1e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10023
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Add a way for a loader to indicate if it is active. Such users
of this callback would be vboot which can indicate to the rest
of the system that it isn't active. is_loader_active() also
gives vboot a chance to perform the necessary work to make
said decision.
Change-Id: I6679ac75b19bb1bfff9c2b709da5591986f752ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10022
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The GTT location is documented in the "309219" datasheet.
For instance it can be found in the TOLUD register description.
The 309219 datasheet is for the
"Mobile Intel® 945 Express Chipset Family". It was published in 2008.
Change-Id: I75ac095ebc577e031af566963ebffe9ed2587c96
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/9622
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In the true spirit of separating components more strictly
and allowing to add new components to coreboot without touching
existing code, move Intel common code selection to the soc
Kconfig and out of src/soc/intel/common/Makefile.inc
Change-Id: I0a70656bb9f4550b6088e9f45e68b5106c0eb9af
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10031
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add additional FSP timestamp values to cbmem.h and specify values for
the existing ones. Update cbmem.c with the FSP timestamp values and
descriptions.
BRANCH=none
BUG=None
TEST=Build for Braswell and Skylake boards using FSP 1.1.
Change-Id: I835bb090ff5877a108e48cb60f8e80260773771b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10025
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add identifers and descriptions for the FSP areas within CBMEM.
BRANCH=none
BUG=None
TEST=Build for Braswell and Skylake boards using FSP 1.1.
Change-Id: I4d58f7f08cfbc17f3aef261c835b92d8d65f6622
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10026
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The memory layout isn't very clear here, since there are two
regions (bootblock and "SRAM") that are actually the same.
So when increasing the bootblock's size, we also need to move
the romstage around.
Change-Id: Ib158a4ef96b7c1dd1132b6e8bd47a0eb9c3951d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This change switches all northbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in northbridge/Makefile.inc or in
northbridge/<vendor>/Makefile.inc.
This means, vendor and northbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: I8468154dbfaaaffcba9fda27ba2d7b9049ad5c19
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9800
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change switches all SOC vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in soc/Makefile.inc or in
soc/<vendor>/Makefile.inc.
This means, vendor and SOC directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9799
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change switches all ECs and the generic EC ACPI code
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in ec/Makefile.inc or in
ec/<vendor>/Makefile.inc.
This means, vendor and ec directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9798
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This moves the vortex86ex cpu's pll configuration out of the mainboard
and into the cpu's Kconfig.
Change-Id: I72ee1baa3a96586fceff03ff43c5f61e2498667e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/9058
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
There were some remaining places that used __PRE_RAM__ for
romstage, while it really means 'bootblock or romstage'.
Change-Id: Id9ba0486ee56ea4a27425d826a9256cc20f5b518
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10020
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The second step in adding support for FSP 1.1 is to add the header
files.
Updates may be done manually to these files but only to support FSP 1.1.
An FSPx_y tree should be added in the future as FSP binaries migrate
to new FSP specifications.
The files are provided in an EDK2 style tree to allow direct comparison
with the EDK2 tree.
BRANCH=none
BUG=None
TEST=Build for Braswell or Skylake boards using FSP 1.1.
Change-Id: If0e2fbe3cf9d39b18009552af5c861eff24043a0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/9974
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Consolidate the FspNotify calls into the FSP driver directory,
using BOOT_STATE_INIT_ENTRY to set up the call times.
Change-Id: I184ab234ebb9dcdeb8eece1537c12d03f227c25e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/9780
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Remove Kconfig files that are no longer used:
src/vencorcode/Kconfig
src/soc/marvell/Kconfig
- Fix the drivers/sil/Kconfig to point to drivers/sil/3114 which had
the same code.
- Make sure all Kconfig files have linefeeds at the end. This can cause
problems, although it wasn't in this case.
- Include cpu/intel/model_65x/Kconfig which was not being included.
Change-Id: Ia57a1e0433e302fa9be557525dc966cae57059c9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/9998
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is not used together with SMM_MODULES.
Change-Id: I52621787cfa5a9e3863c150ce64f62aceb423eb4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10014
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Do not unconditially supply verstage rules for all
platforms.
Change-Id: Ic0713350aa21a9966fca828211750d25c2b6b71d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9969
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This file was moved previously to get it out of the way
for easier merging from the chromium repo. It's not used
currently so remove it.
Change-Id: I8e691623f29ac2218b83bc46f5b4a348e0e1b3ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9960
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
These options will need to just be selected in within
the .config files. There's not need in duplicating all
these options.
Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9959
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There's no need to have the VBOOT2_VERIFY_FIRMWARE
distinction because it's the only game in town.
Change-Id: I82aab665934c27829e1a04115bf499ae527a91aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9958
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In preparation for moving to vboot2 for all verified
boot paths bring over Kconfig options to the common
area from vboot1. Also remove vboot1 directory entirely.
Change-Id: Iccc4b570216f834886618f0ba5f2e1dd6c01db4b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9957
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If verified boot is enabled, merge verstage into bootblock. This also
requires custom bootblock code to actually call into verstage.
[pg: modified to match upstream]
BUG=chrome-os-partner:32631
BRANCH=ToT
TEST=booted on cosmos development board.
Change-Id: I53251aac966ee15da24232c23fefa636de8b253b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2b8ada263017b46afa755b5acb759574184dba06
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Ia0e1236357aa32bf553fb8cc98f3a8d29de17f45
Original-Reviewed-on: https://chromium-review.googlesource.com/229795
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10008
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This slightly streamlines integrating the vboot2 library and
prepares for merging verstage and bootblock on selected devices.
Change-Id: I2163d1411d0c0c6bf80bce64796e1b6a5a02b802
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Otherwise it won't build.
Change-Id: If9e1435b0dc8bfe220b3a257976e928373fbc9a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10003
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Without this, building with COLLECT_TIMESTAMPS fails.
Fixes a mistake during upstreaming in commit 0de8820.
Change-Id: Ie56bd38649a821f6b22a1e5dee5f50ef397035fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10002
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The offset of 0x2000 was for a configuration with two separate OxPCIe
chips. The setup we support is a single chip with 8 UART pors.
Change-Id: If4be046a14464af7b90b86aca5464c6b3400dffc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8780
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Move the GPI interrupt routing selection between SMI/SCI from
mainboards to southbridge. There is speculation if this is all
just legacy APM stuff that could be removed with a followup.
Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7967
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb)
programming to use GPI1 between SCI/SMI modes, while
previous programming was for GPI12.
Change-Id: I3ac0feaa1d10c8f0e53a5fa5af72366503bb5d2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change switches all southbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in southbridge/Makefile.inc or in
southbridge/<vendor>/Makefile.inc.
In order to be able to drop southbridge/amd/Makefile.inc, some
scattered source files had to be moved to a southbridge/amd/common
directory, in accordance to what we are doing on other architectures
already.
This means, vendor and southbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9796
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Long auto-increment access cannot be used when our initial address is
misaligned or when our terminal address is misaligned on write
operations.
BUG=chrome-os-partner:38224
TEST=Verify host command functionality on cyan.
BRANCH=None
Change-Id: Ieba0e8e05dabd44a28c63d5d56a2a634c2d349bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7237c8df027ae70a38478846ff3d5ce97543ff1
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: Id709ca92cc386f9ea5b2a1139733961e1bc59354
Original-Reviewed-on: https://chromium-review.googlesource.com/266653
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9987
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch enables on storm the recently introduced 'console buffer
dump on reboot' capability.
BRANCH=none
BUG=chromium:475347
TEST=generated storm image with serial console disabled and both rw
firmware A and B sections corrupted. Programmed the new image on
an SP5 device and rebooted it. Observed the device dump cbmem
console buffer to the serial output, terminating with
VB2:vb2_fail() Need recovery, reason: 0x3 / 0xa
Reboot requested (1008000a)
Saving nvdata
SF: Detected S25FL128S_256K with page size 10000, total 2000000
and the LED ring started flashing indicating recovery mode.
Change-Id: Idb50c86f59f393c783ccbc15de8f5564e2a1b38e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ec88001b152bb9f1d7268b83367131b004816f8
Original-Change-Id: I9345eeb4d375f42fb1e4c617495b63b308ce51d9
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/265295
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9986
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The new function can be compiled in only when serial console is
disabled.
When invoked, this function initializes the serial interface and dumps
the contents of the CBMEM console buffer to serial output.
BRANCH=none
BUG=chromium:475347
TEST=compiled for different platforms with and without serial console
enabled. No actual test of this function yet.
Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579
Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/265293
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9984
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It returns TPM_E_NO_DEVICE for all calls.
BRANCH=None
BUG=None
TEST=manual MOCK_TPM=1 emerge-foster coreboot, and
coreboot can boot to kernel
Change-Id: Id7e79b58fabeac929b874385064b2417db49a708
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a9a91a65af115657e7317754eda931120750c56d
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Change-Id: I8dcf0db14cf2bc76c67a3bd7f06114e70e08764d
Original-Reviewed-on: https://chromium-review.googlesource.com/264946
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9983
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In the spirit of include what you use actually #include
the header necessary for fmap calls.
Change-Id: I7acede51d7139234c0520281799dad3a8d33454f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9968
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The value of SMM_TSEG_SIZE was equal to SMM_RESERVED_SIZE. This caused
the install_permanent_handler() function to fail. Changed the value to
0x800000, which is already used as default in smm_region_size() in case
SMM_TSEG_SIZE is 0.
Change-Id: I4ff3568aefd4729a98c1777a2cae2a4715afbc2f
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/9961
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
CPTR_EL3 and CPACR_EL1 are the registers for controlling the trap level
and access right of the FPU/SIMD instructions. Need to save/restore them
in every power cycle to keep the settings consistent.
BRANCH=none
BUG=none
TEST=boot on smaug/foster, verify the cpu_on/off is ok as well
Change-Id: I96fc0e0d2620e72b6ae2ffe4d073c9328047dc01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 73e8cc8f25922e7bc218d24fbf4f7c67e15e3057
Original-Change-Id: I51eed07b1bb8f6eb2715622ec5d5c3f80c3c8bdd
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/266073
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: http://review.coreboot.org/9981
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Implement the individual core powerdown sequence as per
Cortex-A57/A53/A72 TRM.
Based-on-the-work-by:
Varun Wadekar <vwadekar@nvidia.com>
BRANCH=none
BUG=none
TEST=boot on smaug/foster, verify the cpu_on/off is ok as well
Change-Id: I4719fcbe86b35f9b448d274e1732da5fc75346b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b6bdcc12150820dfad28cef3af3d8220847c5d74
Original-Change-Id: I65abab8cda55cfe7a0c424f3175677ed5e3c2a1c
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265827
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9980
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This patchs introduces level specific data cache maintenance operations
to cache_helpers.S. It's derived form ARM trusted firmware repository.
Please reference here.
https://github.com/ARM-software/arm-trusted-firmware/blob/master/
lib/aarch64/cache_helpers.S
BRANCH=none
BUG=none
TEST=boot on smaug/foster
Change-Id: Ib58a6d6f95eb51ce5d80749ff51d9d389b0d1343
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b3d1a16bd0089740f1f2257146c771783beece82
Original-Change-Id: Ifcd1dbcd868331107d0d47af73545a3a159fdff6
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265826
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9979
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Same as commit fe0eac5f416e "arm64: Allow cpu specific early setup", we
need the same in secmon too.
BRANCH=none
BUG=none
TEST=boot on smaug/foster
Change-Id: I5b1347880306a95f99233db12cb99547bad4aa8c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f70fd940ff92eb5b8991cd777c2894b7a9633cf
Original-Change-Id: Ifce5a6d636051e7a447d055c8e09ed4e29e091c7
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265825
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: http://review.coreboot.org/9978
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Call arm64_cpu_early_setup to allow cpu-specific initialization to be
performed. Also, add support for setting SMPEN bit for cortex a57
within arm64_cpu_early_setup.
BUG=chrome-os-partner:38222
BRANCH=None
TEST=Compiles successfully and SMP works for foster
Change-Id: Ifa4e6134dbce3ad63046b3dd9b947c3d9134d5e7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe0eac5f416efcf9f7b05388a17444205a8352c0
Original-Change-Id: I28a05a20e6adf084cd0bf94bdd0c3b492632107c
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/262993
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9977
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Fastboot data in Intel FSP project is printed by hexdump32() in dword
length. So the data length needs to be divided by 4 when printing it.
Change-Id: I959d538bd6e60282882dd138045cc730b4bd8159
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/9976
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific
directory. See follow-on patches for sharing of common code.
Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/9970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In commit b0d8f5e9 I moved the call to cbmem_initialize()
in the CONFIG_EARLY_CBMEM_INIT case to the very beginning of
ramstage. However, that caused an issue in the ordering of the
cbmem console driver in that it expects cbmemc_init() to be
called prior to cbmemc_reinit(). Therefore, ensure console
is called as the first thing even if some time is lost w.r.t.
timestamp tracking.
Change-Id: I42137d28116e0bccb9235f4e3f394d4fd8b84e37
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9933
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The Kconfig options pertaining cbmem console in the preram
environment no longer make sense with the linker script
changes. Remove them and their usage within cbmem_console.
Change-Id: Ibf61645ca2331e4851e748e4e7aa5059e1192ed7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9851
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This enables its _size variable (a macro) to work even when
the console has no location assigned to it in the chip/board's
memlayout.ld.
Since _size == 0, the code will do the right thing.
Change-Id: I6b42ed0c5c3aaa613603680728b61cbdb24c4b61
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9973
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To simplify browsing the "Supported hardware" list, I added Release year
for the hardware from asus, asrock, gigabyte, msi, via, tyan, intel,
lenovo, apple, jetway and hp. Still several models and manufacturers to
add information to. This is more of a proof-of-concept.
The "Release year" will be shown in the wiki page.
Change-Id: I6bc14ed06ac7c6b3c9f054b49f08cb9b3dc47947
Signed-off-by: Mathias Friman <mathias@workplays.se>
Reviewed-on: http://review.coreboot.org/9963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Add a new mainboard based on AMD's Family 15 Model 30 processor.
TEST: Lamar will boot DOS, Ubuntu 14.10 and Windows 7.
Change-Id: I2f73c396247239d54f978846e8958950697d7464
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5968
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
By design, the imd library still provdes dynamic growth so that
feature is consistent. The imd-based cbmem packs small allocations
into a larger entry using a tiered imd. The following examples show
the reduced fragmentation and reduced memory usage.
Before with dynamic cbmem:
CBMEM ROOT 0. 023ff000 00001000
aaaabbbb 1. 023fe000 00001000
aaaabbbc 2. 023fd000 00001000
aaaabbbe 3. 023fc000 00001000
aaaacccc 4. 023fa000 00002000
aaaacccd 5. 023f9000 00001000
ROMSTAGE 6. 023f8000 00001000
CONSOLE 7. 023d8000 00020000
COREBOOT 8. 023d6000 00002000
After with tiered imd:
IMD ROOT 0. 023ff000 00001000
IMD SMALL 1. 023fe000 00001000
aaaacccc 2. 023fc000 00001060
aaaacccd 3. 023fb000 000007cf
CONSOLE 4. 023db000 00020000
COREBOOT 5. 023d9000 00002000
IMD small region:
IMD ROOT 0. 023fec00 00000400
aaaabbbb 1. 023febe0 00000020
aaaabbbc 2. 023feba0 00000040
aaaabbbe 3. 023feb20 00000080
ROMSTAGE 4. 023feb00 00000004
Side note: this CL provides a basis for what hoops one needs to
jump through when there are not writeable global variables on
a particular platform in the early stages.
Change-Id: If770246caa64b274819e45a26e100b62b9f8d2db
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9169
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
elog breaks the build if ELOG_FLASH_BASE isn't configured -
and CHROMEOS isn't enabled, since with Chrome OS builds, it
just uses fmap to find out the base.
So it makes sense to enable it on all Chrome OS builds - if
the code never uses it, the linker will drop it soon enough.
Change-Id: I7ee129fadf75caf15fb9bd32b0acf6f7d9d015d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9965
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of switching off the LED ring for the normal boot path, turn
it on with the dedicated pattern, indicating that the device firmware
has started executing.
BRANCH=storm
BUG=chrome-os-partner:39044
TEST=program the new firmware on an SP5 device and verify that the new
'normal boot' pattern is displayed in all following scenarios:
- power up the device (the pattern shows within the first second)
- boot the device to bash prompt and restart.
- press the recovery button and reboot the device. Once the LED ring
shows the 'recovery button pressed' pattern, release the recovery
button.
Change-Id: Iedd66d2575ad587af77e35d23efb22a83a92858b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 092358bd17a323d0bd2fec555f43cb587486bbec
Original-Change-Id: I24de45326eab83b57bcf16b5598388f81c7d0f00
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/265536
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9923
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It became necessary to indicate the beginning of the normal boot
process. This patch adds a new pattern, a slow (over 2 seconds) fade
in into the 0, 87, 155 color.
BRANCH=storm
BUG=chrome-os-partner:39044
TEST=tested by the next patch.
Change-Id: Idd977688e5aa2cc55fc295072c0766526ae95016
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 577c8bd6f8c69073cfdd7acd4a87e7ae603d48e6
Original-Change-Id: I9aff3f4558e733ff2e47206075533556e400f183
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/265535
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9922
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
After testing on a final assembly the PD team adjusted the wipeout
request and recovery request modes' colors.
BRANCH=storm
BUG=none
TEST=verified new colors while booting an SP5 device in recovery mode
Change-Id: I9bd2dac63b99140573533c2cda8eaa9213478ab1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41c34a619dc0317af67907f18ee844c71a73d623
Original-Change-Id: Iab84710ebdeed35ddd4a8a163bbb6b8ac9cdb799
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262602
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9890
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Modify colors as suggested by product review folks. This is not final,
to make it easier to identify RGB locations in the hex dumps, express
their values in decimal as opposed to hex.
BRANCH=storm
BUG=chrome-os-partner:36059
TEST=verified new all three color schemes while pressing the recovery
button at boot for 20 seconds.
Change-Id: I7461acd7004e3d10cba6665a9bfe25ec8aa6f3ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a075824a1954eb5d1b65ce887304924724a6d21
Original-Change-Id: I7f5968e361333572fd1f84aa11b7150194ad902a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/261690
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Storm and whirlwind devices should leave developer mode as soon as
recovery is requested.
BRANCH=storm
BUG=chrome-os-partner:36059
TEST=with the rest of the patches applies observed desired behavior on
SP5
Change-Id: I3e8e481f85cd067eff4fe2049b8aa47e09f6d63e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c6dbafc16edb11ec687359b25098ce8a1b055b91
Original-Change-Id: Iac6fa62229556bc7a6960d7f1630d37570ba72c4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/261621
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9879
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Aaron Durbin