This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.
BUG=None
BRANCH=None
TEST=Build and boot tglrvp.
Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch adds psys_pmax calculation. There are two types of power
sources. One is barrel jack and the other is USB TYPE-C. The voltage
level is fixed for a barrel jack while TYPE-C may vary depending
on power ratings. We need to get voltage information from
EC and calculate correct psys_pmax value. The psys_pmax needs to be
set before FSP-S since FSP-S will handle the setting passing to pcode,
so move the routine ahead to variant_ramstage_init.
BUG=b:151972149
TEST=emerge-puff coreboot chromeos-bootimage
check firmware log and ensure psys_pmax is passed to FSP
check the data from dump_intel_rapl_consumption in the OS and
ensure the power data is close to an external power meter.
Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Support USB Chicony user facing camera.
BUG=b:155109736
BRANCH=None
TEST=Build and Boot waddledoo board and able to capture image
using user facing camera.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I7580a58086977e239dca49c1def4f03583831662
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This CL selects the PcieRpClkReqDetect for the required root ports
which is needed to allow proper clksrc gpio configuration.
Also, sets the unused PcieClkSrcUsage to 0xFF.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe
Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe
Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
smbios_slot_{type,data_width,length,designation} used for smbios_type_9 needs "smbios.h"
Also use already defined 'smbios_type11' in "smbios.h".
This will also include <smbios.h> in "static.c" file, this we can remove indirect includes of
<smbios.h> in "chip.h"
Change-Id: Id412a504da2fd75648636febd150356569e07935
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40310
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The stuffed resistor straps are weaker compared to the internal pull-up.
This can cause the GPIO to read '1' always. Remove the internal pull-up.
Also read the GPIO only on the boards where the board version is
populated.
BUG=b:154301008
TEST=Build and boot the mainboard.
Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update DPTF settings for smooth fan speed control.
BRANCH=firmware-hatch-12672.B
BUG=b:154074920
TEST=Built and test on Helios system
Change-Id: I3f4d9fd9e17541dd5fb7982a8b43a039c41cba87
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1. Add support as per the schematics
2. Add 2 Ports and 2 Endpoints
3. Add support for OTVI8856 and OTVI5676
4. Add ON and OFF logic as Power Rails are same for both sensor
BUG=None
BRANCH=None
TEST=Build and Boot waddledoo board and able to capture image
using world facing camera.
Change-Id: Ic8687bce4896d9fc17b2190b8d11618af3515cc1
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The QEMU XHCI driver does not implement the Port Change Detect bit
in the USBSTS register. As a result no devices are attached without
looking at each port individually.
Detect this as a quirk based on the QEMU XHCI controller PCI ID,
and apply it to the root hub quirk list so it can get used by the
generic hub driver to skip this check.
With this change an attached USB mass storage device is detected and
able to boot when supplied to qemu:
-drive if=none,id=usbmsc,format=raw,file=/tmp/disk.img
-device qemu-xhci,id-xhci
-device usb-storage,bus=xhci.0,drive=usbmsc
Change-Id: I6689cb1dbb24c93d45f5c5ef040b713925d07588
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39839
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update usb2 port strength parameter for usb2_port[0] to improve SI.
BUG=b:154668734
BRANCH=firmware-hatch-12672.B
TEST=Built and checked SI margin of USB2 ports
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add support to generate ACPI operations to get/set/clear RX/TX GPIOs.
BUG=b:152936541
TEST=Build and boot the mainboard. Ensure that there are no errors in
the coreboot logs regarding unsupported ACPI GPIO operations.
Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update UPD IIO bifurcation at run-time according to different Riser
cards. For detail please reference
Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types.
With the engineering build FSP, it can only configure IIO for
one socket so my local test needs to remove all socket1 elements
from tp_iio_bifur_table.
This change relies on [1] and need to add GPP_C15 and GPP_C16 to
early_gpio_table for gpio configuration in bootblock.
[1] https://review.coreboot.org/c/coreboot/+/39427/
Tested=OCP Tioga Pass can see socket0 IIO being updated with
an engineering build FSP.
Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The gpio.h file with PAD_CFG macros was
automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership
register only affects the pads that are configured as input. The
intelp2m utility takes this into account when converting macros and
ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643
[2] Intel Document Number: 549921
Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40736
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We should be sure that after romstage the pads will be configured
according to the config from gpio.h only. This patch sets the GPIO
configuration from gpio.h using the soc/intel/common/gpio.c driver
again in ramstage.
[1] https://review.coreboot.org/c/coreboot/+/40730
Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with vendors firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:
./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643
Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
-n needs to check against a string, but if CONFIG_TIANOCORE_BOOTSPLASH_FILE
is unset, then $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) evaluates to nothing
and the check fails, leading the Makefile to try and copy a non-
existant file/path.
Change-Id: Iff717dd48748cff16f485bafaa91c7a225fb5bdb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Most payloads, like GRUB, SeaBIOS and Linux, are able to initialize the
PS/2 keyboard themselves, so coreboot does not need to initialize it.
Therefore, this option should not be hard-coded for the mainboard, and
be left for the user to select.
Change-Id: Ibfb7efa22c525e60399afc198af6632330faaac3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since commit 6aa8c5bc (drivers/pc80: Do not initialize PS2 keyboard by
default), the Kconfig option `DRIVERS_PS2_KEYBOARD` already defaults to
`n`. So, remove it here, as this option should be user selectable
anyway depending on the payload.
Change-Id: I3d08fb6bbb3e9d53fd2fed96f26679e8b1e73f8c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Most payloads, like GRUB, SeaBIOS and Linux, are able to initialize the
PS/2 keyboard themselves, so coreboot does not need to initialize it.
Therefore, this option should not be hard-coded for the mainboard, and
be left for the user to select.
Change-Id: Iac835d2e7a3232f8e5c76f10984ae3f172f9c0ca
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change enables support for em100 for Picasso platform. Since
em100 requires lower SPI speed, this change configures speed in all
modes as 16MHz.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that em100 works fine on trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40825
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds options to allow mainboard to configure SPI speed for
different modes as well as the SPI read mode.
BUG=b:153675510,b:147758054
BRANCH=trembyle-bringup
TEST=Verified that SPI settings are configured correctly for trembyle.
Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a helper sb_spi_init() that makes all the required
calls for configuring SPI to ROM.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic5b395a8d3bdab449c24b05d1b6b8777e128b5e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40824
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds enums for spi_read_mode and spi100_speed in
preparation for adding these to chip.h in follow-up CLs. This makes it
easier to reference what the mainboard is expected to set for these
SPI configs.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
southbridge.h does not really need chip.h. So, this change removes the
inclusion of chip.h from it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I09c87b975ecd5f7798da8dd858be0c729aef42de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40822
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 285975dbba.
Reason for revert: VB2_RECOVERY_TRAIN_AND_REBOOT was never meant to have
any special effect on memory training behavior. It was just supposed to
be a "reboot automatically after reaching kernel verification" recovery
reason. On x86 devices this was used to prime the separate recovery
MRC cache in the factory (make sure it is initialized before shipping).
This isn't used on Kukui anyway, but in order to make sure nobody copies
this code and keep the behavior consistent between platforms, let's
remove it.
Change-Id: I5df5e00526e90cb573131de3c8bac9f85f4e3a5f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40623
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable aspeed's function that port 80h direct to GPIO for LED display,
refer to section 9.4 Port 80h Direct to GPIO Guide of aspeed's
Application Design Guide, also configure GPIO to UART for output
serial console messages.
Tested=Check if port 80h LED debug card can display POST codes at
early stage, and serial console can see the related messages.
Change-Id: I087d5a81b881533b4550c193e4e9720a134fb8e7
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40481
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:152893285
BRANCH=none
TEST=Build and boot to OS volteer with Intel SATA and reboot
from OS console
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Create the trondo variant of the volteer reference board by copying the
template files to a new directory named for the variant.
BUG=b:154678884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TRONDO
Change-Id: Ie4f9bfe4798e14f91c6cb439f5c5ab2b9ea52b51
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40686
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on USB SI report to fine tune the strength for USB2 port0.
BRANCH=none
BUG=b:153590143
TEST=build and test USB2 port0 function works fine.
Change-Id: I070c9e1c8153a680fb8f827889738a764d7ea9f4
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
memcpy() is meant to be used on normal memory and often implemented with
architecture-specific optimizations to make that as performant as
possible. MMIO registers often have special access restrictions that may
be incompatible with whatever memcpy() does. For example, on arm64 it
uses the LDP (load pair) to load 16 bytes at a time, which makes 4-byte
MMIO registers unhappy.
This patch removes the caching of the XHCI capreg registers and changes
it back to a pointer. The CAP_GET() macro is still accessing a full
(non-bitfield) uint32_t at the end so this should still generate a
4-byte access (which was the goal of the original change in CB:39838).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id058c8813087a8e8cb85f570399e07fb8a597108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
It seems that all SC7180 boards we have can well handle 37.5MHz of SPI
flash speed, so bump that up from the current 25MHz so that we don't
leave boot speed on the table. (The next step would be 50MHz which
currently doesn't work on all boards so we're not going there yet.)
BUG=b:117440651
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Check SPD is not NULL before print. This can prevent the system
from hanging up.
BUG=b:154445630
TEST=Check NULL SPD is not print.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iccd9fce99eda7ae2b8fb1b4f3c2e635c2a428f04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40560
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like 5 is a valid system type, as Google Beltino and Slippy are
using it. According to comments on these mainboards' code, this value
corresponds to ULT systems. So, add it to the comment on the pei_data
struct, which was likely copied from Sandy Bridge and was not updated.
Change-Id: I3654bb6022839dba3e1499cf43e8beaa97d1def1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This change adds a Kconfig option PSP_UNLOCK_SECURE_DEBUG which
when enabled includes secure debug unlock blobs and sets the required
softfuses and options for amdfwtool. By default this is set to 'N'.
BUG=b:154880818
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Meera Ravindranath