Coreboot generic CBFS media API does not support
multiple media access instances, but it should.
With this fix the CBFS context (memory cache for
SPI accesses) is shared among all open media access
streams. A better memory management scheme might be
required, but for now this fix allows to support
booting deptcharge and accessing VPD through two
independent CBFS media streams.
BUG=chrome-os-partner:32152
TEST=no exception is thrown when the second stream
is opened
Change-Id: I62889089b4832c9e9760ef24ecc517220d8f3ec4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 691f9794805d04beff349f1bc60ac9d7530d7cbf
Original-Change-Id: Ib9d9d1f5209c2e515a95d7acbf4a8ac1255d3f8a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219441
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8897
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We don't set these by default in upstream.
Change-Id: Ida7aa498e0fe291c6cf3cf31d6516530a9d136d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Includes moved into $(CPPFLAGS_*), so add that to VBOOT_CFLAGS.
Shift vboot build parameters from the environment to be make parameters,
and use $(MAKE) instead of make to fix non-Linux build systems.
Change-Id: I5aee9935ab36ad571fbcf9f6fa8d8ace2bac16b3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8703
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Depending on the needs of the mainboard certain regions of the address
map may need to be adjusted. Allow for that.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With ryu patches able to insert a non-cacheable memory region.
Change-Id: I68ead4a0f29da9a48d6d975cd41e2969db43ca55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88342562885b09c4350ba1c846b725b5f12c63d9
Original-Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212161
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=None
BRANCH=None
TEST=Built rush and ryu, ran on rush into recovery mode.
I2C6 is in the SOR domain, so a lot of further init is
needed before it can be used. A follow-on patch will do this.
Change-Id: I5701bfcf1d0bb8c6edd3d885b1b7dd14e67ba73a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 69908f2489d1a918bb109d43e713932214741b46
Original-Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212671
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8940
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Able to get sporadic USB communication in depthcharge on ryu.
Change-Id: I6bf6559d167a6ea94523d2500b54c1c7854330f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e5412cfc149902298f2ebeb3030d8f09f27e5ee8
Original-Change-Id: Ic5402d18943c3cc8fb4556c47e587134633fbf72
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212333
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Continuing down the path of easing mainboard maintenance
provide a way to bring up the USB 2.0 ports through funit.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=With ryu patch was able to get same sporadic USB communication.
Change-Id: Ic75821acf1d48a9f1659849fa007251c61658640
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5183c5081a95219f84c4d6dfca70926b383abc1a
Original-Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212332
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8938
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With non-cacheable memory region and dma range addition, booting from usb
reaches the same point as mmc.
Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd
Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211039
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8937
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The clk_rst.h file wasn't including files that had
functionality it was using resulting in broken builds
if just this file was included.
BUG=None
BRANCH=None
TEST=Built with just this file included -> no more errors.
Change-Id: I229cb3890f1320edc3bc3e82469b301cbaff0f72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03b455aa9da64d6e110690206db65939ca023c27
Original-Change-Id: I8dc0fcab363e1089587e6dc8ff04c2a76c5e364c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212331
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8936
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Make sure the array size matches the number of supported
FUNITs. Also remove the FUNIT_NONE enumeration so that
there isn't an empty slot in the array at index 0.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built when array wasn't large enough. Compiler threw an error.
Change-Id: I1b83ddff799a56ea39efa23a91dca1a9e0f10862
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4cbe74905bbeb815e9f20bcc0fad3751a3133b04
Original-Change-Id: I0bb37c51311d202729b7fb9731d6eec0a28dc040
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212330
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To provide easier access to the base addresses of the controllers
by funit identifier add the base addresses to the data structure.
BUG=chrome-os-partner:31251
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built.
Change-Id: I427d432beef36e6342c188d607c0e33b3845c0e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c8f09e61e3dbfbc96980b98ad25e09554fd49a8d
Original-Change-Id: Iff5564b250dcf2038252d54a4caec3df5f7f3de7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212169
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8934
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide consistently named base address enumerations as well
as provide some that were missing.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built.
Change-Id: I2551bbaa83d1d2c158b87d239098c22fba4d3961
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07954a231f3c11c4102f9db0a2d35654abda208f
Original-Change-Id: I75030598f7da7dacf8e8eff1d7427c5bf202814f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212168
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8933
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to prepare for USB initialization move the clock
configuration into a separate routine in the funit library.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted into recovery mode.
Change-Id: I090b5d12c5805f0179c29cfc62499fad2f245c01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f7adaf969762b8296034f4373f550a902d1ed06b
Original-Change-Id: Iea6cd2fbe8369a91c06b15d94b63c409ae83124f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212167
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8932
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Just use direct pointers to the registers in the pre-filled
data structures. In 64-bit the sizes increase, but it's small.
The fields now directly point to the correct register so no
need to do any arithmetic to identify the correct register.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted on ryu into recovery.
Change-Id: I0de85c486c005aed23b6118ec91b45dd39acdfb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 358b78c1c4cb72e0166f91b36011676e65576666
Original-Change-Id: I186bf5d145437472126067960e62d7ed6a25f295
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212166
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8931
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use the new funit API to do all the dirty work.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through depthcharge and into recovery just like
before.
Change-Id: I8625a06dd847bd3dcfc3ce5a50a31d6aff0b860f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebc04a174269ae072eda804e172fd24362f417d2
Original-Change-Id: Ief2d81c5569c33a90fc9458d741edef1dcbd8239
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212152
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently rush needs a DMA region in order to communicate with
USB devices. Therefore, add that region to the memory map.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With the changes for adding non-cacheable memory range and adding DMA
region, booting from USB reaches same point as MMC.
Change-Id: I82d97840fad8cc96bf958c6efa13d2fdc1233d79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b182651a1b6db1a7adbf315b6865467590a0785c
Original-Change-Id: I6a465eaa77e0d5ab4d5fb22161e88e7a5fd9c4a8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212193
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Pull out the common usb setup utmip functions from t124 into tegra usb.h. These
can be reused for t132 as well.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Compiles successfully for nyan, big and blaze
Change-Id: Idddd40e409b56875436db6918d05f2889d83870b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12f12cb30a033cce645f53457d13a987aeec22a1
Original-Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211200
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8927
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently ryu needs a DMA region in order to communicate with
USB devices. Therefore, add that region to the memory map.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With usb added am able to talk to a USB mass storage device
albeit inconsistently.
Change-Id: I7efaf2ba44cc94dc64af3f1cd916bdc5c7ff0795
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e93389479518ee28dc3477da0c6e6e33fa8a47d1
Original-Change-Id: I6b5c052ccaafce30705349e07639dffbb994901f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212162
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8926
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Non-cacheable normal memory is needed when one wants an easy way
to have a DMA region. That way all the reads and writes will be
picked up by the CPU and the device without any cache management
operations.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With a bevy of other patches can use a carved out DMA region
for talking to USB.
Change-Id: I8172f4b7510dee250aa561d040b27af3080764d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a5bc7ab1709edd97d8795aa9687e6a0edf26ffc6
Original-Change-Id: I36b7fc276467fe3e9cec4d602652d6fa8098c133
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212160
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8924
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The high address field was being shifted in the wrong direction
resulting in the lower 12 bits of the upper address being dropped.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Was able to run on ryu and not hang while wiping memory.
Change-Id: If1d7ef1c63ce79c143af3c5012b206ee297cd889
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6b0da6fa391db2ec2bc1e0bec9325f4e74b5286c
Original-Change-Id: I7bf173bb0373d2d25ce9014c80236fb55cc8e17e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211941
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/8923
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use funitcfg api for bootblock, romstage as well as ramstage
initialization in rush.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully and boots till last known good point.
Change-Id: I243597de9ec13904a2bb58a04b402f9545424760
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0618ea6828bae3e700b85b79b185aec28568b8ae
Original-Change-Id: I8f5801c1c214f05ef9d2ba976838605da2d8b914
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211766
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8922
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This api provides a common interface to initialize various clock sources,
dividers as well as enabling the clock for various functional units.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully for rush and boots till last known good point.
Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3
Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211765
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Two changes: 1. A44 ID straps use different gpio pins than nyan.
2. A44 uses tristate values instead two state values.
BUG=none
BRANCH=none
TEST=Built and tested on A44 board.
Change-Id: I6a36f6da0c9f6168780606ba76595c7a0af8e8bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2eb0cae0e3396da1eaeaa72411c4b74300138a7b
Original-Change-Id: Ia2a4309d3b63b0a94d79465dd727b01fae01e1b9
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211753
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
nyan blaze fails to boot because tristates of the board id are interpreted in
the reverse order. this change fixes it.
BUG=none
TEST=Booted Blaze to Linux. Built firmware for Storm.
Branch=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I4ff8a15cf62869cea22931b5255c3a408a778ed2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3f59b13d615a8985edf2029d89af05e95aefad33
Original-Change-Id: I6d81092becb60d12e1cd2a92fc2c261da42c60f5
Original-Reviewed-on: https://chromium-review.googlesource.com/211700
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: http://review.coreboot.org/8980
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The name was changed due to review comments misunderstanding, it
should be restored to properly convey what the function does.
BUG=chrome-os-partner:30489
TEST=verified that Storm still properly reports board ID
Change-Id: Iba33cf837e137424bfac970b0c9764d26786be9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c0fff28c6ebf255cb9cf9dfe4c961d7a25bb13ff
Original-Change-Id: I4bd63f29afbfaf9f3e3e78602564eb52f63cc487
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211413
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8979
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current 2 boards were setting up clocks and enabling
peripherals that apply to the SoC generically. Therefore,
move the common pieces into the SoC code.
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and booted through depthcharge on ryu.
Change-Id: I94ed4b5cc4fafee508d86eefe44cf3ba6f65dc3b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dad573c8689b79bb4aa615811a10f44e7d8c809
Original-Change-Id: I6df1813f88362b8beaf1a716f4f92e42e4b73406
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211191
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/8917
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The I2C pads connected to the EC are pulled to 3.3V. Therefore
the pads need to be configured as open drain.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and booted through depthcharge on ryu
Change-Id: Ie5eadfe6aca78eb31fbca4e8d8117d1061acbbec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1530e7e7f500be47355eada56591ac2dbf1e9326
Original-Change-Id: Ia4ad2377d01296235fc7efbba72fa790016c04af
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211135
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8916
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Ryu's EC talks proto v3 over i2c. Select the correct protocol.
BUG=chrome-os-partner:31148
BRANCH=None
TEST=Built and ran on ryu. Coreboot can speak to the EC now.
Change-Id: Iaed0d2db3c3c93667d65beea98b9719bdbbbfe41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b71cad3bb1e9b64c48b6f2eeb7573c408a508fb3
Original-Change-Id: I50e192cd58f7a29103ab94afc002da18822d4080
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211240
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8915
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the supporting Kconfig options and infrastructure for
performing vboot firmware verification.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Built and ran on ryu into depthcharge noting vboot paths
being taken.
Change-Id: I1d803208cd5789bd73244b91beac6a5a4598ea70
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a2e7d84725739843a1ed1868fcadebb60477a6dc
Original-Change-Id: Ie4c8c3939990a12fc528423948b236230392eb7c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211134
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8914
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The original intent was to set the equivalent flags by default
for the PAD_CFG_* macros so as not to make the usage too chatty.
The GPIO_INPUT variant didn't have the PINMUX_INPUT_ENABLE field
set. Therefore, automaticaly set it for PAD_CFG_GPIO_INPUT().
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran on ryu.
Change-Id: Iab058874314430de08010912c3fc758a98b73eb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 535cdb354efc067caf32d32641846f11fb0cd2ee
Original-Change-Id: Ifb630601cf04d2984542933382aace16540863ad
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211133
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8913
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The tegra132 SoC provides the monotonic timer API. Therefore,
ensure the reset of the coreboot infrastructure is aware.
BUG=None
BRANCH=None
TEST=Built and ran on Ryu. Noted that ramsgage is showing timings
for each bootstate.
Change-Id: Ifc2d5b7eb318ffac0ad79bfbc3d1b61a7ba4b10c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b691572c63a43a01a290f1c00f71097028d1415e
Original-Change-Id: I9b8fcf38cba9bdaaf0455701df1d6328bf1927c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211132
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8912
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
coreboot already has a reset API. Utilize it by selecting
HAVE_HARD_RESET. The tegra132 boards have to provide the
hard_reset() implementation as that involves board-specific
bits. The tegra132 code then provides a cpu_reset() routine
that just promotes that call to a hard_reset().
For the existing tegra132 boards remove the unnecessary files
from the build.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Ensured hard_reset() does something on Ryu.
Change-Id: I6d5aa928fec95b361175e35e0a26812829ffdfc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31edd4ff7486ded87d2525cd360d48959b6aef7c
Original-Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211131
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Now that there's a working udelay() in tegra132, upclock
CAM_I2C and SPI1 to the same speeds as used on Nyan.
BUG=chrome-os-partner:30998
BRANCH=rush_ryu
TEST=Built Rush and tested, no nack errors seen.
Change-Id: If1ee6d5c711252e294818d6263732bb34b2fe6f0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 859c0d4fde2cf098cb829e96a5d6dec394bea600
Original-Change-Id: I58fd03ed3512c2498c793cfe30b0c302e4b0e3d4
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211043
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8910
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The gpio_index_to_port() incorrectly was dividing by
GPIO_PORTS_PER_BANK on a value including the bit number. After
masking off the BANK offset just divide by the number of gpios
in a port to get the port offset.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through to depthcharge. Printed bank, port, and
bit numbers for validation.
Change-Id: I3fbbb90f369bace90e787148a58795b7b1b40c1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97e1f830b4a8e948673433bfa6d81586204b6ee2
Original-Change-Id: I8bb50e922c9fd7c0a1c247ba95394f6deb9f1533
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210909
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8908
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I erroneously added GPIO_NONE_INDEX at the beginning of the
enum block effectively putting every GPIO index off by 1.
Instead, move it to the end.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through to depthcharge on rush. Also
printed out banks, port, and bit offsets to validate.
Change-Id: I4f6510c1b6fcdddddbe36ff738299b4439ffc597
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c020c2125b9a2378a7faa17209d1b78e019c7df
Original-Change-Id: I0471480e8658de9e534beb859a1f5027a961d73e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210908
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8907
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It's helpful to be able to track this information. Therefore
dump it in to the console log.
BRANCH=None
BUG=chrome-os-partner:31126
TEST=Built and ran on rush. Revision information is put out on the
console.
Change-Id: I22e7d222259c1179b90edda6d7807559357f6725
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18d318331b696a6a32e0a45b8f903eb740896b02
Original-Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210903
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8905
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are used by the LPDDR3 code in sdram.c.
Based on the schematic and email, I've filled in 4 slots
in sdram_configs.c. My A44 returns RAMCODE 0 (using only bits
1:0) for Samsung SDRAM. I haven't tested the other 2 types of
RAM (Hynix and Micron). The 4th slot is a fallback slow Micron
config.
Previously existing configurations were dropped.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: I55a737db269fe5fac1565d58bd8f8afcbc5beecb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9a431466171a85a5c8151e7466eb5f77862e7b44
Original-Change-Id: If216096ffc9e9836b6d082ad0668640b3eec37b7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: a45e7788dd78697ac5f48b6cc64108ca0e4912dd
Original-Change-Id: Ib7e8b814eb6dadb9b366536721876a3eeba0d2c0
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216000
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of calling out with function names all the possible
combinations of interface and device provide one call to the
mainboard to configure all the necessary bits.
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and ran on rush.
Change-Id: Id7817e85065884d64f90ac514bf698bf539f2afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4f63f5965d403a32872d7b52c180694f5ef679d
Original-Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210838
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8901
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Rush has its EC on SPI, and Ryu has it on I2C, so need both
mainboard_init_ec_spi and mainboard_init_ec_i2c in both builds,
due to romstage.c being in the common tegra132 subdir.
BUG=none
BRANCH=rush_ryu
TEST=Built both rush and rush_ryu images OK. Will try to
boot on Ryu later.
Change-Id: Iddbf9e9f6de7ba7244f9dd2e810fb6178937c85a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d8b81717c366d19b43964bed3c4047598db4495
Original-Change-Id: I48d9530697d5669177ecd9ba3c34360197002003
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210595
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This resolves an issue where large sections of the cbmem logs
were being dropped on AMD Fam10h boards.
Change-Id: I0e4e86e169aa4f20f06472f1a6e3136705ae4f9d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8851
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The cbmem console output retains usage of the CRLF line ending.
Converting line endings to the standard UNIX LF avoids the
need to use dos2unix before running analysis on log files.
Change-Id: I74a04ee69836d82640c94f250465acb4d1ee1071
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8857
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
I broke cbfs loading with commit 358901. As multiple
functions are being reused one needs to ensure there is
always a cbfs media object allocated on the stack and
initialized. Ya for no common writable globals.
TEST=Ran qemu-armv7. CBFS loading works again.
Change-Id: Ibd047af7dcd8575e6203651471079fc2042da282
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8973
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Switch over to the padconfig API for bootblock PAD configurations.
Aside from support code, each entry is 4 bytes. The open coded
calls were 12 bytes each.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built for ryu.
Change-Id: Iff981509f258c8fe7bbc2e24ce87bad0c43a55b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8a7ee469124eeb6d05b978b5e68a2fc03b102f47
Original-Change-Id: I2d32d702da38bc0d87a1c159113bba32f4c03407
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210837
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8879
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Switch over to the padconfig API for bootblock PAD configurations.
Aside from support code, each entry is 4 bytes. The open coded
calls were 12 bytes each.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran on rush. Observed consistent results.
Change-Id: Ibfa6fc188a7c503cfad41420ed50c7a88fdec579
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2245478f8e21167e93a6e97b12730788a7f927ae
Original-Change-Id: I1d5d38322bda6740a0ea50b89f88b722febdee22
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210836
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of hard coding certain pieces of a board in the common
chipset code provide a way to initialize things early in the
bootblock path. Add a bootblock_mainboard_early_init() function
before console init to performany necessary mainboard initialization
early in the bootblock.
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BUG=chrome-os-partner:29981
BRANCH=None
TEST=built both on rush and ryu. rush still behaves the same.
Change-Id: Idcf081eeffd189a4e2cbfeb8a4ac5dd0a3d1f838
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a523add6de03bea0d88e95b9dbb5e283c629400
Original-Change-Id: I7d93641dff3a961f120e8f0ec2d959182477ef87
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210835
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8877
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Start using the soc_configure_pads() API. This allows for
bulk processing of pads.
BUG=chrome-os-partner:31105
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and can get console messages on rush.
Change-Id: Id2c8a685a4566bda8fc260f74f5dffdd0da03056
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bbd7c81bc0777b38bb641b9fcf89425bfd93566d
Original-Change-Id: Iaa6a6ff4d559aedb98b078e87b0ecddefd3402d6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210834
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8876
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of sprinkling the pad configuration and pinmux
selection throughout the code allow for a data-driven
initialization sequence. Most of the calls in the
original pinmux functions require 12 bytes per pad
plus the support code. This implementation allows for
4 bytes per pad in addition to the support code.
BUG=chrome-os-partner:29981
TEST=Built and booted into depthcharge on rush.
Change-Id: I22c243a5f9891a97e14b78d8c8064e36adaf50b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9329c17bbadcaab803b38842e38e1704d262817d
Original-Change-Id: I3a119b4068e880b74a0a1597f143d7c4e108a6c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210833
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8875
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
this change syncs the i2c driver with the one in depthcharge.
BUG=None
TEST=Booted Veyron Pinky
BRANCH=None
Change-Id: Ic9c7006770bba50fd412e0bcefc52f879b7195ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Id: 95ca6c88061062c0de95a8dd3567a71a372771b0
Original-Change-Id: I0d0fdefa58c5b4cc5c991be40796a800ccf074a5
Original-Reviewed-on: https://chromium-review.googlesource.com/218873
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8872
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The Rk808 PMIC is a part that will probably be used by most Rk3288
boards, so it makes sense to keep it as common code in the the SoC
directory. This patch puts LDO control functions into rk3288/rk808.c, so
that the mainboard only has to call a simple interface to set up the
specific LDOs it requires.
BUG=chrome-os-partner:30167
TEST=Booted both this and the old version with a stubbed-out
i2c_writeb(), ensured that the final values are the same.
Change-Id: I7efa60f8a357ce6be7490e64d2e0e3f72ad16f1c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4df22cd78ee04fefc6f7fa0e5c3d903eb1794422
Original-Change-Id: Ic172f9c402e829995f049726d3cb6dbd637039d1
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217598
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8871
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This patch adds code to read the board ID from Pinky and put it into the
coreboot table.
(Note: This implementation differs slightly from Tegra since it pinmuxes
the GPIOs inside board_id(). That means the pinmuxing might be set more
than once if called in multiple stages, which is perfectly harmless and
in my opinion cleaner than having to (remember to) do it manually in one
of the per-stage files.)
BUG=chrome-os-partner:30167
TEST=With depthcharge patch, select -rev1 device tree for board ID 0.
Change-Id: I265fafcb176a31a46f7792ecf352f1671be7dd41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9da10ce8b62ec98243fc7c82544b3004316799a8
Original-Change-Id: I5b5689373e1e47b1e0944b5fe5f2e70a285b931f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217675
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8870
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
We retroactively decided to use the variant name "pinky" for the Rk3288
board we're currently bringing up, and retcon the unadorned "veyron"
name to refer to the Rockchip evaluation board. Since we currently have
no interest to maintain coreboot support for that board in our tree,
let's rename everything to "veyron_pinky" and forget about "veyron".
CQ-DEPEND=CL:217592
BUG=chrome-os-partner:30167
TEST='emerge-veyron libpayload coreboot' fails but
'emerge-veyron_pinky libpayload coreboot' succeeds.
Change-Id: I88bf5cc2da7c2f969ea184b5f12affaa94045a06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aa8ec24b63d11798fec1993091b113a0c0938c7a
Original-Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217674
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8869
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some files for the veyron project were checked in with execute
permissions where it doesn't make sense. Fix.
BUG=chrome-os-partner:30167
TEST=None
Change-Id: I2a96816d4fd0af3949b0adaf5208fd2862835b5b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7a408ff273d848b60aaad4f8b27103318e56111
Original-Change-Id: Ia3788abf3755baf028518efb975701cf6cb37e46
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217673
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8868
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz.
ddr timing config file in src\mainboard\google\veyron\sdram_inf
Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz).
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321
Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209465
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8865
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I23af280764eb28d3f6b215ab32553fe42ee73272
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: abf5c14c8b32573107d2a1c73a752e740264db7e
Original-Change-Id: I46257cc71cc3cd1e867edf589ddf09f7990d6784
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209462
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8863
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I74b30ecfe40c039855b835db0dfd0cd25adf960e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a30378a3152c930029a5b170cc6bf46180b5c7b8
Original-Change-Id: I5105e5277b8072c06bb41b39479373697ef81c67
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209468
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8860
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
In order to display a "update in progress" screen on devices with
a slow EC or PD chip it may be necessary to also load the VGA
Option ROM when doing EC software sync.
This adds config options for VBOOT_EC_SLOW_UPDATE which simply sets
a flag in the input parameters that is already handled by vboot.
It also adds a config option for VBOOT_OPROM_MATTERS which is a bit
more tricky in that it sets a flag in input parameters, but also
needs to keep track of the option rom being loaded and pass that
flag into VbInit as well.
Since VbInit will clear the NV bit for option rom loaded the check
that is done in vboot_wants_oprom() needs to first compare against
the vboot handoff copy of the input flags.
BUG=chrome-os-partner:32379
BRANCH=samus
TEST=manual testing:
1) in normal mode, with EC/PD in RW, ensure that they are rebooted
to RO and the VGA Option ROM is loaded and the wait screen is
displayed, and then the system is rebooted at the end and the
VGA Option ROM is not loaded.
2) same as #1 with EC/PD in RO already, same result
3) same as #1 with system in developer mode, same result except
there is no reboot at the end of software sync
4) same as #1 with system in developer mode and EC/PD in RO,
ensure that there is no extra reboot at the beginning or end of
software sync.
Original-Change-Id: Ic2b34bf9e7c6cc5498413fa1b8dff6e6207c9d0a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223831
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 7d7aa89238efb5081885f9386c8e872fc96f573f)
Change-Id: Ib7fb24e6e80e1f7e836bc62246ab9b3e056fd73d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
this change makes coreboot initialize kernel space and backup space in the tpm
when no firmware space is found in the tpm.
BUG=chrome-os-partner:32410
TEST=Forced factory initialization and verified it went through without errors.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I777e3cb7004870c769163827543c83665d3732b9
Original-Reviewed-on: https://chromium-review.googlesource.com/220412
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit d8c0c407bf0fed60d76441ada7bedd36f6fc3a38)
Change-Id: Icc3779125262b4499e47781991ebbf584abf074a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
this change makes prevent execution from falling through to unverified
code when hard_reset is not implemented. it also includes a few touch-ups.
BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Original-Change-Id: I9b02ab766172a62c98b434c29f310bc4a44f342d
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219625
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit d1f5207d83d2247b55f2bb9d02ac843305fc3ded)
Change-Id: I99dd5a2ca3a5369accb14408ea9d266bf60e7132
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over
the bootblock, then exits to the romstage. this is necessary for some SOC
(e.g. tegra124) which runs the bootblock on a different architecture.
With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock.
Then, the bootblock loads the romstage over the verstage and exits to the
romstage. this is probably necessary for some SOC (e.g. rockchip) which does not
have SRAM big enough to fit the verstage and the romstage at the same time.
BUG=none
TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544
Original-Reviewed-on: https://chromium-review.googlesource.com/212365
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Note: This purposefully is probably broken in vendorcode/google/chromeos
as I'm just trying to set a base for dropping more patches in. The vboot
paths will have to change from how they are currently constructed.
(cherry picked from commit 4fa17395113d86445660091413ecb005485f8014)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9
Reviewed-on: http://review.coreboot.org/8881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
this change reduces the code duplication of the bootblock and the romstages for
Nyans.
BUG=none
TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri)
Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a
Original-Reviewed-on: https://chromium-review.googlesource.com/214050
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef
Reviewed-on: http://review.coreboot.org/8880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This introduces a new kconfig variable to select the VBNV backing
store explicitly instead of inferring it from CPU/SoC architecture.
x86 platforms have historically relied only on CMOS to store VBNV
variables, while ARM-based platforms have traditionally relied on
the EC. Neither of those solutions are going to scale well into
the future if/when CMOS disappears and we make ARM-based systems
without an EC.
BUG=chrome-os-partner:29546
BRANCH=none
TEST=compiled for nyan_blaze and samus
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I4a8dadfb6bb666baf1ed4bec98b29c145dc4a1e7
Original-Reviewed-on: https://chromium-review.googlesource.com/213877
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit d088fc71b2e2b45e826d3dedb8e536ad58b8d296)
Change-Id: Iea325a8c4d07055143e993d89b827f86b8312330
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8777
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
rmodules ccopts contain information about specific arch like armv4,v7. Hence, it
is important to include them in VBOOT_CFLAGS
BUG=None
BRANCH=None
TEST=Compiles correctly for armv4 in rush
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id:
Original-Change-Id: I8f5509f753e28046678c3782d6f0b6210559f798
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209979
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit ca9f2f86ff1bc445abf5f97f61c04b6eccbd3e25)
Change-Id: I6cd7c47f33cf897d8ee96e7154222b3bfbe5221f
Reviewed-on: http://review.coreboot.org/8775
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to more cleanly apply upcoming changes some files
will need to do a dance.
Change-Id: Ib50670743c10221785447490190ecdbff8c764fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8654
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This code ports antirollback module and tpm library from platform/vboot_reference.
names are modified to conform to coreboot's style.
The rollback_index module is split in a bottom half and top half. The top half
contains generic code which hides the underlying storage implementation.
The bottom half implements the storage abstraction.
With this change, the bottom half is moved to coreboot, while the top half stays
in vboot_reference.
TEST=Built with USE=+/-vboot2 for Blaze. Built Samus, Link.
BUG=none
Branch=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I77e3ae1a029e09d3cdefe8fd297a3b432bbb9e9e
Original-Reviewed-on: https://chromium-review.googlesource.com/206065
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
(cherry picked from commit 6b66140ac979a991237bf1fe25e0a55244a406d0)
Change-Id: Ia3b8f27d6b1c2055e898ce716c4a93782792599c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8615
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
These boards are supposed to be able to determine the board ID at run
time based on GPIO settings.
BUG=chrome-os-partner:30489
TEST=verified that all boards build. Checked that storm proto0 reports
board ID of 0 on the console
Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210119
(cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733
Reviewed-on: http://review.coreboot.org/8722
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
storm uses three GPIOs in tertiary mode, such that proto0 returns
value of 8 when the GPIOs are interpreted as a single tertiary number.
Adjust the calculated value to return board ID of 0 on proto0, and
monotonously incrementing values on newer boards.
BUG=chrome-os-partner:30489
TEST=when enabled, the board ID value of zero is reported on the console.
Original-Change-Id: I2ff8fd5cbc8d568877b6f8bf220e146893f1e4be
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210118
(cherry picked from commit 6ba24f31583933f02be111c8767ae9df56537011)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I35ee218df35a0924d4bb8fcbc6c875450a609f24
Reviewed-on: http://review.coreboot.org/8721
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For the majority of Chrome OS boards there is no need to include board
ID calculation in any stage but ramstage, where the ID should be
available for inclusion into the coreboot table.
BUG=chrome-os-partner:30489
TEST=build only, no other tests yet
Change-Id: I1451d52382bc48cc126d40267e0f61712f4a6d4b
Original-Change-Id: Ib9c06698a399d31e79a9b14143343ba2ad46d0fb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210117
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 27dd40e85bfcd0a38f388bad4d79f5fbb77a7566)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8720
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Board ID value is usually of interest to bootloaders. Instead of
duplicating the board ID discovery code in different bootloaders let's
determine it in coreboot and publish it through coreboot table, when
configured.
BUG=chrome-os-partner:30489
TEST=none yet
Change-Id: Ia1e36b907ac15b0aafce0711f827cb83622e27bb
Original-Change-Id: Iee247c44a1c91dbcedcc9058e8742c75ff951f43
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210116
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit b2057a02db9391e2085b138eea843e6bb09d3ea2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8719
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add implementation of the GPIO API defined in src/include/gpiolib.h.
Also, clean up the GPIO driver, make it use pointers instead of
integers for register address.
This requires a touch in the SPI driver, where the CS GPIO is toggled
and in the board function where it enables USB interface.
BUG=chrome-os-partner:30489
TEST=tested with the following patches, observed proto0 properly read
the board ID.
Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210115
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2
Reviewed-on: http://review.coreboot.org/8718
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Some platforms use tertiary interpretation of GPIO input state to
increase number of distinct values represented by a limited number of
GPIOs. The three states are
- external pull down (interpreted as 0)
- external pull up (1)
- not connected (2)
This has been required by Nvidia devices so far, but Exynos and
Ipq8086 platforms need this too.
This patch moves the function reading the tertiary state into the
library and exposes the necessary GPIO API functions in a new include
file. The functions are still supposed to be provided by platform
specific modules.
The function interpreting the GPIO states has been modified to allow
to interpret the state either as a true tertiary number or as a set
two bit fields.
Since linker garbage collection is not happening when building x86
targets, a new configuration option is being added to include the new
module only when needed.
BUG=chrome-os-partner:30489
TEST=verified that nyan_big still reports proper revision ID.
Change-Id: Ib55122c359629b58288c1022da83e6c63dc2264d
Original-Change-Id: I243c9f43c82bd4a41de2154bbdbd07df0a241046
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209673
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c79ef1c545d073eaad69e6c8c629f9656b8c2f3e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8717
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bootblock stack on Danube should be SRAM and defined separately from
the rest of the coreboot stack. The actual coreboot stack will be
defined later.
The top of the stack should be above the bottom, as the stack grows
towards lower addresses.
BUG=chrome-os-partner:31438
TEST=ran bootblock on simulator under codescape, observed stack
properly initialized.
Change-Id: I43d2bae5f85a09a95ca0103b253399bd92555aef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e02724cb4b30990ebaa631dabb45917af29d6437
Original-Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218732
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add basic board support for the ImgTec Danube Virtual Platform, which
emulates a system built around the Danube SoC.
Run this by loading coreboot.bimg into a flash device connected to SPFI1
chip select 0 & then executing the Danube boot ROM.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: Ia62af62804bab261f3cabf7c2e62f5bb08a4a1a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6cb1017f5e2fec85f7f5c60cd2cfec63cc886b49
Original-Change-Id: I7a2b52f304bcb4b614440ec38975e05f38b0e590
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207976
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8766
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Actual timer support is not yet available for Danube, it will be added
soon. For now, just to make the target build, modify it to use
GENERIC_UDELAY and HAVE_MONOTONIC_TIMER configuration option.
BUG=none
TEST=the target builds again
Change-Id: Iad1ceb966d5dbc8687b966be4d2506c8f92eba5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 261837539fb5a31f96e682edbcbbbc0e588f2750
Original-Change-Id: Ie3289eace9d2baadd01bd641b5dffc635ac80c0f
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220395
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8765
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Romstage initialization code does not need to be board specific, keep
it in the SOC directory. Should there be a need for the board specific
code, it can be added later.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: Ib619fa9313d463ded13e9259e50bb5aeaab4fb05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c08977aaa5e9b5da29359d1920d7d8b61ce86d3
Original-Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215992
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Iniitialize I2C bus required for TPM operation. Problem observed was that if
frequency is raised above 20KHz, TPM starts responding with NAKs either for
address or for data. Need to look into that.
BUG=None
BRANCH=None
TEST=Compiles successfully and TPM success messages seen while booting.
Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210001
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2
Reviewed-on: http://review.coreboot.org/8715
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable L1 Sub-State when both root port and endpoint support it.
[pg: keyed the feature to MMCONF_SUPPORT, otherwise boards
without that capability fail to build.]
Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092
Original-BUG=chrome-os-partner:31424
Original-TEST=Build a image and run on Samus proto boards to check if the
settings are applied correctly. I just only have proto boards and
need someone having EVT boards to confirm the settings.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a
Original-Reviewed-on: https://chromium-review.googlesource.com/221436
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There was an empty udelay() implementation result in 0 waits.
Provide an actual implementation.
BUG=None
BRANCH=None
TEST=Built and ran through to depthcharge on rush.
Change-Id: Ia7060566a71c36bb7e4543c2fe4ee49d168518c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c8832e73de238358ea801ccd7c2330de35a7b40e
Original-Change-Id: I201f2fdc4e4f5c88d48e4002839b03e808a5a1bc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210827
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8830
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=Built, but similar usage tested on tegra132.
Change-Id: I1147f2bed84b93d1b776205df9ae04d1db9c98a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c38e054dd166d5eb53f692833b5ce88a230816e3
Original-Change-Id: I6d3f3da4e035e872890d8b67947b17a981673dba
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219712
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8819
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of open coding the monotonic timers use the stopwatch
abstraction.
BUG=None
BRANCH=None
TEST=Booted and noted timings work as expected. Built with software_i2c
and no compilation failures.
Change-Id: Ie5ecdd5bc764c1ab8ba4a923e65a1666aacd22f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7bffb5aeb41e9b88cd2c99edd6abc38f1dc90af
Original-Change-Id: I0170fe4b93d9976957a2dcb00a6ea41ddc0320ce
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219495
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8817
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Simplify the SPI timeout by using the stopwatch.
BUG=None
BRANCH=None
TEST=Built nyan. Confirmed stopwatch works independently.
Change-Id: Ida26a0748d4b5a6a28aa8f6e2b92fe2ee4cbe17f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 900d7ac826b76d49290033c87849bf776684f2c1
Original-Change-Id: I84b7949060326b7c6cc1872420b93bd44604c4d3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219493
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There's a lot of places where expiration and running time are
open coded. Allow for those places to be simplified by adding
a stopwatch construct. The stopwatch can have an expiration or
just be used to accumulate time.
BUG=None
TEST=Built and verified API works as expected by using implementation.
Change-Id: Ibd636542b16d8554f1ff4512319a53dce81c97e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc623a1b36eb08c5877591c4509cd61131c62617
Original-Change-Id: I53604900fea7d46beeccc17f1dc7900d5f28518b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219492
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8815
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These modules are necessary to resolve external names when building
the board image. These are just skeletons for now which will be filled
later.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: I0fcb5d33187172ecac77041425402b33e89e8944
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94ec79b0ab872f5c5fe7db5bef5fdabf77d6b3b6
Original-Change-Id: I69cc178976a910ebf8031ed9ac9ad67b4cc0878a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215678
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add build infrastructure and basic support code for the ImgTec Danube
SoC. This support is sufficient to run on a simulator.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I59e36589765bf06b075fd4850215a0ef71246bb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 881278d7fbb8e6803bc8f6f9e84c64640b097401
Original-Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207974
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8762
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With the proper configuration flags enabled, do_printk is available
from src/console, no need to define it elsewhere.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: I82071b4ca1686639c0bd39c63a06b61cb5bf5571
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 69c655537c50274a61cf123b7fc387ec60dd29c7
Original-Change-Id: Ib1e3e5750cdc1adc509b4580a4f24d3ff3b105ee
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215862
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8761
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the build infrastructure and basic architectural support required
to build for targets using the MIPS architecture. This is sufficient
to run on a simulator, but will require the addition of some cache
maintenance and timer setup in order to run on real hardware.
BUG=chrome-os-partner:31438, chromium:409082
TEST=none yet
Change-Id: I027902d8408e419b626d0aab7768bc564bd49047
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcc0d934d7223922c878b1f87021cb5c2d7e6f21
Original-Change-Id: If4f99554463bd3760fc142477440326fd16c67cc
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207972
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8760
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As MIPS toolchain does not provide adequate support for 64 bit
division and shift operations, the missing functions are required to
be provided by the user.
This patch brings in the Linux implementation of the 64 bit arithmetic
shift borrowed from arch/mips/lib/ashldi3.c (eg. Linux v3.14).
BUG=chromium:406038
TEST=With the upcoming patches coreboot successfully builds for MIPS
targets in chroot (coming later).
Change-Id: I2168f69352a9b9e3c5d197489f701a442e65703c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ec616161be8ad3aeb6494e7121615e3329b414d
Original-Change-Id: Ia1ccb29d4c9f3c95e04e06f6af7ce8a00e2e7455
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214156
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8759
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Certain boards need to speak proto v3 over i2c. Leverage the
transport agnostic API to share the logic with other proto v3
impelementations.
BUG=chrome-os-partner:31148
BRANCH=None
TEST=Built and ran on ryu. Can talk to the EC successfully.
Change-Id: I1d0cd6907057af4ded3c4460193bbe1d897a1db7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb9ac965ad04c9491f40fd9aa595176a28a467b3
Original-Change-Id: Ib699120fd232392e8caa0889c2bf40f4587a8a35
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211139
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Depending on the transport mechanism for proto v3 different bytes
need to be send and/or read before the request and response. Depending
on the software and/or controller interface that requirement leads to
needing to copy data into temporary buffers. Avoid this by allowing
the transport mechanism to provide the request and response
buffers.
BUG=chrome-os-partner:31148
BRANCH=None
TEST=Built for rush and ryu. Ran on ryu with i2c implementation.
Also built for rambi to check x86 systems.
Change-Id: I35d4d69bd1fa900fc0cfe3822496f381405bdcb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7224426e1d0bcf06ed010131a2462a6ca201d8b
Original-Change-Id: Iad6cce566a253ca72e6f5009a97235ece0a6c1b5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211138
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8827
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EC doesn't return any data when one performs a write to
VBNV context. Therefore there is a mismatch of expectations.
Correct this by properly setting the expected response length.
BUG=chrome-os-partner:31148
BRANCH=None
TEST=No longer hanging while writing to VBNV on ryu.
Change-Id: I7077a507c3280358dac1f88ece62cacee9b71bea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c1735c3377163aeb9e90155cb9f081a1eea919c9
Original-Change-Id: I455724f20f5442bd62a792f09273227417475f07
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211137
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8826
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It's helpful to view program size by inspecting the symbols.
_start and _end exist on romstage and ramstage. In order to
be consistent add _end for bootblock too.
BUG=None
BRANCH=None
TEST=Built and noted bootblock has _end symbol.
Change-Id: I06634b317e957e8271bf32530a56b5541c79b9ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4ac926b30749d22e90a6f12ebac52107e241526
Original-Change-Id: I7f0b4dd4078c7d23c70949563b4c3f4df9e66142
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210832
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In some cases, we need to use 1 common VGA device ID to share
among different VGA devices.
But it will show error when it can't find a specific pci rom
by PCI DID.
in fact, it will find the pci rom with common vga ID.
Without this commit, you may need to skip error check during
suspend_stress_test
BUG=none
BRANCH=none
TEST=build OK, and check no error on Auron and Samus
Change-Id: I2b18347e46c831038f048cfd0b065430c72c6f30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c32ee21b4c942182e5ffb21b58b93fa7c082223
Original-Change-Id: Ib743e960f772b7e2e73a1feb80790a13bd8c06c7
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217415
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: http://review.coreboot.org/8821
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It causes fan top speed due to this bug + our board-specific workaround,
and causes invalid temperature sensor readings.
Therefore, re-configure the register "External Temperature Sensor Host
Control Register" to terminate processes when this issue happens.
BUG=chromium:402204
TEST=ran suspend_stress_test 500 times
Change-Id: I439d5de798fbe999e4eec5497e6969b7b453121b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b82f2922c7fce3ca6b2797a8d9775e9db2817fe9
Original-Change-Id: I6e71b6a46a31b00e541c304f1ed58c1678c1d42e
Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219445
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/8820
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When adding gargabe collection to x86 the --gc-sections
flags was inadvertently missed when linking romstage_null.debug.
Fix this omission.
Change-Id: I7d2700755afa78459c6f8707303a0e64936a1a9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8850
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Instead of sprinkling the cbfs calls around (as well as getting
return values incorrect) use the common run_romstage() to perform
the necessary work to load and run romstage.
Change-Id: Id59f47febf5122cb3ee60f9741cfb58cb60ccab5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of sprinkling the cbfs calls around (as well as getting
return values incorrect) use the common run_ramstage() to perform
the necessary work to load and run ramstage.
Change-Id: I37b1e94be36ef7a43efe65b2db110742fa105169
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8710
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide a common run_romstage() function to be used by
bootblocks to load and run romstage. This is similar to
run_ramstage() in that it provides a single entry point
for doing the necessary work of loading and running romstage.
Change-Id: Ia9643cc091f97a836cf5caefdff8df4a3443df4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8709
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Miraculously a console is being compiled in for romstage.
However, as no calls were potentially printing to the preram
console this was being ignored. Instead provide the symbol
required so as not to fail the build.
Change-Id: Id8f0b6e6d15b41fa7fe1b63bf2d91f15baa0edda
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8712
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of two headers for payload and ramstage loading
combine the 2 files into one. This also allows for easier
refactoring by keeping header files consistent.
Change-Id: I4a6dffb78ad84c78e6e96c886d361413f9b4a17d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8708
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Vboot2 targets so far did not have COMMON_CBFS_SPI_WRAPPER
configuration option enabled, so the verstage is missing the relevant
files in some Makefiles. This patch fixes the problem.
BRANCH=none
BUG=none
TEST=with the rest of the patches applied cosmos target builds fine
with COMMON_CBFS_SPI_WRAPPER enabled
Change-Id: I3ce78c8afc5f7d8ce822bbf8dd789c0c2ba4b99c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b72693c96f7d8ce94ce6fe12b316d5b88fded579
Original-Change-Id: Iab813b9f5b0156c45b007fe175500ef0de50e65c
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223751
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8772
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
GD25LQ64C and GD25LB64C have the same ID and settings.
BUG=chrome-os-partner:25907
BRANCH=baytrail
TEST=Boot with GD25LQ64 and check MRC data save/restore works.
Change-Id: I8a4aa7cabd9a7657c2f0bae255a87341db3f1061
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20b5896adbbbdedcb1b7de435466dcc6bfa703cb
Original-Change-Id: I86d1e69552b6000faa9e0523356e27d7e2a6a6db
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193238
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8770
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This allows us to use the driver before ramstage.
BRANCH=none
BUG=none
TEST=built and booted on Pinky
Change-Id: I0700388b0e4e0562e3c0a52863c8357097bfd8d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cd57587dab74de509d5c50cfc1ad337d765af6c8
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I0ce901331e401274254b8889484ffb41359119fa
Original-Reviewed-on: https://chromium-review.googlesource.com/235864
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8774
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When the driver is included in bootblock, malloc() is not available.
Come to think of it, it is perfectly fine to use a statically
allocated structure for the SPI device descriptor - coreboot is
unlikely to require concurrent support of multiple SPI devices of the
same kind.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=bootblock on the FPGA board recognizes the installed Winbond
device:
coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting...
SF: Detected W25Q16 with page size 1000, total 200000
Change-Id: Iea1936a219d38848580a10f75eb8bbcab17e6507
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0b4082442aa526d387a80cb5872d78670e6b468b
Original-Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228959
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8771
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
S25FL116K family uses the first 3 bytes in response to a legacy identification
command (9f) while previously supported models use the last 4 bytes. This change
defines identify functions to allow both types to be handled correctly.
BUG=none
BRANCH=tot
TEST=verified romstage is loaded on cosmos development board.
Change-Id: I1970a9af17e81299fada5029724d405de4022156
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 65ff436db2355cb68a766a3dedbcd7e2f765e6db
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Icdd2645e356652672c4482e7b805da1bc0f21e71
Original-Reviewed-on: https://chromium-review.googlesource.com/234431
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a macro to check if a value is aligned.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: I0680954eb1b1964a631527f96aa0570a32944fa1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f1717648e0a4b54217d71f8d0a15d496737d156
Original-Change-Id: Ie0bc1374918a7ffaaec5fea62c1193a42edd416c
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246692
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8757
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
mainboards/amd/fam10: Initialize cbmem area after raminit
When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE
When GFXUMA is disabled, CBMEM is placed at TOM
This matches the behaviour present before conversion to early
CBMEM.
The CBMEM location code implicitly assumes TOM does not change
between romstage and ramstage. TOM is set by romstage raminit,
and is never changed by romstage or ramstage afterward. As
the CBMEM location is positioned at a specific offset from TOM
that is known to both romstage and ramstage early CBMEM is safe
on Fam10h systems.
TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp
tables from romstage and cbmem log tables from ramstage.
Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8489
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Our target is to get rid of backup_top_of_ram() and get_top_of_ram()
entirely so only declare these with LATE_CBMEM_INIT=y.
Change-Id: I54f549fe774996f4d803f9ec527e0fac46f6576f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8749
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA
is enabled, however when GFXUMA is disabled an attempt was made to locate
the CBMEM memory segment above the I/O hole in certain rare cases.
Removing this special case does not impact functionality, and paves
the way for early CBMEM support.
Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The AMD RS780 early initialization code originally used the
CF8/CFC I/O method for PCI configuration space access. After
the default configuration access method was changed to MMIO
(http://review.coreboot.org/#q,aad07472), booting would hang
at "PCI: pci_scan_bus for bus 01". Fix the problem by changing
function rs780_nb_gfx_dev_table() so that it no longer borrows
the BAR3 address needed for PCIe MMIO config usage.
Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8394
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The GCC 4.9.2 update showed that the boot_state_init_entry
structures were being padded and assumed to be aligned in to an
increased size. The bootstate scheduler for static entries,
boot_state_schedule_static_entries(), was then calculating the
wrong values within the array. To fix this just use a pointer to
the boot_state_init_entry structure that needs to be scheduled.
In addition to the previous issue noted above, the .bs_init
section was sitting in the read only portion of the image while
the fields within it need to be writable. Also, the
boot_state_schedule_static_entries() was using symbol comparison
to terminate a loop which in C can lead the compiler to always
evaluate the loop at least once since the language spec indicates
no 2 symbols can be the same value.
Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
SERIRQ_CONTINUOUS_MODE is specific feature of LPC busses.
This fixes a KCONFIG unmet dependency warning on ARM mainboards with
chromeec.
Change-Id: Iae61986219585dcb1124cf3b24fa32a8596d56c8
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8665
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add license header with copyright of the original authors.
Change-Id: I8c55bb38a2a2a387ad2461e11d402c7392fa2497
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8691
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The decode of UART addresses down to the LPC bus needs
to occur early to allow romstage console messages to
be seen. This enables the decode of most of the I/O
ports typically seen in a system.
Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The current spi_xfer() function sets the count in hardware and then
loops while waiting for the requested number of bytes to be sent or
received. However, the number of bytes to be transferred may exceed
the maximum count that can be programmed into the controller.
This patch re-factors spi_xfer() to split the low-level FIFO handling
portions for transmit/receive into their own functions to be called
by loops in spi_xfer() which will break large transfers into smaller
ones.
BUG=chrome-os-partner:30904
BRANCH=storm
TEST=built and booted with a >64KB payload on Storm
Original-Change-Id: I70743487996cf08cfc602449f2181a7fcd99bfa4
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209838
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Tested-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit 5ec28de11f12c2438356f45ce978a17fbb603bf7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0033e0dd96006cfd30a7a4f5e5a052f677e05108
Reviewed-on: http://review.coreboot.org/8676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Vadim Bendebury