These are configured by the TXE, so they do not need to be configured.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I13957992d637a53203b4328e39c0e6607e017891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Disconnect GPIO's that are unused, or not connected.
Also update comments that are vague or have errors.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1b071ec1d194f76ee78066396bac8dfff5ec851b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64651
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without this, calls to i2c_link() and runtime i2c detection fails on
AMD common platform boards.
Test: Runtime i2c detection of correct touchpad model succeeds on
google/zork.
Change-Id: I238b680b2afb4b9d3e5ac75fe9e630b2adc74860
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select
DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the
selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding
the Designware I2C bus ops handler in a subsequent commit.
Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
When trying to find the parent i2c bus of a given device, ensure that
the bus link doesn't point to itself, else we'll get stuck in an
infinite loop.
Change-Id: I56cb6b2a3e4f98d2ce3ef2d8298e74d52661331c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Create the pujjo variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Follow other ADLN variant to generate by manual)
BUG=b:235182560
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJO
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I73ec985bc19320260d0c3132c1ca23a3648df9e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Convert the librem_14 and librem_mini from using separate devicetrees
to using a baseboard devicetree and overridetrees. This reduces code
duplication, and facilitates adding any new variants with minimal
additional code.
Test: build/boot Librem 14 and Librem Mini v2 boards
Change-Id: Ide65ffc750495c9ba2074757ce467efa2f384c56
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Hook Up SataPortsEnable to the devicetree. As the default value is 0,
set both [0] and [1] in all mainboards so they aren't affected.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ADL-S has more USB ports than mobile chipsets. Add missing ACPI
names.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63655
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After commit 63e54275f6 (libpayload: Implement new CBFS access API),
libpayload includes headers from commonlib/bsd, which in turn include
vb2_sha.h from vboot after commit 0655f78041 (commonlib/bsd: Add new
CBFS core implementation). Usually submodules are initialized by the top
level Makefile.inc, but since this file is never read when building
libpayload based payloads outside the main coreboot build, the header
cannot be found unless the vboot submodule had previously been
initialized. This is especially evident when following Tutorial 1 in the
documentation, where the coreboot repo is cloned without recursing into
submodules and coreinfo is built separately from the coreboot build
using `make -C payloads/coreinfo`.
TEST=Deinitialize submodules and run `make -C payloads/coreinfo`.
Coreinfo should build without error.
Change-Id: I29b16525999921fbce51c2459d3d534b64e00b3c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65222
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CPUID function to get the number of cores on a package is common
across multiple generations of AMD cpus.
Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64869
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The syscfg has to option to automatically mark the range between 4G and
TOM2, which contains DRAM, as WB. Making it generally not necessary to
allocate MTRRs for memory above 4G if no PCI BARs are placed up there.
Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Set tcc_offset value based on the power_profile value, ranging from 10
to 20 degrees.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I66fb266c1730833ff6e2dbf8ea39f23ee0878590
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nereid overridetree to enable port 10.
BUG=b:236162084
TEST=USE="project_nereid emerge-nissa coreboot" and verify it builds
without error.
Signed-off-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
Change-Id: Ic45301b863383e447b2dd3e06811b469cc247229
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65188
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.
This change also corrects the daughterboard USB 3.0 port number.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib6a934a1e5e65fe387c63b78cbe80e45e97e0a8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The daughterboard USB 3.0 was set to port 3, which is incorrect. This
patch corrects that to port 4.
This fixes an issue where USB 3.0 devices are not detected when plugged
in to this port.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50f86dee1b512d0dd20d07e3ee17ebfa5e537bc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The USB ports for the Motherboard USB 3.0 and Type-C were labelled
incorrectly. This change swaps the ports, so they are labelled correctly
and also corrects the over-current pins that they use.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I80484dc8bdd68dd72b3848720c790d59237a9f8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2a7f50ca2b2001e83211e8eba56bfa929ecdfd74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested on the StarLite Mk III & Mk IV with Zorin 16.2 Core. This
resulted in a reduction in power consumption of approximately 3%.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7b5f4e01bc786db02184b722c74fda7d0ca055be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Hook up C1e FSP S UPD which enables enhanced C-states, to
enhanced_cstates. This allows it to be enabled in the
devicetree with a value of "1" as the default is disabled.
C1e exists on both APL and GLK, and has been there since their
initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie803a75ac9fb64a6c21b31baeea7b736e4fbf5fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Hook up FSP S UfsEnabled UPD (1d.0) to devicetree.
UFS only exist on GLK, and has been there since its
initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Nuvoton EC requires a window to be opened for updates, so open
this window only if the Nuvoton EC is present.
Change-Id: Iaa45aa58749c4d0bfc77e60b52eab2bcb270f3ee
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib5fec81a7a04f2f5ab13784435944601902904d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie9bc6b3e20dddeb14cea195ef9a719432f66c6e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Page table entries bit 0 is used as "valid". Its value should be set
by a bitwise OR and not by an addition.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: I14467081c8279af4611007a25aefab606c61a058
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It’s a section title, so mark it up as a title as it’s done similarily
in other documents.
Change-Id: If9d524afe6f80ae1b2704d11617786ee923814b2
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add support for the MT53E2G32D4NQ-046 WT:C and MT53E512M32D1NP-046 WT:B
memory parts to skolas4es.
BUG=b:236284219
BRANCH=firmware-brya-14505.B
TEST=None
Change-Id: I5e3534985e12535ccc4285a0d829bca04781cf1b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65179
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The value stored to 'data' is never read. So remove dead increment and
commented out code.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ifef67fc6415af1260d1a1df54f53fbe67f8860bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Update Shotzo own ec.h with the battery, lid and ps2
defines stripped.
This is to ensure the correct ASL is generated so that we don't
advertise PS2 keyboard support and battery/lid interrupts which
don't exist.
In MAINBOARD_EC_SCI_EVENTS drop following events.
EC_HOST_EVENT_LID_OPEN
EC_HOST_EVENT_LID_CLOSED
EC_HOST_EVENT_BATTERY_LOW
EC_HOST_EVENT_BATTERY_CRITICAL
EC_HOST_EVENT_BATTERY
EC_HOST_EVENT_BATTERY_STATUS
set MAINBOARD_EC_SMI_EVENTS to 0 and drop
EC_HOST_EVENT_LID_CLOSED smi event.
In MAINBOARD_EC_S5_WAKE_EVENTS drop below event.
EC_HOST_EVENT_LID_OPEN
In MAINBOARD_EC_S3_WAKE_EVENTS drop following events.
EC_HOST_EVENT_AC_CONNECTED
EC_HOST_EVENT_AC_DISCONNECTED
EC_HOST_EVENT_KEY_PRESSED
EC_HOST_EVENT_KEY_PRESSED
BUG=b:235303242
BRANCH=dedede
TEST=Build
Change-Id: I5717e2e8ca7549d160fe46ccde31c6d7cf9649d7
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65167
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.
Add check and skip for enabled root port that does not have clock
structure. In addition, a root port can not use a free running clock or
clock set to LAN.
Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The EEs and I misunderstood, and apparently the vfio-pci kernel driver
will turn off the dGPU when it sees it is unused, so coreboot should
leave the dGPU on so the kernel driver can save state before it shuts it
down.
TEST=Tested by ODM
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I30b5dead7a5302f3385ddcaecfbf134c3bb68779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65181
Reviewed-by: Robert Zieba <robertzieba@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Updating from commit id 25b94935:
vboot_ref/futility: Wrap flashrom_drv behind USE_FLASHROM
to commit id 61971455:
vboot_ref/Makefile: Expose symbols irregardless of USE_FLASHROM
This brings in 90 new commits.
BUG=b:207808292,b:231152447
TEST=builds with vboot_ref uprev.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: Id542f555732b58e1205e757393f9d5fdbde2de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch renames identifiers (macros, function and structure names) in
the basecode/debug/debug_feature.c to generic names so that they can be
used to control the features which may have to be controlled either
during pre and post memory.
Currently, the naming of identifiers indicate that it meant to control
the features which can be controlled during only pre-memory phase.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update PL1 and PL2 based on the suggestion of the thermal team.
Then the settings are both updated in firmware log.
BUG=b:233703656, b:233703655
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ibb81a1a8519b88ed4774385d9ccf895d64bbdc21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Prior commit hash 0310d34c2 (cpu/intel/microcode: Have provision to
re-load microcode patch) introduces an option to reload the microcode
based on SoC selecting RELOAD_MICROCODE_PATCH config.
This patch might potentially introduce a boot time regression (~30ms)
when RELOAD_MICROCODE_PATCH kconfig is enabled as all cores might end up
reloading the microcode without the proper need.
Note: RELOAD_MICROCODE_PATCH kconfig is not yet selected by any SoC
hence, it doesn't impact any coreboot project.
The idea is reloading microcode depends on specific use case
(for example: Skip FSP doing MP Init from Alder Lake onwards) hence,
a follow up patch will create a newer API to allow reloading of
microcode when RELOAD_MICROCODE_PATCH config is enabled.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie320153d25cefe153fc8a67db447384f1f20f31f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
TSEG does not need to be aligned to 128KiB but to its size, as the MSR
works like an MTRR. 128KiB is a minimum TSEG size however.
TESTED on google/vilboz.
Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64865
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Create the joxer variant of the nissa reference board by copying
the template files to a new directory named for the variant.
BUG=b:236086879
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_JOXER
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4cb74f90c4ec33818b551d5f51759930e3222677
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Sean Rhodes