Commit Graph

10752 Commits

Author SHA1 Message Date
Kyösti Mälkki 0430c69918 superio/nct5104d: Refactor IRQ trigger config
That function was getting too long.

Change-Id: Ic50f210391c2467b65215aa556269b0ba601c2ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10176
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-05-14 16:41:45 +02:00
Vladimir Serbinenko cbcf28fef0 lenovo: Disable radio when suspending or turning off.
Without this some radios may remain operational. They may consume power but
the immediate demonstrable effect is wireless LED still being on.
Coreboot will reenable radios on resume or poweron.

Change-Id: I9fcb08880964b1594f779a246840bc3013a44afe
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10190
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-14 15:08:52 +02:00
Vladimir Serbinenko 4b1f09694c x230: Fix VGA PCIIDs.
x230 is ivy, not sandy. Fix copy-paste error.

Change-Id: Ic462bab39ddac0e1e6fef1e043970957e45fb6ed
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10189
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-14 15:08:40 +02:00
Aaron Durbin 3dc60c51cb vboot: fix die() hang for recovery path
When we are taking the recovery path there is no slot or
components to fill out.

Change-Id: Ic97a247629365ef54a340c4398cb7491935edc11
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10198
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-13 22:44:16 +02:00
Marc Jones a6a566bf0b amd/pi: Move AGESA cbfs access into the wrapper
The AGESA.c file in 3rdparty has cbfs access functions
for locating the AGESA binaries. coreboot access functions
need to be within coreboot where they can be updated with
cbfs changes. Move the offending function to coreboot.

Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10058
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 22:30:07 +02:00
Aaron Durbin 2591e937e7 secmon: allow for serial console
Add necessary checks and objects for secmon serial console.

Change-Id: Ibafa19061255ef6847a424922565a866328ff34c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10197
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-05-13 20:54:00 +02:00
Aaron Durbin fd6fb26ae7 verstage: provide support for serial console
verstage previously lacked serial console support.
Add the necessary objects and macro checks to allow
verstage to include the serial console.

Change-Id: Ibe911ad347cac0b089f5bc0d4263956f44f3d116
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10196
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-05-13 20:53:38 +02:00
Aaron Durbin ce2c50d895 vboot: indicate verstage loading on console
There was no indication of verstage being loaded. Provide this
output so that one can follow the flow from console messages.

Change-Id: I67ae6bb334608fe10a4a12fe690498afaf6b8366
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10195
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13 20:53:31 +02:00
Aaron Durbin aab13266b1 console: enumerate all known stages
There are more stages than currently handled in the
initial message from console_init(). Add support for those
including an UNKNOWN catchall.

Change-Id: I2374db590072bdca8ff35116e2ecb2ad6459b697
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10194
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13 20:53:25 +02:00
Vladimir Serbinenko e7366daf2e Include back the 306ax microcode again.
In ee89435798 microcode for 306ax
was forgotten in migration.
Without microcode update my machine experiences random hangs and various
misbehaviour.

Change-Id: I61c704d88a8a0ed74a16fb3f80cce08e8515e6e2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10180
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-05-13 19:57:30 +02:00
Lee Leahy 522149c310 cbmem: Add initial allocation support
Add support to allocate a region just below CBMEM root.  This region is
reserved for FSP 1.1 to use for its stack and variables.

BRANCH=none
BUG=None
TEST=Build and run on Braswell

Change-Id: I1d4b36ab366e6f8e036335c56c1756f2dfaab3f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10148
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 17:07:51 +02:00
Aaron Durbin 1f04e94b79 x86: expose tsc's timer_monotonic_get() in SMM
The implementation of timer_monotonic_get() for the tsc
module was being guarded from SMM. Allow this to be
linked into SMM as the generic spi flash driver now needs
this support which can be included in SMM.

Change-Id: I3909edecac8de117922c4ea6c53e6e561f6f435b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10187
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-05-13 00:23:53 +02:00
Aaron Durbin 797ca1b712 baytrail: broadwell: correct refcode loading
I messed up the conditionals on loading the reference code.
The bug used || instead of && causing 2 reference codes to
be loaded.

Change-Id: I29a046bf0e8dc29a9efdb636ebfd04e11eb73f82
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10185
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-05-13 00:23:42 +02:00
Aaron Durbin 09560facd4 vboot: handle RELOCATABLE_RAMSTAGE
The support for RELOCATABLE_RAMSTAGE was accidentally omitted in
the vboot loader. Add said support.

Change-Id: I569918823253c33f698acefd6a619133543c7aef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10184
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-05-13 00:23:27 +02:00
Lee Leahy 3dad489cac FSP 1.1 Comparison Base
Add FSP 1.0 source for comparison with FSP 1.1.

BRANCH=none
BUG=None
TEST=None

Change-Id: I8df349f97acfa74f4de3607d49633da3d4884546
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10116
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-12 19:55:52 +02:00
Kyösti Mälkki cc4d30924a usbdebug: Add FTDI FT232H support
Tested with gizmosphere/gizmo1 Explorer add-on board, which
exposes the following device:

   0x0403 Future Technology Devices International, Ltd
   0x6014 FT232H Single HS USB-UART/FIFO IC

For now UART is hard-coded to 115200, 8n1, no flow-control.

Change-Id: I4081f84f7700751ccbf079e7fcbb1467aa71d872
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10063
Tested-by: build bot (Jenkins)
2015-05-12 07:12:07 +02:00
Aaron Durbin 0e571fd7ac vboot: allow for dynamic work buffers
The vboot library currently relies on link-time known
address and sizes of the work buffer.  Not all platforms
can provide such semantics. Therefore, add an option
to use cbmem for the work buffer. This implies such platforms
can only do verification of the firmware after main memory
has been initialized.

Change-Id: If0b0f6b2a187b5c1fb56af08b6cb384a935be096
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10157
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11 22:40:10 +02:00
Aaron Durbin 1e8be636cc vboot: add vb2_working_data_size()
Instead of using the symbols directly provide a size
function to provide symmetry between getting the work
data and size. It also allows for an abstraction where
the linker symbols may not be the only source of this
information.

Change-Id: I4568064a0050d118c3544ab1ea59a08eb0bad8e4
Signed-off-by: Aaron Durbi <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10156
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11 22:39:49 +02:00
Aaron Durbin c6100e5421 chromeos: remove vboot_verify_firmware()
vboot_verify_firmware() was only defined to ease upstreaming.
It was only an empty inline as it is so remove it. Additionally,
vboot2 does not require romstage_handoff so there's no need in
adding it for the nyan boards.

Change-Id: I4d84ac9fb60c756cf10742f26503f7f11af5f57b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11 22:39:31 +02:00
Aaron Durbin 17200ad5fb vboot: inject vboot loader for stage loading
As previously done the vboot loader can be optionally
inserted in the stage loading logic in order to
decide the source of each stage. This current patch
allows for verstage to be loaded and interrogated
for the source of all subsequent stages. Additionally,
it's also possible to build this logic directly into
one of the additional stages.

Note that this patch does not allow x86 to work.

Change-Id: Iece018f01b220720c2803dc73c60b2c080d637d0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10154
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-05-11 22:39:22 +02:00
Aaron Durbin 01562b6cb5 imd: don't recover on limit == 0
If the limit of the large starting region was set with
a NULL pointer then the limit field will be 0. If the
limit is zero then no attempt to recover is necessary
as there is no region to recover.

This prevented an early call cbmem_find() from hanging a
rambi device. The config was with vboot enabled and was
way before memory init in the sequence.

Change-Id: I7163d93c31ecef2c108a6dde0206dc0b6f158b5c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10175
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-11 22:39:13 +02:00
Patrick Georgi 375570e617 vboot2: Use the right set of compiler flags for building vboot libraries
This make it pass through -fno-stack-protector, and also uses
libverstage fields consistently.
verstage is for 'stage' stuff, libverstage for all the vboot logic.

Change-Id: I3032e072414bed52effd2dc5057896781ad562c6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/10174
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-05-11 20:09:44 +02:00
Aaron Durbin d2ab4e420d vboot: allow options to be selected from .config
In order to allow easier setting of variables without
changing mainboards and/or chipset Kconfig files allow
the vboot options to be selected by the user.

Change-Id: I6e995eb209b4cd63c73ef679d0c5699759d129f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10153
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11 18:38:45 +02:00
Aaron Durbin d1cf44c596 vboot: fix vboot_reference compilation
The VB_FIRMWARE_ARCH variable was not being set correctly,
and the VBOOT_STARTS_IN_BOOTBLOCK Kconfig option was not properly
prefixed with CONFIG_. Correct both of these oversights.

Change-Id: Id27974c285d2629bd47b90b6a93aca1ec8a76512
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10152
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11 18:37:04 +02:00
Aaron Durbin e385b37126 chromeos: add missing vboot functions
Somewhere along the development path the following
vboot functions were dropped:
  int vboot_enable_developer(void)
  int vboot_enable_recovery(void)

Add them back, but also refactor the flag extraction
so as not duplicate all that same logic.

Change-Id: Id58f3b99f29caeff98b2d3111cfa28241d15b54f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10151
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11 18:36:39 +02:00
Aaron Durbin bc40933e40 arm64: update verstage linking
The linker scripts are added to stage objs so remove those
from the object lists. boot.c will be needed to link verstage
properly.

Change-Id: Ib8427fe015b72e2282219f116a39949739a0af48
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10150
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11 18:36:25 +02:00
Aaron Durbin 52a530d032 arm: update verstage linking
The linker scripts are added to stage objs so remove those
from the object lists. boot.c will be needed to link verstage
properly.  Lastly, VERSTAGE_LIB has no value so remove it.

Change-Id: Ie53b42c4995a96006463ec5b358aa43a731cb1b8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10149
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11 18:35:57 +02:00
Furquan Shaikh a9ee61e253 cache: Add arch_program_segment_loaded call to arm and arm64
arch_program_segment_loaded ensures that the program segment loaded is
synced back from the cache to PoC. dcache_flush_all on arm64 does not
guarantee PoC in case of MP systems. Thus, it is important to track
and sync back all the required segments using
arch_program_segment_loaded. Use this function in rmodules as well
instead of cache_sync_instructions which guarantees sync upto PoC.

BUG=chrome-os-partner:37546
BRANCH=None
TEST=Boots into depthcharge on foster

Change-Id: I64c2dd5e40ea59fa31f300174ca0d0aebcf8041d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35ba0b882b86ff2c29ac766e1d65f403c8346247
Original-Change-Id: I964aa09f0cafdaab170606cd4b8f2e027698aee7
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/260908
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10173
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-05-11 18:02:14 +02:00
Patrick Georgi 9bb90cd1a2 secmon: Add some missing files
secmon is referring to uart's default_baudrate() and
various coreboot version strings.

Change-Id: I40a8d1979146058409a814d94ea24de83ee4d634
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10129
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-11 17:43:46 +02:00
Patrick Georgi c96ff45b7f nvidia/tegra132: we write tables in ramstage
So that's more precise than "anything non-pre-ram".

Change-Id: I21db536a5ea704c4b087f57d0b761dd3fdf43e3e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10128
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-11 17:43:43 +02:00
Kyösti Mälkki 6be1a8bf08 AGESA: Drop unused AGESA_MEM_TABLE
These tables are not referenced anywhere, thus all
comments about adjustments are void.

Also drop stub AgesaReadSpd that is all commented out.

Change-Id: I12233ea0dc4baaf36a75f359c52cc59c9b6dad79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10143
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-05-10 18:44:04 +02:00
Timothy Pearson ef33db01b3 cpu/amd/model_10xxx: Add missing ACPI _PSD object
The ACPI power state generator for AMD 10xxx CPUs did not generate
the _PSD object required for reliable PowerNow! operation.  Without
a correct _PSD object PowerNow! does not know the required core
clock relationships, potentially causing unstable system operation.

Generate the _PSD object in accordance with the BKDG Rev. 3.62.

Change-Id: I255a4837ab29ff1b0874daf189ffb61798645795
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10142
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-05-08 22:56:41 +02:00
Timothy Pearson 61942de689 northbridge/intel/gm45/gma: Minor cleanup
1.) Removed invalid set of TRANS_STATE_MASK bit
2.) Used i915 register defines to clarify code

Change-Id: I08d016e9d66b5eeea8f2174abaa35a98e2b4eca3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-08 21:30:35 +02:00
Damien Zammit f88b93214b southbridge/i82801gx: Add x_EN defines for LPC_EN
A few hardcoded values could be fixed after this commit

Change-Id: I3ae67f4f6136361d67d4fdae2a5a29b7b1a75478
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10065
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-08 21:29:04 +02:00
Timothy Pearson e7f70907ba northbridge/intel/gm45/gma: Add backlight control register field
This allows the backlight control register to be set via devicetree.cb

Change-Id: I32b42dfc1cc609fb6f8995c6158c85be67633770
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9330
Tested-by: build bot (Jenkins)
2015-05-08 21:28:34 +02:00
Sol Boucher 69b88bf127 fmaptool: Introduce the fmd ("flashmap descriptor") language and compiler
This adds a compiler for a language whose textual representation of flashmap
regions will be used to describe the layout of flash chips that contain more
than just a single CBFS. Direct integration with cbfstool (via a new
command-line switch for the create action) is forthcoming but will be added
separately.

BUG=chromium:461875
TEST=Use Chromium OS's cros_bundle_firmware script on the fmap.dts file for
panther. Using the latter file as a reference, write a corresponding
fmap.fmd file and feed it through fmaptool. Run both binary output files
though the flashmap project's own flashmap_decode utility. Observe only
the expected differences.
BRANCH=None

Change-Id: I06b32d138dbef0a4e5ed43c81bd31c796fd5d669
Signed-off-by: Sol Boucher <solb@chromium.org>
Original-Commit-Id: 005ab67eb594e21489cf31036aedaea87e0c7142
Original-Change-Id: Ia08f28688efdbbfc70c255916b8eb7eb0eb07fb2
Original-Signed-off-by: Sol Boucher <solb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255031
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/9942
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-08 19:55:42 +02:00
Aaron Durbin 7aafe5303b timestamp: fix incremental linking error for !HAVE_MONOTONIC_TIMER
In linking ramstage a single object file is created before linking
with the linker script. Though there is a weak timestamp_get() symbol
in timestamp.c any of its dependent symbols need to be available
during the incremental link. As not all platforms have
HAVE_MONOTONIC_TIMER enabled this will create a linking error.
Fix this by providing a hint to the compiler to remove dead code
and thus the dependent symbols causing linking errors in the presence
of !HAVE_MONOTONIC_TIMER.

Change-Id: Ib8a5dca2c12c2edac7605f403ed91b793823c8a3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10138
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-07 19:52:50 +02:00
Stefan Reinauer 1d7b9de350 kbuild: Use wildcard for driver subdirectories
Change-Id: Id1685c0b28ec8e3ab972a671af6f2de6f321c645
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9805
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-07 19:41:42 +02:00
Patrick Georgi b2aee6f2e7 vboot2: Replace hard coded 'fallback' prefix with Kconfig variable
Change-Id: I9cbdf06f4d0956b5374915f8af7501c6f75b4687
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10113
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-07 13:53:34 +02:00
Patrick Georgi b4a6ca96c0 imgtec/pistachio: Add comment on the unusual memory layout
To avoid having to dig up the constraints again, document
the memory layout right in memlayout.ld.

Change-Id: I298cc880ae462f5b197ab2f64beb2f0e0d9f5a7d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10039
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-07 13:53:15 +02:00
Patrick Georgi 29ed46cacc 3rdparty/vboot: Add vboot
This allows providing a verified boot mechanism in the
default distribution, as well as reusing vboot code like
its crypto primitives for reasonably secure checksums over
CBFS files.

Change-Id: I729b249776b2bf7aa4b2f69bb18ec655b9b08d90
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05 22:49:34 +02:00
Patrick Georgi 26e24cc12d 3rdparty: move to 3rdparty/blobs
There's now room for other repositories under 3rdparty.

Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05 22:49:18 +02:00
Patrick Georgi f4f028790a 3rdparty: Move to blobs
To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.

Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05 22:49:11 +02:00
Kyösti Mälkki b9cd5ece14 sandy/ivy boards: Rename defines from onboard.h for ACPI
Adopted style from later Chromebooks.

Change-Id: I4993b8f40489b6bf5d08e00089f36f293853629e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/9992
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-05 17:56:24 +02:00
Aaron Durbin 168eda5f0d arch/arm64: provide boot_cpu()
Change-Id: I708041133dfafdc97e052952ad9d8f2e4164209c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10105
Tested-by: build bot (Jenkins)
2015-05-05 17:49:31 +02:00
Aaron Durbin 9e80e27d38 timestamp: provide weak default implementation of timestamp_get
Change-Id: I2e7f17a686f6af3426c9d68cd9394e9a88dbf358
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10104
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-05 17:49:30 +02:00
Aaron Durbin ae1fcc3c1d vboot: add cbfs_core
And we don't support lzma compressed data in verstage.

Change-Id: I3d8d3290f147871c49e9440e9b54bbf2742aaa9e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10103
Tested-by: build bot (Jenkins)
2015-05-05 17:49:29 +02:00
Aaron Durbin 2daadf8f57 timestamp: refine boot CPU test
The timestamp code's restriction to run only on the BSP
is for AMD systems. No need to run it everywhere, so
tighten the test (and only run boot_cpu() when required).

Change-Id: I800e817cc89e8688a671672961cab15c7f788ba8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10102
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-05 17:49:28 +02:00
Aaron Durbin d914412bec cbfs: make cbfs_load_prog_stage_by_offset() public
That function will be used by the vboot loader.

Change-Id: I204c6cd5eede3645750b50fe3ed30d77c22dbf43
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10101
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-05 17:49:27 +02:00
Aaron Durbin 26681ec2cb vboot2: Fix compiler flags dropped during verstage/libverstage split
verstage still needs to be built with its flags.

Change-Id: I125e4be283d3838fc7ce6587bf9996731540d517
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10098
Tested-by: build bot (Jenkins)
2015-05-05 17:46:43 +02:00
Aaron Durbin 32bc18ef97 nvidia/tegra132: Fix vboot2 memory layout
bootblock et al were listed twice, which shouldn't happen.

Change-Id: I3e6077d70e064ebe74bd4e5e3156f87d548c2fcb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10097
Tested-by: build bot (Jenkins)
2015-05-05 17:46:39 +02:00
Aaron Durbin 8fb36c07ac console: rename do_vtxprintf to do_printk_va_list and use it
The name is more consistent with what we have elsewhere,
and the callsite didn't build at all (with vboot enabled)

Change-Id: I3576f3b8f737d360f68b67b6ce1683199948776d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10096
Tested-by: build bot (Jenkins)
2015-05-05 17:46:35 +02:00
Aaron Durbin ed98eeea84 vboot: Remove vboot_get_payload()
It's not used at all.

Change-Id: I97bf02a9277f6ca348443c6886f77b4dfc70da78
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10095
Tested-by: build bot (Jenkins)
2015-05-05 17:46:32 +02:00
Aaron Durbin 0946a1bb21 vboot: remove uses of vboot2_verify_firmware()
The vboot mechanism will be implemented within the program loader
subsystem to make it transparent to mainboards and chipsets.

Change-Id: Icd0bdcba06cdc30591f9b25068b3fa3a112e58fb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10094
Tested-by: build bot (Jenkins)
2015-05-05 17:46:28 +02:00
David Hendricks c3b0e29b43 veyron_danger: Turn on backlight enable before VCC_LCD
On current Danger boards, VCC_LCD is gated by BL_EN. Thus we
need to enable BL_EN in order to power on the display so that
we can read the EDID and set things up.

Later board revisions may change this ordering, but for now it
doesn't seem to be causing a significant issues (no noticable
"snow" or other corruption using Pepto display).

BUG=none
BRANCH=none
TEST=booted on Danger, saw dev mode screen come up

Change-Id: I70aab8c1f6da2d0fce310d59073026eef0f67821
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a918824e747600a2f3a88602320f4f563ce17b7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Iaf17cc4682bd3c46f62cba789e3ecf8d5a474362
Original-Reviewed-on: https://chromium-review.googlesource.com/266913
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10089
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-05-05 09:56:35 +02:00
Julius Werner 9ac9ac6309 veyron: Initialize EC interrupt GPIO and add them to coreboot tables
This patch initializes the GPIO for the Chrome EC interrupt line on
Veyron boards and passes its description through the coreboot table, so
that payloads with keyboard support can use it to detect pending key
presses.

BRANCH=none
BUG=chrome-os-partner:39514
TEST=Booted Jerry, confirmed that it could still detect keypresses.
Confirmed that EC log does not show a huge amount of MKBP polls.

Change-Id: I4de35ef411c3acc02282ebf8e764785a1e7bf6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ad95d667ef3af3fb217e3c370468dc1d6ec36c9
Original-Change-Id: I8b426621af088460929cfff0a4b46618e2a86725
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/267344
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/10088
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-05-05 09:56:32 +02:00
Sol Boucher 8ccdeaeb20 haswell: Link stage_cache_external_region into ramstage, too
When CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is set, this
function is now linked into the ramstage as well as the romstage,
since the former makes calls to it in panther builds.
With this commit, it's possible to build panther using the config file
from the Chromium OS project[1] if you supply the appropriate Intel
descriptor and ME binary blobs and manually set
CONFIG_VBOOT_VERIFY_FIRMWARE=n, CONFIG_BUILD_WITH_FAKE_IFD=n, and
CONFIG_HAVE_ME_BIN=y. The resulting image is at least able to load a
payload, although I only tested with depthcharge, which immediately
complained, "vboot handoff pointer is NULL" and gave up the ghost.

[1] https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/master/sys-boot/coreboot/files/configs/config.panther

Change-Id: Id3bb510fa60129a4d36a0117dc33e7aa62d6c742
Signed-off-by: Sol Boucher <solb@chromium.org>
Reviewed-on: http://review.coreboot.org/10046
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-05 03:39:41 +02:00
Kyösti Mälkki 634899ca49 resource: Adjust memory resources high earlier
Do this to avoid reporting incorrect resource window in the logs.

Change-Id: Icb7978deeb54f0ec6c29473ce9034fe44b6d7602
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8890
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-05 01:26:02 +02:00
Kyösti Mälkki e6a9290fa2 resource: Enhance resource reporting
Remove some redundancy in both source code and console output.

Change-Id: I32350966de7af30b3ca4ac747fe3bf623ea9484b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-05 01:25:24 +02:00
Kyösti Mälkki 134b616267 resource: Report correct secondary resource window
Once a bridge window resource is allocated, it becomes the base and limit
for any resource on the secondary bus. Upper limit was incorrectly
reported in the log while assigning secondary resources.

Change-Id: I69f0a02aae6d13f77aaa2dace924b8970b23edad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-05 01:25:04 +02:00
Jonathan A. Kollasch ade2c5e8b7 winent/mb6047: symbolic arguments for acpi_create_madt_lapic_nmis()
Change-Id: I19af5f36a55d6c2906d603e940b3aadd2ca97140
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8317
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-04 22:34:59 +02:00
David Imhoff fd1f514fe4 drivers/spi/stmicro: Rename N25Q256A to N25Q256
The 'A' indicates the production process(64 nm). All other chips from
the same family leave this out.

TEST=Build and booted on Minnowboard Max

Change-Id: I21e6c01de5d547bbc2252e679a001948e7ab752c
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10078
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-04 22:34:22 +02:00
David Imhoff a42edc30e9 drivers/spi/stmicro: Add '.op_erase' for N25Q256
'.op_erase' was not specified for this chip. Set it to sub sector
erase(CMD_M25PXX_SSE). Adjust page/sector size for sub sector erase
to work.

TEST=Untested, due to lack of hardware.

Change-Id: Icc2748fbd3afeb56693e1c17d97eb490fba67064
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10077
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-04 22:34:06 +02:00
David Imhoff 61295b5290 drivers/spi/stmicro: Add N25Q064 support
N25Q064 is similar to N25Q128.

TEST=Build and booted twice on Minnowboard Max

Change-Id: Iec105f8b81f619846cf40b40042cc59150b81149
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10076
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-04 22:34:01 +02:00
David Imhoff 52148b7785 intel/fsp_baytrail: Fix SPI debugging
Fix compiler error's due to type mismatch. This is broken since commit
bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to
pointer).

TEST=Build with CONFIG_DEBUG_SPI_FLASH=y and booted on Minnowboard Max

Change-Id: Id3d448e219716135897f381a73d416ff34036118
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10075
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-04 22:33:54 +02:00
David Imhoff 7249572b80 spi: Remove out of date comment and reorder flash table
What is described by the comment has already been fixed in f0d038f4
(flash: use two bytes of device ID to identify stmicro chips).
This also means that STM_ID_N25Q128 doesn't have to be at the top of
stmicro_spi_flash_table anymore.

TEST=Untested, due to lack of hardware

Change-Id: I7a9e9a0cdfdb1cf34e914e186fc6957c1d9b5ca6
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10068
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-04 22:33:49 +02:00
David Imhoff 8d4377b56d spi: Change 'page' to 'sector' in log message
The log message says 'page size' while actually the sector size is
printed. This is confusing since for stmicro page size != sector size.
Also add '0x' prefix to numbers to make it clear they are in hex.

TEST=Build and booted on Minnowboard Max

Change-Id: I795a4b7c1bc8de2538a87fd4ba56f5a78d9ca2ac
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10067
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-04 22:33:39 +02:00
Stefan Reinauer 2436bda11d cpu: get rid of socket source code
None of the sockets has actual configuration options, so the source
for them is only cosmetical boilerplate. Hence, drop it. This reduces
the sockets to be selectors for certain CPU types, which will be dropped
in future commits, and mainboards will select their CPUs directly rather
than through an additional layer of indirection (sockets)

Change-Id: I0f52a65838875a73531ef8c92a171bb1a35be96e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9797
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-04 22:18:23 +02:00
Timothy Pearson 58649b058b src/southbridge/intel/i82801ix: Add GPIO register locations
Change-Id: I226a1a6bc6b1f921c03f8ec57875a88314928aeb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-03 09:14:33 +02:00
Paul Menzel 1abd0ddfae drivers/intel/fsp1_0: Remove executable bit from C files
Fix up commit c13ad6c6 (driver/intel/fsp: Correct the fastboot data (MRC
data) printing length) unintentionally making the changed files
executable.

Change-Id: I909c323023a9ccfb0c20094d9085ae90043b9e04
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10060
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-02 19:15:20 +02:00
Timothy Pearson 289eec8ab7 mainboard/lenovo/x200: Use defines from southbridge for GPIO config
Change-Id: I9f65922d0785e06a173221b3262e73b575087dfd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9321
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-02 19:13:58 +02:00
Dave Frodin b738913ce0 northbridge/intel/fsp_rangeley: Correct MMIO size setting
The Rangeley chipset has the MMIO PCI config space feature
enabled at 0xe0000000-0xefffffff. This is a 256MB space
which covers all of config space. The ACPI table for
this space only defines it as being 64MB. This change
fixes that setting.

Change-Id: I8205a9b89ea6633ac6c4b0d5a282cd2745595b2e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/10047
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-05-01 17:29:00 +02:00
Dave Frodin 2eaa0d49e1 intel: Correct MMIO related ACPI table settings
Several of the intel platforms define the region reserved
for PCI memory resources in a location where it overlaps
with the MMIO (MCFG) region.

Using the memory map from mohon_peak as an example:

  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  1. 0000000000001000-000000000009ffff: RAM
  2. 00000000000a0000-00000000000fffff: RESERVED
  3. 0000000000100000-000000007fbcffff: RAM
  4. 000000007fbd0000-000000007fbfffff: CONFIGURATION TABLES
  5. 000000007fc00000-000000007fdfffff: RESERVED
  6. 00000000e0000000-00000000efffffff: RESERVED
  7. 00000000fee00000-00000000fee00fff: RESERVED
  8. 0000000100000000-000000017fffffff: RAM

  The ACPI table describing the space set aside for PCI memory
  (not to be confused with the MMIO config space) is defined
  as the region from BMBOUND (the top of DRAM below 4GB) to
  a hardcoded value of 0xfebfffff. That region would overlap
  the MMIO region at 0xe0000000-0xefffffff. For rangeley
  the upper bound of the PCI memory space should be set
  to 0xe0000000 - 1.

  The MCFG regions for several of the affected chipsets are:
  rangeley    0xe0000000-0xefffffff
  baytrail    0xe0000000-0xefffffff
  haswell     0xf0000000-0xf3ffffff
  sandybridge 0xf8000000-0xfbffffff

TEST = intel/mohonpeak and intel/bayleybay.

Change-Id: Ic188a4f575494f04930dea4d0aaaeaad95df9f90
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/9972
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-05-01 17:28:44 +02:00
Matt DeVillier 3905caec32 dmp/vortex86: fix missing cpu Kconfig guards
Commit e2c2bb9 (dmp/vortex86: move PLL config to cpu Kconfig)
failed to properly restrict the PLL config selection to that cpu,
resulting in the selection option being present/required for all CPUs.

Fix by guarding the Kconfig options with if/endif.

Change-Id: Ifecf291b985ab9d0d13d6b1264d3bc9a314b8546
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10038
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-30 22:33:16 +02:00
Lee Leahy c95ebccd9a vendorcode/intel: Add EDK2 header files
As the first step in adding support for FSP 1.1, add common header files
for EDK2.  Internally FSP is based upon EDK2 and uses the defines and
data structures within these files for its interface.

These files come from revision 16227 of the open source EDK2 tree at
https://svn.code.sf.net/p/edk2/code/trunk/edk2.  These files are
provided in an EDK2 style tree to allow direct comparison with the EDK2
tree.

Updates may be done manually to these files but only to support FSP 1.1
on UEFI 2.4.  A uefi_2.5 tree should be added in the future as FSP
binaries migrate to UEFI 2.5.

Note: All the files were modified to use Linux line termination.

BRANCH=none
BUG=None
TEST=Build for Braswell or Skylake boards using FSP 1.1.

Change-Id: Ide5684b7eb6392e12f9f2f24215f5370c2d47c70
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/9943
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30 22:28:12 +02:00
Patrick Georgi 405bd698a6 intel/broadwell: Allow using non-fake IFD descriptor
Change-Id: I3091437444ffd9ca3e103c41c37a5374805b1231
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-04-30 22:11:53 +02:00
Matt DeVillier 31769d99da cpu/intel/haswell: remove dependency on socket_rpga989
Remove dependency of Haswell on cpu/intel/socket_rpga989 code,
which is a carry-over from Sandy Bridge/Ivy Bridge and older
coreboot conventions where features were structured around socket types.

Add CPU-specific options to Kconfig and required subdirs to
Makefile.inc which are curently included with socket_rpga989.

TEST=successfully built and booted on google/panther

Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10037
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 17:50:47 +02:00
Patrick Georgi 40e2004abf intel/broadwell: bootstate mechanism only exists in ramstage
So don't try to use it elsewhere.

Change-Id: Ia600ba654bde36d3ea8a0f3185afae00fe50bfe9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10030
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 16:57:19 +02:00
Patrick Georgi c41fd4b75c arm/armv7: drop merge left-over
Fixes up commit 93d8e3c4 (armv7-m: add armv7-m configuration).

Change-Id: Ie0b6c90e9ce89d564e3345d2746297f39ba9121d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10042
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 16:15:15 +02:00
Patrick Georgi 27ef602fab vboot: split class in library and stage
The build system includes a bunch of files into verstage that
also exist in romstage - generic drivers etc.
These create link time conflicts when trying to link both the
verstage copy and romstage copy together in a combined configuration,
so separate "stage" parts (that allow things to run) from "library" parts
(that contain the vboot specifics).

Change-Id: Ieed910fcd642693e5e89e55f3e6801887d94462f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10041
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 15:39:53 +02:00
Patrick Georgi 8ef8afbb38 arch/arm: only include subdirectories for ARM builds
Change-Id: Ieac02fcc4508f7c1b194802453d6222b902a38a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10032
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 15:39:29 +02:00
Patrick Georgi b5e1984594 intel/broadwell: Don't select MONOTONIC_TIMER_MSR
That's a Haswell exclusive, used nowhere else, but confusing
when hunting for the monotonic timer used on that SoC.

Change-Id: I60ec523e54e5af0d2a418bcb9145de452a3a4ea9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10034
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 15:39:10 +02:00
Patrick Georgi e3f880e4d8 intel/broadwell: Build monotonic timer driver for SMM
SPI flash drivers need it.

Change-Id: I63d79472d70d75f7907e7620755c228d5a4918e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10033
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 15:39:04 +02:00
Patrick Georgi ba2b1e32b0 i2c/tpm: add final newline
Change-Id: I0024c4d56f93eb6c9a54103e79c9d8a8b7d8d6fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10043
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 15:37:55 +02:00
Patrick Georgi e360df0fe2 chromeos: Use __attribute__ normal form
Change-Id: Idf99c1491386578ac2471ca5cc8a153d2b5225e4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10044
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 15:37:42 +02:00
Patrick Georgi 3e18acabd3 chromeos: Add missing headers
Builds with CHROMEOS fail due to missing includes.

Change-Id: I8c88bca8f8cc3247d3f3311777f794c4fdfee3c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10029
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 15:37:21 +02:00
Aaron Durbin 57e37287f4 vboot: add and rejuggle Kconfig options
The ChromeOS machines employing vboot verfication require
different combinations of support:

1. When vboot verification starts.
2. Is the vboot code a separate stage or program?
3. If a separate stage, does the that vboot program (verstage) return
   to the stage that loaded the verstage?

For the above, #1 is dependent on when to load/run vboot logic which
is orthogonal to #2. However, #3 is dependent on #2. The logic
to act on the combinations follows in subsequent patches.

Change-Id: I39ef7a7c2858e7de43aa99c38121e85a57f1f2f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30 13:05:36 +02:00
Aaron Durbin 5abcba7121 vboot: move Kconfig options for stage indicies
With vboot1 out of the way place all the associated Kconfig
options in vboot2's Kconfig file (excluding main vboot verify
option). More options will be added to accomodate vboot's various
combinations of use cases.

Change-Id: I17b06d741a36a5e2fefb2757651a61bfed61ae1e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10023
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-04-30 13:05:20 +02:00
Aaron Durbin 5e8286bed6 program loading: add optional is_loader_active() callback
Add a way for a loader to indicate if it is active. Such users
of this callback would be vboot which can indicate to the rest
of the system that it isn't active. is_loader_active() also
gives vboot a chance to perform the necessary work to make
said decision.

Change-Id: I6679ac75b19bb1bfff9c2b709da5591986f752ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10022
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30 13:05:13 +02:00
Denis 'GNUtoo' Carikli 16110e7ffa i945/gma: Fix wrong comment about the documentation.
The GTT location is documented in the "309219" datasheet.
For instance it can be found in the TOLUD register description.

The 309219 datasheet is for the
"Mobile Intel® 945 Express Chipset Family". It was published in 2008.

Change-Id: I75ac095ebc577e031af566963ebffe9ed2587c96
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/9622
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30 12:01:43 +02:00
Stefan Reinauer 9616f3ceb7 kbuild: Don't require intel/common changes for every soc
In the true spirit of separating components more strictly
and allowing to add new components to coreboot without touching
existing code, move Intel common code selection to the soc
Kconfig and out of src/soc/intel/common/Makefile.inc

Change-Id: I0a70656bb9f4550b6088e9f45e68b5106c0eb9af
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10031
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30 12:00:14 +02:00
Lee Leahy b8179087af cbmem: Add FSP timestamps
Add additional FSP timestamp values to cbmem.h and specify values for
the existing ones.  Update cbmem.c with the FSP timestamp values and
descriptions.

BRANCH=none
BUG=None
TEST=Build for Braswell and Skylake boards using FSP 1.1.

Change-Id: I835bb090ff5877a108e48cb60f8e80260773771b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10025
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30 01:33:10 +02:00
Lee Leahy bdd98254ab cbmem: Identify the FSP areas in CBMEM
Add identifers and descriptions for the FSP areas within CBMEM.

BRANCH=none
BUG=None
TEST=Build for Braswell and Skylake boards using FSP 1.1.

Change-Id: I4d58f7f08cfbc17f3aef261c835b92d8d65f6622
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10026
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30 00:18:46 +02:00
Patrick Georgi 6e944c467c imgtech/pistachio: Give some more space to the bootblock
The memory layout isn't very clear here, since there are two
regions (bootblock and "SRAM") that are actually the same.
So when increasing the bootblock's size, we also need to move
the romstage around.

Change-Id: Ib158a4ef96b7c1dd1132b6e8bd47a0eb9c3951d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-04-30 00:17:00 +02:00
Stefan Reinauer e1133b7d7d kbuild: automatically include northbridges
This change switches all northbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in northbridge/Makefile.inc or in
northbridge/<vendor>/Makefile.inc.

This means, vendor and northbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.

The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).

Change-Id: I8468154dbfaaaffcba9fda27ba2d7b9049ad5c19
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9800
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29 18:12:14 +02:00
Stefan Reinauer aae53ab76a kbuild: automatically include SOCs
This change switches all SOC vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in soc/Makefile.inc or in
soc/<vendor>/Makefile.inc.

This means, vendor and SOC directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.

The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).

Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9799
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29 18:11:30 +02:00
Stefan Reinauer 77c04e95ba kbuild: automatically include ECs
This change switches all ECs and the generic EC ACPI code
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in ec/Makefile.inc or in
ec/<vendor>/Makefile.inc.

This means, vendor and ec directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.

The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).

Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9798
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29 18:10:41 +02:00
Martin Roth e2c2bb9447 dmp/vortex86: move PLL config to cpu Kconfig
This moves the vortex86ex cpu's pll configuration out of the mainboard
and into the cpu's Kconfig.

Change-Id: I72ee1baa3a96586fceff03ff43c5f61e2498667e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/9058
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-29 17:36:24 +02:00
Kyösti Mälkki f20046f5cf mainboard/intel: Drop unused onboard.h files
Change-Id: I0851375f419202f62ddc8c80fa77e1d8c95ed50f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/9991
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-29 16:57:12 +02:00
Patrick Georgi 815f4bfbbd Use __ROMSTAGE__ to denote romstage
There were some remaining places that used __PRE_RAM__ for
romstage, while it really means 'bootblock or romstage'.

Change-Id: Id9ba0486ee56ea4a27425d826a9256cc20f5b518
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10020
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-04-29 07:24:26 +02:00