Power down the eMMC controller via the AOAC interface when it's not
enabled in the devicetree.
BUG=b:184978118
TEST=On guybrush the unused eMMC controller is disabled in AOAC after
applying this patch. Before this patch it was enabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18f4626a29fdc422218777058341b0eae401bcd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
NCT6776's data sheet does say that the virtual LDN of GPIO base should
be 0x308, and most mainboards using it usually correctly config it in
devicetree.cb under the path 2e.308, but in nct6776.h it used to be
defined as 8 from the beginning (an ancient commit 1e3a22649a, lately
revived in commit f95daa510d), identical to the LDN of WDT, which
eliminates the definition of value 2e.308, and makes related resource
allocations unable to take effect. (in log we can find "PNP: 002e.308
missing read_resources" if 2e.308 is enabled and assigned with
resources)
In this commit, NCT6776_GPIOBASE is set to a value consistent with the
data sheet.
With this commit, resources under 2e.308 of NCT6776 can be allocated
successfully.
Change-Id: I604bad7ab34a8f57262fdec508e5952cf8eabf1c
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change follows other Intel SoCs common way to support SKUs with
bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and
allowing its detection at boottime. It completes support for HCV/DNV
after base SoC patch: commit ba936ce5db
soc/intel/denverton_ns: Ensure CPU device has a valid link
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)."
Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11
Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size
call evaluates to an empty string, so the file-size call will run
"cat | wc -c" which will cause make to get stuck in there. Also print a
message when no FSP-M file is specified that the resulting image won't
boot successfully.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This documentation doesn't add any more value. Thus, remove it.
Change-Id: I0402bc736c6cc77d88a836bddce8eadae8ec5d7c
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:194356991
TEST=ALC5682-VD/ALC5682-VS audio codec can work
Change-Id: I71b824c42c13cc2a8bebe0072de4a65ce238f074
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add supported memory part in the mem_parts_used.txt and generate the
SPD ID for the part. The memory part being added is:
MT53E512M32D1NP-046 WT:B
BUG=b:194223174
BRANCH=dedede
TEST=Build the boten board.
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I36fcbf7333fd9e85b28baa64676f8435aca63889
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update the USB port configuration based on driblee schematic.
USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 1
USB2 [3]: None
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: None
USB2 [7]: None
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: None
BUG=b:195622487, b:191732473
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56997
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add two thermal sensors for fan and wwan for DPTF based thermal control.
BRANCH=None
BUG=b:181271666
TEST=None
Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
This will add ACPI information to enable WACOM touchscreen.
TEST=Boot DUT and issue command:
$ ls -al /sys/bus/i2c/devices
WACOM PWB-D893 device should be listed and touchscreen should be functional.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Add the support RAM parts for Corori.
Here is the ram part number list:
DRAM Part Name ID to assign
H9HCNNNBKMMLXR-NEE 0 (0000)
K4U6E3S4AA-MGCR 0 (0000)
lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR
BUG=b:196744958
BRANCH=keeby
TEST=emerge-keeby coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ia11b5db145deeea838a8f5949accdb11e13342f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56988
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow schematic to modify USB port settings.
USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 0
USB2 [3]: None
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: None
USB2 [7]: Integrated Bluetooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: None
BUG=b:196998272
BRANCH=keeby
TEST=FW_NAME="corori" emerge-keeby coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2045b2be9d79bfd394fa4520faa0fb552a704206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57010
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the anahera variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:197850509
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ANAHERA
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id7649d56a8d6f85d12208f7ddaf2f71a7fe98e8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Ensure braces are consistent on all branches of a conditional statement,
as per the coding style.
Tested with BUILD_TIMELESS=1, Google Butterfly remains identical.
Change-Id: I34f3b22486e0f0712bc248477acb43012b21c5ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100
case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to
Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config
for the EM100 emulator case that has limited SPI frequency support.
Tested on Majolica by Martin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define
this function accordingly.
Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the `mainboard_fill_spd_data` function out of romstage, in
preparation to confine `pei_data` usage to as few files as possible.
Change-Id: I6447da4d135d920f9145e817bfb7f9056e09df84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55805
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variants only need to provide the SPD index and whether said index
corresponds to a dual-channel configuration, which can be achieved
without using `pei_data`. Add two functions that return the values
and use them in `spd.c` at mainboard level.
Change-Id: I9bc4527057d4a771883c8cc60da2501516d6fb94
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This change calls `add_more_links()` in `denverton_init_cpus()` if
`dev->link_list` is NULL. This condition can occur if mainboard does
not add any APIC device in the device tree.
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the
same SKU and steping (Intel Atom C3538)."
Change-Id: I6f453901b17f7eff22beed8dbf6995cdc9f9b776
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57152
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add GPIO "rt1011 reset" and i2c2 initialization for RT1011.
Add CHERRY_USE_RT1011 and CHERRY_USE_RT1019 to Kconfig, so we can
spearate code for the specific codec by config.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I18939a2a2caae0444ce17f4712764647975121ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57157
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently clear_screen() calls set_pixel() to set all pixels. However,
the actual order of pixels being set depends on the framebuffer
orientation. With NORMAL orientation, the framebuffer is accessed
sequentially; with LEFT_UP/RIGHT_UP orientation, it is accessed back and
forth, leading to performance drop (>1 second on bugzzy).
Therefore, ensure sequential access to the framebuffer, regardless of
the orientation.
BUG=b:194967458
TEST=emerge-cherry libpayload
BRANCH=dedede
Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57104
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, The SPI speed/mode configuration is split between Kconfig
and devicetree. We'd like to have everything in one place. Since we
need the fast-read speed and the mode available in the Makefile to build
the AMD EFS table, we currently need it in Kconfig. Move all of the
settings to Kconfig and remove them from Devicetree in a later commit.
BUG=b:195943311
TEST=boot majolica & guybrush, verify spi settings
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD support to drawcia for MT53E512M32D1NP-046 WT:B.
This part is already in global_lp4x_mem_parts.json.txt, and use
/util/spd_tool/lp4x/gen_part_id to assigns DRAM IDs.
BUG=b:196951879
BRANCH=firmware-dedede-13606.B
TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage
Change-Id: Ic42e6357943ba651ffd92fb2974e9ea52fa19020
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56905
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When modules are added to the FSP and they won't fit into the FSP binary
any more, the size can be increased in the FSP build. Especially in the
case of debug builds the increased size might not fit into the memory
region it gets decompressed into which starts at FSP_M_ADDR and has a
size of FSP_M_SIZE. SoCs can implement the soc_validate_fspm_header
function that ends up being called by the FSP driver in romstage to do
some additional checks on the FSP binary's header that includes the
version number and the image size. We can use the image size field to
check if it fits into the reserved region. Since the FSP-M memory region
is located after romstage loading it won't clobber the romstage code
where we do the check.
This runtime check is added in addition to the build-time check to also
cover the case when the FSP binaries in CBFS get replaced with ones that
don't fit into the reserved memory region after the coreboot build.
BUG=b:186149011
TEST=Mandolin still boots fine with the patch applied. When as a test
the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000
which is by far not enough for the decompressed FSP-M binary to fit into
it prints the newly added error message on the console and then stops.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL indroduces the ELOG_RW_REGION_NAME. This constant replaced the
hardcoded "RW_ELOG" value. This constant will be used also by elogtool
(see CL in the commit chain).
BUG=b:172210863
Change-Id: Ie8d31204e65fd67d52b0f8ced7b8c1ffdcf5b539
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56986
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit moves some drivers/elog/ functionality to commonlib/bsd
since they will be called from util/cbfstool/.
In particular:
* elog_fill_timestamp(), elog_update_checksum(), elog_checksum_event()
were moved to commonlib/bsd/elog
* elog_fill_timestamp() receives the time parameters and updates the
event based on the "time" arguments.
The original elog_*() functions were written by Duncan Laurie
(see CB:1311) and he gave permission to re-license the code to BSD.
BUG=b:172210863
Change-Id: I67d5ad6e7c4d486b3d4ebb25be77998173cee5a9
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
add CBI sku RAM ID 5 for 4GiB Capacity with dual channel and dual rank
with 4gb dram density.
BUG=b:178665760
BRANCH=Octopus
TEST=build fw and flash to the dut with RAMID 5, dut can boot up successfully.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I922a518cffc4dac71caec68e6f7a55c6c5717438
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56982
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Override USB port configurations based on the latest bugzzy schematics.
BUG=b:192521391
BRANCH=None
TEST=Built test coreboot image
Change-Id: I4368946f4175f4f065a3483dc7ca6068c6de3123
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
Change-Id: Ice4c727f2b75893cd012345a556fd21d9807dfaa
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
TEST=boot to OS, read PCI 0:0.0 config register 0x80, value is 0x31
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0c3e16edeab6f85a79eb10e1477d95952b554a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some FSPs provide a UPD to allow the bootloader to set the PAM lock bit
instead of the FSP, therefore add a function in the common code to do
this. Source: ADL & TGL FSP integration guides
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1d6642b496617b6e8ccda8a0aa6bfd88ea9dc3ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Rename soc_validate_fsp_version to soc_validate_fspm_header, since it
can not only be used to check the version info in the FSP-M binary's
header, but also to check every other field in the binary's header. This
is a preparation for a follow-up patch that implements this function to
check the FSP-M binary's size.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The FSP-M binary needs to fit into the memory region that starts at
FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time
if the uncompressed FSP-M file is larger than the size of the region it
will be copied into.
BUG=b:186149011
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Felix Held