Commit Graph

27080 Commits

Author SHA1 Message Date
Akshu Agrawal f9735dc760 mainboard/google/kahlee: Set PSPP setting to BalanceLow
With correct stapm values audio issue is not observed with
PsPPBalanceLow (Gen1 speed).

BUG=b:117569918
TEST=audio playback multiple times

Change-Id: Iaeae52b262b12622a6753432e3fc40bf5f0fd8e0
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/29028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-11 21:03:58 +00:00
Akshu Agrawal eb75f7c360 mb/google/kahlee: Set stapm parameters with time value fixed
stapm_time passed to smu via agesa is in msec. With earlier value
smu was getting stapm_time as 2.5 sec instead of 2500 sec and thus
causing issue in S3, and audio in PsppBalanceLow state.

BUG=b:117569918, b:117252463
TEST=
1.) audio works with PsppBalanceLow
2.) S3 cycles

Change-Id: I673e7e673d042918dff47141f37bbca354f5c45c
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/29027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-11 21:03:11 +00:00
Ronald G. Minnich 83bd46e5e5 selfboot: remove bounce buffers
Bounce buffers used to be used in those cases where the payload
might overlap coreboot.

Bounce buffers are a problem for rampayloads as they need malloc.

They are also an artifact of our x86 past before we had relocatable
ramstage; only x86, out of the 5 architectures we support, needs them;
currently they only seem to matter on the following chipsets:
src/northbridge/amd/amdfam10/Kconfig
src/northbridge/amd/lx/Kconfig
src/northbridge/via/vx900/Kconfig
src/soc/intel/fsp_baytrail/Kconfig
src/soc/intel/fsp_broadwell_de/Kconfig

The first three are obsolete or at least could be changed
to avoid the need to have bounce buffers.
The last two should change to no longer need them.
In any event they can be fixed or pegged to a release which supports
them.

For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage)
to 0xe00000 (14 Mib) which will put the non-relocatable x86
ramstage out of the way of any reasonable payload until we can
get rid of it for good.

14 MiB was chosen after some discussion, but it does fit well:
o Fits in the 16 MiB cacheable range coreboot sets up by default
o Most small payloads are well under 14 MiB (even kernels!)
o Most large payloads get loaded at 16 MiB (especially kernels!)

With this change in place coreboot correctly still loads a bzImage payload.

Werner reports that the 0xe00000 setting works on his broadwell systems.

Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11 17:42:41 +00:00
Patrick Georgi ce1064edd6 tegra124_lp0: make sure to build with compiler.h included
Fixes builds of that binary in clean trees.

Change-Id: If5a995449a74c00da836fcf22bda44ebc8197518
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-11 11:00:49 +00:00
Bora Guvendik 39363744cc commonlib/storage: Make pci sdhci code compile in romstage
In romstage malloc is not available, so use CAR_GLOBAL
variable instead.

BUG=b:78106689
TEST=Boot to OS

Change-Id: If9438d0b707c6ffaa61db80bd1d385112bc91cfc
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/25067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11 10:57:07 +00:00
Xiang Wang 4356e09235 riscv: add physical memory protection (PMP) support
These codes are written by me based on the privileged instruction set.
I tested it by qemu/riscv-probe.

Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28569
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11 10:56:54 +00:00
Bora Guvendik a08475e9ab soc/intel/common/block/gpio: check for NULL using if statement
Remove assert() and instead use if statement to check if
comm->groups is NULL.

Found-by: klockwork

BUG=None
TEST=Boot to OS

Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/28940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11 09:24:01 +00:00
Wisley Chen a07efab72a mb/google/octopus: I2C clock tuning for meep
Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.

BUG=b:117298114
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz

Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11 06:37:51 +00:00
Jonathan Neuschäfer 806ad196f3 Documentation: Improve message printed by livesphinx target
Printing "Autobuild finished" after the autobuild server exits (which
normally doesn't happen) is not very useful.

Change-Id: I909d7ab5f399993dbb1916e66ba94c48d7bc53bf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-11 01:22:35 +00:00
Jonathan Neuschäfer d3037bdf64 Documentation: Add and link the arch directory
Fixes: b159d5ba8f ("riscv: add documentation for stages and payloads")
Change-Id: I5ca8ed094c9b6d115da707375205872e782a66b2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-11 01:22:21 +00:00
Jonathan Neuschäfer a85951fb2f Documentation/releases: Improve readability
A colon usually indicates that something related follows. But in
Documentation/releases/index.md, nothing followed. Fix this by swapping
two lines.

Change-Id: I3e2750c208a2b725145b94615f64381ac763f0dc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-11 01:22:12 +00:00
Piotr Król 3c60375c57 payloads/tianocore: Fix not applying patch 06_CorebootPayloadPkg_keep_cb_table
Mentioned patch could not be applied in coreboot-sdk:1.52. With this fix
patch apply correctly.

Change-Id: I130856520f91bcfbd9a62741b1d5abb6495a6eac
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-11 01:20:06 +00:00
Patrick Rudolph 1e69b0a863 mb/cavium/cn8100_sff_evb: Only expose two UARTs
Only two UARTs are connected to the FTDI UART USB chip.

Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-11 00:58:31 +00:00
Furquan Shaikh 99d258afcb soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not
enabled on the platform. This is required to prevent unnecessary wakes
if the WAKE# pin remains not connected on the platform. Function to
set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as
well as S3 resume path (BS_OS_RESUME).

BUG=b:117284700
TEST=Verified that no spurious wakes are observed on nocturne.

Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-10 20:21:43 +00:00
peichao.wang d5325ddcc2 mb/google/octopus: Drop I2C bus 0 clock frequency for Phaser
Need to tune I2C bus 0 clock frequency under the 400KHz 
since this bus attached the Stylus EMR pen and need meet the spec.

Bug=b:117297214
TEST=flash coreboot to the DUT and measure I2C bus 0 clock
frequency whether under 400KHz

Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28973
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10 18:38:38 +00:00
Aaron Durbin 4b6f262ead lib: increase part number size in memory_info/dimm_info
The dimm_info and memory_info structs are used in devices that
don't strictly use DIMMs. Those platforms have the DRAM soldered
down so there's no DIMM part number that encapsulates the DRAMs
used in the DIMM. The full part number is desired to be exposed in
the SMBIOS tables. As such extend DIMM_INFO_PART_NUMBER_SIZE to 33
to accommodate longer part numbers

'MT53B256M32D1NP-053 WT:C' is one of the longer part numbers that
are desired to be maintained.

BUG=b:115697578

Change-Id: I0c39dd1d1c2f0776d70d8c4d8d56719779ff82ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-10 18:07:57 +00:00
Jens Drenhaus fe66a0760c soc/cavium: dynamic UART initialization for cavium cn8100
Now only those UARTs that are enabled in devicetree.cb are initialized.

Tested on Opencellular Elgon.

Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62
Signed-off-by: Jens Drenhaus <jens.drenhaus@9elements.com>
Reviewed-on: https://review.coreboot.org/28975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-10 16:37:38 +00:00
Chris Zhou 6ae7a2a101 mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPD
Add SPD file for sdp samsung_dimm_K4AAG165WB-MCRC (ram id: 9)

BUG=b:112679174
TEST=emerge-nami coreboot chromeos-bootimage

Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28974
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10 16:29:53 +00:00
Richard Spiegel d74df17eb4 mb/google/kahlee/variants/*/devicetree.cb: Reset I2C slaves
Use the new I2C slave reset function and reset all slaves connected to all
4 I2C. Do this in all boards.

BUG=b:114479395
TEST=Added debug code. Build and boot grunt. Examined output, confirmed
GPIO pins changing as required. Removed debug code.

Change-Id: Ia78ee5d5319d3c1a7daa9c56c81d435999b3a359
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28575
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10 16:29:29 +00:00
Richard Spiegel 5401aa207c soc/amd/stoneyridge/gpio.c: Create I2C slave reset code
AMD's SOC do not wait for I2C transactions to complete before executing
a reset. Because of this, it's possible for the reset to happen in the
middle of a transaction, resulting on a slave hang. There are 2 possible
solutions:
If the slave has a reset pin connected to a GPIO pin, it can be used to
reset the slave, else the only solution is to bang SCL 9 times. Create
code that makes it easy to implement SCL bang, using a devicetree
register to define which I2C SCL lines needs to be reset.

BUG=b:114479395
TEST=Build and boot grunt. Look at transactions on a scope.

Change-Id: I7f74b7e45c509044825355874753969f074e2382
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28574
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10 16:29:20 +00:00
Martin Roth 309210c980 mb/google/kahlee: Add delan variant
BUG=b:117173908
TEST=Build delan

Change-Id: If149b8c43ff16637c38d5320eb606bb72d62e953
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-10 16:27:27 +00:00
David Wu 9baff96e0e mb/google/fizz: Prepare sharing directory for variants
Clean up Kconfig file in order to support variants for fizz. Add
BOARD_GOOGLE_BASEBOARD_FIZZ that can be set by various fizz variants
to use the common baseboard configs.

BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot

Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-10 12:17:51 +00:00
Tristan Shieh 022f76b0d3 mediatek/mt8183: Init PLLs for DRAM
Set up DRAM related PLLs.
And update post divider table to fulfill all freqency settings.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/28667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2018-10-10 12:16:43 +00:00
Jonathan Neuschäfer 38dc00bed1 .gitignore: Spell Documentation in uppercase
Fixes: 4d8b843d37 ("Rename documentation -> Documentation")
Change-Id: I423cb159ca3c837ed52937dc6d76d9a43a069256
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-10 12:16:13 +00:00
Angel Pons 49c8de74ee util/superiotool/smsc.c: Add SCH5504 register dump
There is no datasheet available for this SuperIO, but dumping all
possible registers on a Dell Optiplex GX520 resulted in data that was
similar to other supported chips. Data also matches what is set in the
BIOS, e.g. the parallel and serial ports' addresses.

Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-10 11:19:01 +00:00
Subrata Banik c8a842b708 soc/intel/cannonlake: Add PCIE ASL entry
This patch creates _PRT entires for each PCIE root port devices.

TEST=Able to see PCIE wake device in cat /proc/acpi/wake list

Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09 20:12:17 +00:00
Subrata Banik a0729899d7 soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices
This patch provides option for PCI IRQ mapping in both PIC and APIC mode.

TEST=Build and Boot on CNL RVP.

Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09 20:12:01 +00:00
Subrata Banik 50cdce9575 soc/intel/common/acpi: Fix ACPI Namespace lookup failure, AE_ALREADY_EXISTS issue
This patch fixes below ACPI compilation issue:

Found 1 external control methods, reparsing with new information
Pass 1 parse of [DSDT]
ACPI Error: [EPCS] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660)
ACPI Error: [EMNA] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660)
ACPI Error: [ELNG] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660)
Pass 2 parse of [DSDT]
ACPI Warning: NsLookup: Type mismatch on EPCS (Integer), searching for (RegionField) (20160318/nsaccess-664)
ACPI Warning: NsLookup: Type mismatch on EMNA (Integer), searching for (RegionField) (20160318/nsaccess-664)
ACPI Warning: NsLookup: Type mismatch on ELNG (Integer), searching for (RegionField) (20160318/nsaccess-664)
Parsing Deferred Opcodes (Methods/Buffers/Packages/Regions)

TEST=Able to build sgx.asl without any ASL error.

Change-Id: If4e7d4c66b6aab6c081fa272d8c2c9a1f0651ef7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09 20:11:37 +00:00
Subrata Banik ee941635e6 soc/intel/common/block/pcr: Add NULL pointer check in pcr_execute_sideband_msg()
This patch to fix KW issue due to msg, data and response pointers NULL
check fail.

Change-Id: I39324514079f240ba1683a04e579de85485299bf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09 20:11:21 +00:00
Subrata Banik 7cf9862657 soc/intel/cannonlake: Disable Legacy PME for Root ports
Legacy PME are enabled by default in FSP-S UPD. This policy sets
PME Interrupt Enable (PIE) bit of RCTL register to trigger interrupt
generation when RSTS.PS state has changed (either due to 0->1 transition
or due to this bit being set with RSTS.PS already set). Due to this
interrupt generation, system wakes from sleep immediately it enters.

This patch overrides root port legacy pme upd policy from coreboot to
ensure no false SCI is triggerd when system is in S3/S0ix state.

BUG=b:113083354
BRANCH=none
TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase
without any failure.

Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09 20:11:00 +00:00
Subrata Banik 819b143925 soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers
This patch save and restore ITSS IPCx register before and after
FSP-S call.

Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-09 20:10:12 +00:00
Subrata Banik 46caf09598 soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
This patch save and restore ITSS IPCx register before and after
FSP-S call.

Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09 20:10:00 +00:00
Subrata Banik 1f33a0c799 soc/intel/common/pch: Select Kconfig for ITSS polarity configuration
This patch selects Kconfig for Intel Core Platform in order to ensure
proper ITSS IPCx programming.

Change-Id: I81e75e17ceb23c364b78300c3950144be1580700
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09 20:09:46 +00:00
Chris Zhou 3087bf5283 mb/google/kahlee/variants/liara: Update H1/TP/TS i2c timings
After adjustment on Liara EVT
H1: 392.03 KHz
TP: 397.87 KHz
TS: 397.71 KHz

BUG=b:116309237
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
     measure by scope

Change-Id: Ib5d7ce09ac58f33ee826d7541e1a0d14a03add9a
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-09 14:33:22 +00:00
Philipp Hug 56dceb2e1a payloads: Only show supported payloads in menuconfig
Some payloads don't depend on their supported platforms, which makes
them visible in menuconfig even if they are not supported (yet).

Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-09 11:29:52 +00:00
Nico Huber e3c05c4a3f util/cbmem/Makefile: Remove .dependencies on `clean`
Change-Id: Ic122b3eaed54e29bbb3e11de84822169c81c04eb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-09 07:08:18 +00:00
Angel Pons fa6ff60c8c util/superiotool/smsc.c: Add some register dumps
The SCH3112, SCH3116 and SCH5127 were lacking a pin dump. Since their
datasheets are available, add their pin dumps.

The SCH3112, SCH3114 and SCH3116 are almost identical, they only differ
in the number of serial ports. Some values in the SCH3114 dump were
inaccurate, that has been fixed as well.

Datasheets used:
 - SCH311X: DS00001872A
 - SCH5127: DS00002081A

Change-Id: Ic985526be9b09e0452eaf883904dfaf709b7e907
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-08 17:54:27 +00:00
Akshu Agrawal dd14029457 mainboard/google/kahlee: Set PSPP setting to BalancedHigh
Setting default PSPP setting to BalancedLow was causing audio
playback issue in most of the units. With BalancedLow either there
was no sound or noise on playback.
Switching to BalancedHigh as default option.

BUG=b:116553085, b:112020107
TEST=Test playback and hear proper audio.

Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/28967
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 17:22:57 +00:00
Nico Huber d44221f9c8 Move compiler.h to commonlib
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.

Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.

Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08 16:57:27 +00:00
Subrata Banik 834543c0c7 soc/intel/skylake: Fix ‘dev’ pointer NULL before being dereferenced
This patch fixes KW issue due to pointer being NULL and will be dereferenced

Change-Id: Iedb59daf5f448e31c0097873a086e4d08cd4a979
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28948
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 14:49:18 +00:00
Pan Sheng-Liang f7cc469139 mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for Bobba
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 3 for DVT.

BUG=b:115697578
TEST=verified it in Bobba EVT board which rework ram id.

Change-Id: I0fb457d8772f5038e5d90188d7682956ddfad46b
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28891
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 14:45:46 +00:00
Patrick Georgi 9360feaf51 smmstore: Add a key/val store facility in flash, mediated through SMM
It exposes an interface that is as generic as possible, so payloads
and/or kernels can use it for their data.

Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25182
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 09:46:30 +00:00
Elyes HAOUAS 88607a4b10 src: Use tabs for indentation
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 09:46:16 +00:00
Nick Vaccaro d9169f826a mb/google/poppy/variant/nocturne: correct wifi wake register
Wifi wake register is incorrectly set in devicetree.
Set wifi wake to its correct wake source, GPE0_DW2_01.

BUG=b:117330593
TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture,
connect wifi to a hotspot, suspend device, echo freeze >
/sys/power/state, and then shutdown the hotspot and verify device
wakes.

Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28938
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 09:45:39 +00:00
Nick Vaccaro 82aa8f8d7b mb/google/poppy/variant/nocturne: Disable WAKE# signal
The WAKE# signal has moved to LAN_WAKE, so WAKE# is now
floating and must be disabled.  This change disables WAKE#.

BUG=b:117284700
TEST=none

Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-08 09:45:36 +00:00
Elyes HAOUAS ef20ecc92b nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address
Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-08 09:44:56 +00:00
Patrick Rudolph 6f027ff28a Documentation: Improve elgon documentation
* Convert PNG to JPG and reduce image quality.
* Mark flash IC and USB serial connector.
* Mark SPI programming header.
* Add programming header pinout.

Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-08 08:45:17 +00:00
Patrick Rudolph 17856b720b util/intelvbttool: Rewrite tool
* Add Makefile dependency to source file
* Add argument support
* Add help support
* Print usage on wrong arguments
* Add support for parsing VBT binary file
* Add support for parsing PCI Option ROM
* Add support for writing VBT binary file
* Add support for patching PCI Option ROM
* Keep support for accessing legacy VGA area Option ROM
* Keep support for dumping VBT contents to stdout

Allows to extract VBT, analyse VBT and patch PCI Option ROMs as needed.

The required arguments have been changed:

./intelvbttool --<SOURCECMD> [filename] --<DESTCMD> [filename]

SOURCECMD set the VBT source. Supported:
 inlegacy  : Legacy BIOS area at phys. memory 0xc0000
 invbt     : Read raw Intel VBT file
 inoprom   : Read VBT from Intel Option ROM file

DESTCMD set the VBT destination. Supported:
 outdump   : Print VBT in human readable form
 outvbt    : Write raw Intel VBT file
 patchoprom: Patch existing Intel Option ROM

Any combination of SOURCECMD and DESTCMD is possible.

Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-08 02:33:06 +00:00
Jonathan Neuschäfer fd29ff3555 Documentation/mb/sifive: Fix dead links
SiFive's website was reorganized, which broke our links to PDF files.
Update these links to the current ones, obtained by browsing
https://sifive.com/documentation/.

Change-Id: I312de84bf12abb0789bdd971c40033f1e4ea0dd1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06 21:32:11 +00:00
Jonathan Neuschäfer 50b74b2a27 arch/riscv: Update comment about mstatus initialization
coreboot does not set up virtual memory anymore.

Change-Id: I231af07b2988e8362d1cdd606ce889fb31136ff1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06 21:30:32 +00:00