Previous setting was correct but assumed SMI handler is
always located at the beginning of TSEG. Break the assumption.
Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The callers don't necessarily check return value of
function. Make sure the parameters are not left
uninitialised in that case.
Change-Id: Ic02db2d35b2ec88506320e7df609940de4aef005
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34708
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do this to avoid some amount of explicit typecasting
that would be required otherwise.
Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is declared weak so that platforms that do not
have smm_subregion() can provide their own implementation.
Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add explicit CBMEM_STAGE_CACHE option. Rename
CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE.
Platforms with SMM_TSEG=y always need to implement
stage_cache_external_region(). It is allowed to return with a
region of size 0 to effectively disable the cache.
There are no provisions in Kconfig to degrade from
TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE.
As a security measure CBMEM_STAGE_CACHE default is changed to
disabled. AGESA platforms without TSEG will experience slower
S3 resume speed unless they explicitly select the option.
Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
No need to limit these declarations to FSP. Both
PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE
can be built on top of this.
Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This implementation adds support to provide list of LPSS controllers
for a canonlake and icelake platforms. It implements strong function
of get_soc_lpss_controllers defined under intel common block lpss
driver.
Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add an API to check if device is a LPSS controller. This API can be
used for IRQ assignments for LPSS PCI controllers, since the LPSS
controllers have a requirement of unique IRQ assignments and do not
share same IRQ# with other LPSS controllers.
SOC code is reponsible to provide list of the LPSS controllers
supported and needs to implement soc_lpss_controllers_list API,
in case it needs to use this common implementation.
Change-Id: I3f5bb268fc581280bb1b87b6b175a0299a24a44a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34137
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This implementation revises the UART PCI device reference in common
UART driver. The SOC functions have been aligned to provide the UART
PCI device reference using pcidev_path_on_root.
The uart_get_device() return type is changed, and files in which
it gets used are updated.
Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.
Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clear the GPI Interrupt Status & Enable registers to prevent any
interrupt storms due to GPI.
BUG=b:138282962
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot-up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.
Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This patch ...
- adds the PCH ID for C232 chipset,
- renames "Premium" chipset to "HM170" (because of same IDs),
- reorders the Skylake-H PCH IDs ascending by hex values.
Used documents:
- Intel 332690-005EN
Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The initial implementation was assigning the devfn as PCI device
reference directly which was incorrect.
Change-Id: Iad57e9bc6b2acf1823ee38116aea8a93feece6f9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.
Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33129
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There were two hooks in the boot state machine which dumped the ME
status to the debug UART, which is unnecessary. Removed the hook
for the BS_OS_RESUME_CHECK state, leaving just BS_PAYLOAD_LOAD, which
is called before FspNotifyEndOfFirmware, as required.
BUG=b:138463532
BRANCH=none
TEST=Boot up, check cbmem to ensure the ME status messages are
only printed one time.
Change-Id: I86bc6e33de4096f33023730ffabb25715c985de0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
There will be a possible out of bounds array access if
power_limit_1_time == ARRAY_SIZE(power_limit_time_sec_to_msr), so
prevent that in the index check. This issue was fixed for other cpus in
commit 5cfef13f8d (cpu/intel: Fix out-of-bounds read due to off-by-one
in condition). Based on the discussion for that commit, also remove the
magic constant 28 in favour of the index of the last array element.
Change-Id: Ic3f8735b23a368f8a9395757bd52c2c40088afa1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This reverts commit 46445155ea.
Reason for revert: Breaks coreboot. Either no UART working or the
complete boot process stops.
Platform: Intel Apollolake, tested on Up Squared
Change-Id: If581f42e423caa76deb4ecf67296a7c2f1f7705d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Consider the following assignment:
u64 = s32
For positive values this is fine, but if the s32 is negative, it will be
sign-extended in the conversion to a very large unsigned integer. This
manifests itself in two ways in the following code:
First, gpu_pipe{a,b}_port_select are defined as int, and can have the
values 1 or 2. In the case when they have the value 2, the shift 2 << 30
will be a negative number, making it susceptible to the sign-extension
problem above. Change these variables to something more reasonable like
a uint8_t, which is unsigned.
Second, in any bit shift, any variable with width less than an int will
be implicitly promoted to an int before performing the bit shift.
For example, the variable gpu_pipea_power_on_delay is a uint16_t, and if its
highest bit is set, the shift gpu_pipea_power_on_delay << 16 will become
negative, again introducing the above problem. To prevent this, cast all
smaller variables to a u32 before the shift, which will prevent the
implicit promotions and sign extensions.
Change-Id: Ic5db6001504cefb501dee199590a0e961a15771b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229699, 1229700, 1229701, 1229702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34487
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prevent implicit cast to pointers.
The compiler doesn't warn about the conversion from
integer to pointer without a cast, because SA_DEV_ROOT
is literally '0' and there seems to be an exception
for that conversion.
Change-Id: I64fc156e3b9f578414ad03a00edb7cf3e33205c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The "internal PME" wake-up source could be from integrated LAN,
HD audio/audio DSP, SATA, XHCI, CNVi, or an ME maskable host wake.
chromium:1680839 adds USB port details to the wake-up when the
XHCI causes the wake-up. Expand the logging for wake-up details to
identify and log the other wake-up sources with more details. Note that
wake on Integrated LAN (GbE), SATA, and ME Maskable Host Wake are not
in use on Hatch, so these will not be tested.
BUG=b:128936450
BRANCH=none
TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference
libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch
coreboot chromeos-bootimage``
Ensure /build/hatch/firmware/image-hatch.serial.bin has been built.
Program image-hatch.serial.bin into the DUT using flashrom.
Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via
servo).
XHCI USB 2.0
* Plug a USB keyboard into a USB-A port
* ``powerd_dbus_suspend``
* Verify low power mode by issuing the ``powerinfo`` command on the EC
console (via servo). Expect to see ``power state 4 = S0ix``.
* Press a key on the USB keyboard
* ``mosys eventlog list`` shows:
12 | 2019-06-26 14:52:23 | S0ix Enter
13 | 2019-06-26 14:53:07 | S0ix Exit
14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3
15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109
CNVi (connected to Wi-Fi):
* Enable wake on disconnect via ``iw phy0 wowlan enable disconnect``
* Set up a hotspot on an Android phone
* Connect the Chromebook to th hotspot
* ``powerd_dbus_suspend``
* Verify low power mode by issuing the ``powerinfo`` command on the EC
console (via servo). Expect to see ``power state 4 = S0ix``.
* Turn off the hotspot on the phone
* ``mosys eventlog list`` shows:
8 | 2019-07-11 10:58:17 | S0ix Enter
9 | 2019-07-11 10:59:17 | S0ix Exit
10 | 2019-07-11 10:59:17 | Wake Source | PME - WIFI | 0
11 | 2019-07-11 10:59:17 | Wake Source | GPE # | 109
XHCI USB 3.0
* TBD
HD Audio
* TBD
Change-Id: I2c71f6a56b4e1658a7427f67fa78af773b97ec7f
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34289
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates new kconfig option to bring display over external
PCI based GFX card. This kconfig to select required kconfig which are
not default selected by VGA_ROM_RUN to launch legacy oprom from pci
based GFX card.
Change-Id: I8ebde69e38defbe3321eb5e5bbd632c209ae2cd8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Set the controller state to D0 during the GSPI sequence,this ensures
the controller is up and active.
BUG=b:135941367
TEST=Verify no timeouts seen during GSPI controller enumeration
sequence for CML and ICL platforms.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Set the controller state to D0 during the uart init sequence, this
ensures the controller is up and active.
One more argument struct device *dev has been added
to uart_lpss_init function for the same.
BUG=b:135941367
TEST=Verify no timeouts seen during UART controller enumeration
sequence in CML and ICL platforms.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0187267670e1dea3e1d5e83d0b29967724d6063e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34447
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit bde6d309df (x86: Change MMIO addr in
readN(addr)/writeN(addr, val) to pointer) accidentally changed
the type of reg32 to a u8 *, so change it back to a u32.
Change-Id: If6beff17ed3ddf85889aba5f41d1ba112cd74075
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402160
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All the PCI accesses in the file are now accessed
without SA_DEV_ROOT expanding to function call.
Change-Id: I30d331e9c18a486ea971e8397a6e20a0f82d5f84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since PCH_DEVFN_PMC device is a PCI device that may be
hidden from enumeration, use SA_DEVFN_ROOT instead to
locate the SOC configuration.
Change-Id: I4b5195827fb32ec1dbd0bd6c9e243f4f9a4775ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to the documentation [1], by default the RX Level/Edge Trig
Configuration set to disable (2h = Drive '0') for each pad. Since this
setting doesn't matter for the GPO pad, there is no need to change the
default value for such pads. The patch updates PAD_CFG_GPO* macros to
set trig to disable. It also resolves some problems of creating the
PCH/SoC pads configuration based on information from the inteltool
dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
https://www.intel.com/content/dam/www/public/us/en/documents/
datasheets/100-series-chipset-datasheet-vol-2.pdf
[2] https://review.coreboot.org/c/coreboot/+/34337
[3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In the case there is no the circuit diagram for motherboard, the
PCH/SoC GPIOs config is based on information from the inteltool
dump. However, available macros from gpio_defs.h can't define the
pad configuration from this dump:
0x0440: 0x0000002084000500 GPP_A8 CLKRUN#
0x0448: 0x0000102184000600 GPP_A9 CLKOUT_LPC0
0x0450: 0x0000102284000600 GPP_A10 CLKOUT_LPC1
To convert these raw DW0/DW1 register values to macros, the following
parameters must be set:
func - pad function,
pull - termination,
rst - pad reset config,
trig - rx level/edge configuration,
bufdis - rx/tx (in/output) buffer disable.
The patch resolves the above problem by adding a new macro for the
native function configuration:
PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig)
These changes were tested on Asrock H110M-DVS motherboard [2].
It also resolves the problem of automatically creating pads
configuration [3,4]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
https://www.intel.com/content/dam/www/public/us/en/documents/
datasheets/100-series-chipset-datasheet-vol-2.pdf
[2] https://review.coreboot.org/c/coreboot/+/33565
[3] https://github.com/maxpoliak/pch-pads-parser/issues/1
[4] https://github.com/maxpoliak/pch-pads-parser/commit/215d303
Change-Id: If9fe50ff9a680633db6228564345200c0e1ee3ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34337
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bit 18 of MSR_POWER_CTL is documented as reserved, but we're setting it on
Haswell in order to enable EPB. It seems to work on SKL/KBL as well, so
do it there too.
Signed-off-by: Matthew Garrett <mjg59@google.com>
Change-Id: I83da1a57a04dac206cc67f2c256d0c102965abc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
