1) Both SAR sensors had a UID of `2`, making them indistinguishable
2) No `device` underneath max98357a `chip`
Change-Id: Icf586229532819a7779652cbee73755b036dfbdc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The serirq enable bit defaults to true, so if we want it disabled, we
need to explicitly disable it.
BUG=b:180631748
TEST=Boot majolica and see spurious IRQ 9 gone.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Even though `device` entries are children of `chip` entries in the
devicetree source format, the chips in the translated C structures
are only hooked up to device nodes. Hence, to configure a chip in
a device- or overridetree, it always needs a `device` below it.
This should fix docking events for the X200 ThinkPad.
Change-Id: I561e7ae81f2e096a091868ce51daa1c8f66af067
Signed-off-by: Nico Huber <nico.h@gmx.de>
Found-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kevin Keijzer
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing.
BUG=b:180721202
TEST=builds
Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
For consistency with newer platforms, do this in pch.c instead.
Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The MRC cache driver assumes BOOT_DEVICE_MEMORY_MAPPED=y already. This
is to ease factoring out common code across seven Intel platforms.
Change-Id: I0598cb18b456e10789b2a42792fbfa2639cdd2c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50951
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RAM is not yet configured in bootblock. This function was copy-pasted
from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in
there can be removed as nothing else uses them.
Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It only calls `smbus_common_init()`, so just call that directly.
Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Backport commit 03ed5bff5c (soc/intel/cannonlake: Move tco_configure to
bootblock), commit bb50c67227 (soc/intel/tigerlake: Move tco_configure
to bootblock) and commit 60c619f6a3 (soc/intel/jasperlake: Move
tco_configure to bootblock) to other platforms. This is for consistency.
Change-Id: I31fd0ceb67eacf30aefa457d757bf0d7f4cd7e87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's two instances of the same function, one for the bootblock and
another for romstage. Prefix them with the stage they are executed in.
Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to document 332691-003EN (SPT-H datasheet volume 2), the
hardware defaults to 0x44, which matches what newer platforms use.
Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is to align with newer platforms.
Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The iGPU is on the northbridge or system agent, not the southbridge.
Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Avoid a Secure OS Abort. This prevents coreboot timing out on C2P
mailbox commands and allows HDT unlocking.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I358530a1ba959ee1896e26a47853c9918ee124b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
DPR register's size field is given in whole MiB, so correct where it is
used to ensure the correct size multiple (KiB vs. MiB) is used with it.
Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling")
Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function returns true if any GPIO pad is programmed to route the
given IRQ to the IO-APIC. It does so by keeping track of which pads are
routed to IOxAPIC and looking this up in the new function.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This code will eventually support both ME 9.x and ME 10.
Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide.
Clamp any values that would overflow this field. Bits in TC_DTP already
get set when the tXP and/or tXPDLL values are large.
Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill the ECC type in `struct memory_info` in romstage, and in SoC code.
The SMBIOS override is unnecessary, and this is not mainboard-specific.
Change-Id: I8370b3ee7d75914b895946b53923598adf87b522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are platforms that support error correction types other than
single-bit ECC. Extend meminfo to accomodate additional ECC types.
It is assumed that `struct memory_info` is packed to save space. Thus,
use `uint8_t` instead of an enum type (which are usually 4 bytes wide).
Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
Measured I2C frequency just as below after tuning:
touchpad:372 kHz
audio codec RT5682:386.8 kHz
speaker AMP L:387.5 kHz
speaker AMP R:388.9 kHz
BUG=b:181342340
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I05d78c088190e349281a34b2aeed39ae8d867dc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If a previous build failed or the build dir is still around for other
reasons (e.g. buildgcc's `-t`) the symbolic link to our `bin` dir we
create there is also still around and can't be created again without
removing it first. Attempts to use `ln -f` also fail as the existing
destination is treated as directory and a new symbolic link would be
created inside.
Change-Id: I7a2720b0286e33d1ba26ea01f323dbf4f8afaea0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds new soundwire device ALC1308
The codec properties are filled out as best as possible
with the datasheet as a reference.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
The unique ID is calculated from schematics by referring to ASEL[1:0]
strap settings. Datasheet of ALC1308 provides info about the mapping of
ASEL strap settings to unique ID
For example this device is connected to master link ID 1 and has strap
settings configuring it for unique ID 2.
chip drivers/soundwire/alc1308
register "desc" = ""Left Speaker""
device generic 1.2 on end
end
Bug=None
Test=Build and boot on TGLRVP.Extract SSDT and confirm that the entries for
PCI0.HDAS.SNDW are present for ALC1308
Test speaker out functionality
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ibf3f1d5c6881cbd106e96ad1ff17ca216aa272ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51042
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sathyanarayana Nujella
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit d510b60f5b.
This patch includes the DSDT ASL code for shadowmountain board.
BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch includes the ramstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SMBIOS type 17 asset tag. Use dimm locator as default value.
Tested=Execute "dmidecode -t 17" to check asset tag field is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I323e6b4cf6b11ede253d5a2a4bfc976a3f432b05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently, this function is only invoked for the SPI device through
common SoC code. Since both Intel Harcuvar and Scaleway Tagada have
enabled the SPI device in the devicetree, there's no need to use the
debug version of `pcidev_path_on_root`.
Change-Id: I4340d5860d23c2fa230105f7a7d345c367b2b2aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50128
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Jakub Czapiga