Commit Graph

33561 Commits

Author SHA1 Message Date
Wonkyu Kim e3bf8ba2d8 mb/google/volteer: Enable RP LTR setting
BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:52:25 +00:00
Wonkyu Kim 5943117647 soc/intel/tigerlake: Configure RP setting
Add LTR and AER configuration to the root ports config.

BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:52:16 +00:00
Nick Vaccaro ba41ee1f0a mb/google/volteer: fix incorrect fields in SPDs
According to Intel Document #616599,
  1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10
     columns)
  2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel
     x16)

This change fixes those two values in the existing SPD files for
Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a
generic SPD).

BUG=b:152827558
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
Volteer to kernel.

Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-04-14 09:50:41 +00:00
Nick Vaccaro 5926fb5035 mb/google/volteer: fix CROS_GPIO_WP_AH export
Fix GPIO_PCH_WP (GPP_B11) to associate GPP_PCH_WP with community
zero instead of community 1.

BUG=b:152876091
TEST="emerge-volteer coreboot chromeos-bootimage", flash, boot to
and log into Volteer kernel, execute "wp enable" in H1 console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in H1 console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.

Change-Id: I082154efd72459ec54999ed7c7bb7420a38f7b6e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14 09:50:32 +00:00
dalao 56a25a98db mainboard/lenovo: Use the original hardware ids for keyboard/pointing
Currently coreboot is using the compatible ID PNP0303 for all keyboards
and PNP0F13 for all pointing devices, which causes some problems. On
Windows, the touchpad driver can't be automatically matched and
installed through Windows Update. On Linux, there are some strange
issues. So it's better to use the original hardware IDs for each model.
The hardware IDs for the following models can be found By searching for
dmesg logs on vendor BIOS:

T60: https://mail.gnome.org/archives/networkmanager-list/2012-January/msg00110.html
Keyboard: PNP0303 Pointing: IBM0057

R60: https://openbenchmarking.org/system/1202279-AR-COMPRESS715/Lenovo%20R60/dmesg
Keyboard: PNP0303 Pointing: IBM0057

X60: https://github.com/pavelmachek/missy/blob/master/db/notebook/lenovo/thinkpad/x60/pavel/2018.3648803539788/dmesg.out
Keyboard: PNP0303 Pointing: IBM3780

X200: https://ubuntuforums.org/showthread.php?t=1833248&page=2
Keyboard: LEN0010 Pointing: IBM3780

T400: https://github.com/heradon/libreboot-fork/blob/master/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log
Keyboard: LEN0010 Pointing: IBM3780

T510: https://bbs.archlinux.org/viewtopic.php?id=120287
Keyboard: PNP0303 Pointing: LEN0015

T410: https://forum.ubuntuusers.de/topic/kein-sound-109/
Keyboard: PNP0303 Pointing: LEN0015

T420: https://linux-hardware.org/index.php?probe=e6a094ade5&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T420s: https://bbs.archlinux.org/viewtopic.php?id=191510
Keyboard: PNP0303 Pointing: LEN0015

T520: https://bbs.archlinux.org/viewtopic.php?id=195636
Keyboard: PNP0303 Pointing: LEN0015

W520: https://linux-hardware.org/index.php?probe=9306cac54c&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T430: https://github.com/farjump/fwtr/blob/master/lenovo/thinkpad-t430/2347ds2/lenovo/g1et73ww-2.09/fwts/20160218_174223/dmesg.log
Keyboard: PNP0303 Pointing: LEN0015

T430s: https://linux-hardware.org/index.php?probe=01545dc8fb&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T530: https://forums.fedoraforum.org/showthread.php?316640-Fedora-27-High-CPU
Keyboard: LEN0071 Pointing: LEN0015

W530: https://bugs.freedesktop.org/attachment.cgi?id=115557
Keyboard: LEN0071 Pointing: LEN0015

L520: https://pastebin.com/U6MaBAY3
Keyboard: PNP0303 Pointing: LEN0017

X201: https://linux-hardware.org/index.php?probe=d7085ee4c8&log=dmesg.1
Keyboard: PNP0303 Pointing: LEN0018

X220: https://bbs.archlinux.org/viewtopic.php?id=237669
Keyboard: PNP0303 Pointing: LEN0020

X230: https://forums.bunsenlabs.org/viewtopic.php?id=2460
Keyboard: PNP0303 Pointing: LEN0020

X131e: https://linux-hardware.org/index.php?probe=d765880811&log=dmesg
Keyboard: MSF0001 Pointing: LEN0026

X1 Carbon Gen 1: https://bugzilla.kernel.org/show_bug.cgi?id=85851
Keyboard: LEN0071 Pointing: LEN0030

s230u: https://launchpadlibrarian.net/147231958/dmesg-reboot.txt
Keyboard: PTL0001 Pointing: LEN0031

T540p: https://linux-hardware.org/index.php?probe=da766a30bc&log=dmesg
Keyboard: LEN0071 Pointing: LEN0034

X240: https://linux-hardware.org/index.php?probe=fa7155b0e4&log=dmesg
Keyboard: LEN0071 Pointing: LEN0035

T440p: https://bugzilla.kernel.org/show_bug.cgi?id=91541
Keyboard: LEN0071 Pointing: LEN0036

T440s: https://bugzilla.kernel.org/show_bug.cgi?id=91541
Keyboard: LEN0071 Pointing: LEN0036

T450: https://gist.github.com/kzar/1c38630eb22e4bf5b976
Keyboard: LEN0071 Pointing: LEN200e

Others:
https://github.com/torvalds/linux/blob/master/drivers/input/mouse/synaptics.c

Test result: This can make Windows automatically install the Lenovo
touchpad driver. It also fixes the T440p touchpad issue.

Change-Id: Ifb635da99c5e05f987aaf4f172108d788dcc2932
Signed-off-by: dalao <dalao@tutanota.com>
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36371
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:50:10 +00:00
Wim Vervoorn 65535332db mb/facebook/monolith: Add fmd files for 6MB BIOS area
The current flash layout requires changes to the descriptor area to
create the 9MB BIOS region.

Add fmd files that allow switching to coreboot by only replacing the
BIOS region.

BUG=N/A
TEST=tested on facebook monolith

Change-Id: I2b003018e245693934202505d7e3891c2f545e6c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-04-14 09:49:10 +00:00
Patrick Rudolph fc8867c3d8 mb/lenovo: Add additional FMAPs for stripped ME
Make it easier to use measured boot with stripped ME by
providing the corresponding FMAPs.

Change-Id: I1763583a42bbc91e6acc06b262deab10d34447a3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-04-14 09:48:55 +00:00
Marcello Sylvester Bauer 45a354fe78 mb/lenovo/*: Add vboot RO FMAPs on 12MiB devices
Tested on W530

Change-Id: I9be0c5e06fcb8287d32171cb72dabb5fcf047e7a
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39450
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:48:44 +00:00
Duncan Laurie c68902c210 Update vboot submodule pointer
Update the pointer for vboot_reference so it can be used to compile
depthcharge payload on the master branch.

Change-Id: I5fc6e05896d7221a1e48ca86c6b15081488302b5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14 09:47:56 +00:00
Duncan Laurie 287cf6c7d1 lp/drivers/usb: Work around QEMU XHCI register issue
The QEMU XHCI controller does not support byte/word reads from the
capability register and it expects dword reads only.

In order to make this work move the access of the capability
register fields to use macros instead of a packed struct bitfield.

This issue was filed upstream:
https://bugs.launchpad.net/qemu/+bug/1693050

The original fix attempt in 2012 was not effective:
6ee021d410

With this change the controller is detected properly by the libpayload
USB drivers.

Change-Id: I048ed14921a4c9c0620c10b315b42476b6e5c512
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 09:47:22 +00:00
Brandon Breitenstein bc885c194c google/chromeec: Add USB MUX Interrupt
Kernel relies on the USB MUX interrupt to configure USB devices that
are connected on the Type-C ports for TGL. Adding in the Q1C Interrupt
so the Kernel can properly receive and configure USB devices

BUG=b:152902608
TEST=buld_packages for volteer and verified that Proto 1 and Proto 2
are now seeing extcon events

Change-Id: Ie3a2f829a295f090a03e72e12f19ecc5bb724952
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Prashant Malani <pmalani@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13 23:39:29 +00:00
Patrick Rudolph 56a3ef2e74 acpi: Bump MADT to revision 3
Add structs and methods for revision 3.

Change-Id: Ida75f530551ad2b8b20ce7fdeffb3befc51296bc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13 23:32:27 +00:00
Patrick Rudolph c02bda0f06 acpi: Bump FADT to revision 6
Some of the revision 4 FADT fields were already updated to ACPI
spec revision 6, but not all of them. In addition the advertised
FADT revision was 3.

Implement all fields as defined in version 6 and bump the advertised
FADT revision to 6.

Also set all used access_size fields and x_gpe0_blk to sane values
as Windows 10 verifies those fields starting with FADT revision 5.

Fixes: https://ticket.coreboot.org/issues/109

Tested on Windows 10.

Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13 23:32:15 +00:00
Varun Joshi 2255ebaa23 mb/google/deltaur: Add support to enable GbE on variant
- Configure devicetree for enabling GbE on variant
  and remove from baseboard.
- Configure Kconfig to enable GbE region.
- Configure fmd to incorporate GbE.

BUG=b:151102809
Cq-Depend: chrome-internal:2843183
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I1c36b132546049e3e775585c41164072f4ece73e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-04-13 20:28:18 +00:00
Anil Kumar c6f5b05cf3 mb/google/deltaur: Return SKU ID info
For Deltaur and Deltan variants return proper SKU ID based on EC
firmware type and sensor detect GPIO value

BUG=b:152544516
TEST=make build successful for deltan

Change-Id: I20a497739e5062400b093648c3a634203dec6105
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-13 20:26:54 +00:00
Varun Joshi 06684979f9 mb/google/deltaur: Update onboard memory config
Update dq, dqs map based on deltan schematics.
Configure memory to read SPD.

BUG=b:151702387

Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-13 20:24:59 +00:00
Rajat Jain 3639f38171 include/input-event-codes.h: Add Linux input key codes header file
Add header file from keycodes from Linux sources. This is needed so
that coreboot can provide scancode to keycode mappings in the ACPI
that the linux kernel expects (https://lkml.org/lkml/2020/3/24/588)

Signed-off-by: Rajat Jain <rajatja@google.com>
Change-Id: I40051cb63a6c154728887ac9b0521bc671b2a518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40029
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13 19:54:30 +00:00
Rajat Jain 999001144f util/lint: Accept "GPL-2.0-only WITH Linux-syscall-note" licenses
The Linux kernel UAPI header files are licensed under
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */

Allows files with this license to be included in coreboot.
For more details about this particular license:

https://www.kernel.org/doc/html/v4.17/process/license-rules.html
https://spdx.org/licenses/Linux-syscall-note.html

Change-Id: I4f0f8d36c637a66a6999a18321fdbc4c42d5751e
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13 19:54:19 +00:00
Srinidhi N Kaushik 3907a64a48 mb/google/volteer: enable Early Command Training
Update memory configuration on Tiger Lake platform to enable Early
Command Training. This feature was not supported before FSP v2527.

BUG=b:150357377
BRANCH=None
TEST= Build and boot volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40023
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13 15:51:01 +00:00
Aaron Durbin 4ed96f2443 ec/google/chromeec: add smbios_mainboard_manufacturer()
When EC_GOOGLE_CHROMEEC_SKUID is selected provide an
implementation of smbios_mainboard_manufacturer() so the code
doesn't need to be duplicated in the mainboards.

BUG=b:153767369

Change-Id: Ib65fe373a79d606cffcba71882b0db61be5a18c3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13 15:03:48 +00:00
Marshall Dawson d2d93829bb cpu/x86/smm.h: Add SW SMI for PSP SMM Info
Add a definition for a software SMI to allow AMD systems supporting
the MboxBiosCmdSmmInfo command to properly initialize the PSP.

BUG=b:153677737

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I1d78aabb75cb76178a3606777d6a11f1e8806d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40294
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13 12:39:25 +00:00
Marshall Dawson d6b7236732 soc/amd/common/psp: Split mailbox support into v1 and v2
Family 17h redefines the PSP command and status, and therefore the
steps required to send commands via the mailbox.  Convert the existing
version into a v1 and add a v2.  New Kconfig options allow the soc to
choose v1 vs. v2.

The v2 PSP begins responding to the mailbox command when the full
bit range is written.  Define the new mailbox as a union of a u32
and a structure.

Additional PSP details may be found in the NDA publication (#55758)
  AMD Platform Security Processor BIOS Architecture Design Guide for
  AMD Family 17h Processors

Change the existing two soc functions that return pointers to void
pointers.

BUG=b:153677737

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4d358fdae07da471640856f57568059e9487f6a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13 12:39:12 +00:00
Felix Held a67c753d55 soc/amd/picasso/soc_util: add TODO to Dali detection
Change-Id: I8ff5a9275d4cdf0049b63cc30b8a1cc376b50f80
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13 12:38:30 +00:00
Ronak Kanabar da968d5f2e mb/intel/jasperlake_rvp: Enable S0ix for JSLRVP
Enable S0ix from devicetree for JSLRVP

TEST= Build, boot JSLRVP and Verified S0ix is
working by running "echo freeze > /sys/power/state"
from kernel console.

Change-Id: Iedbd7ce9db546f8dc6cb3343fa624abde0ef0d3f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-04-13 06:45:10 +00:00
Maulik V Vaghela d7564dc1b9 mb/intel/jasperlake_rvp: Enable audio
Enable audio for Jasper Lake RVP board. It has 2 Audio codec chips
connected on I2C0: DA7219 and MAX98373

1. Enable Kconfig to enable I2C drivers for both chips.
2. Make necessary devicetree changes to enable FSP UPDs and ACPI entry
   for I2C0.
3. Enable audio related GPIO configurations.

BUG=None
BRANCH=None
TEST=Checked that dmic and speaker are functional on Jasper Lake RVP

Change-Id: Ibf76eb36c478bd33cbc0c86099236452b397fcc5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39695
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13 06:44:51 +00:00
Aamir Bohra 9225fd5040 soc/intel/tigerlake: Remove scs.asl
Remove EMMC and SD card ACPI devices copied from Ice Lake.
Tiger Lake does not support these controllers.

BUG=b:151208782
TEST= Build volteer board

Change-Id: I4b3e37f93b94757d16d775fb27bee644d9dc539e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40228
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13 05:44:44 +00:00
Srinidhi N Kaushik 9a90a439a2 soc/intel/tigerlake: Disable MrcSafeConfig
This change disables MrcSafeConfig option during MRC training.
MrcSafeConfig was enabled as part of the early testing.
Now with FSP 2527, there is no need to set this config anymore.

BUG=b:150357377
BRANCH=master
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11 21:31:54 +00:00
Srinidhi N Kaushik 083379d0f8 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527
Update FSP headers for Tiger Lake platform generated based FSP
version 2527. Which includes below additional UPDs:

FSPM:
 - PchTraceHubMode
 - CpuTraceHubMode
 - CpuPcieRpEnableMask
FSPS:
 - D3HotEnable
 - D3ColdEnable
 - RtcMemoryLock
 - PchLockDownGlobalSmi
 - PchLockDownBiosInterface
 - PchUnlockGpioPads
 - CpuMpPpi
 - ThcPort0Assignment
 - ThcPort1Assignment

BUG=b:150357377
BRANCH=none
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11 20:28:26 +00:00
Aaron Durbin 32107dffb7 ec/google/chromeec: expose failure and unprovisioned SKU id values
Provide CROS_SKU_UNKNOWN and CROS_SKU_UNPROVISIONED defintion so
callers can utilize the default and failing value without open coding it.

BUG=b:153642124

Change-Id: I447004e9016b6ab3306ea532721494ebbcda741d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40299
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11 14:26:47 +00:00
Scott Chao 2a203c50ef mb/google/kukui: correct board name
Modify board name from "Kadadu" to "Kakadu"

BUG=b:153590144
TEST=CPU log show "Starting depthcharge on Kakadu..."
BRANCH=kukui

Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Change-Id: Ibf387b0e0153315ff2ab5c19381db44a61c14e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40283
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11 09:32:42 +00:00
Elyes HAOUAS 3dff32c804 nb/i945: Improve code formatting
Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-11 09:19:13 +00:00
Elyes HAOUAS fd8de1860d src/mb: Remove unneeded spaces before/after tabs
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 22:30:06 +00:00
Jake Mannens a0722870a8 mb/lenovo/t420s/devicetree.cb: Fix PCIe port definitions
The NEC uPD720200A USB 3.0 controller on the T420s is actually
connected to PCIe root port #5 on the PCH, not #7. Enable RP#5,
disable RP#7 and update comments accordingly.
Test=USB 3.0 controller shows in `lspci`

Change-Id: I21ac72fd5632e552bdcdbd573cf92b433ed545ff
Signed-off-by: Jake Mannens <jakem_5@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-10 22:28:00 +00:00
Aamir Bohra cf0d1c3164 soc/intel/jasperlake: Publish EMMC and SD card ACPI devices
BUG=b:150872580
TEST=Build waddledoo board. Verify EMMC and SD card ACPI devices are
     present in dsdt.asl.

Change-Id: I70d47455c48990afe9e79c013c5272d70f4f71e7
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-10 19:33:23 +00:00
Karthikeyan Ramasubramanian d38108f26f mb/google/dedede: Add Synaptics Touchpad configuration for waddledee
TEST=Build and boot the mainboard. Ensure that the touchpad is
operational.

Change-Id: I937462cd3992a884194bbd1759a0802a147e925a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-10 19:32:59 +00:00
Aamir Bohra 30ab312322 soc/intel/jasperlake: Publish single GPIO ACPI device
Current pin-ctrl kernel v5.4 driver expects the firmware to publish
single GPIO ACPI device. Until kernel pin-ctrl driver implementation is
updated to consume community based GPIO ACPI device, update the current
ACPI code to comply with pin-ctrl driver requirement.

BUG=b:150154277
TEST=Verify intel pin-ctrl driver can successfully load in OS

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: Ifcc92adaee550182ab405541ea85019f31bb8658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-10 19:31:48 +00:00
Karthikeyan Ramasubramanian e9eb4d5df9 mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio
According to the EDS, EC_AP_PWR_BTN_ODL has a default internal pull-up
of 20K. Retain it during the GPIO pad configuration.

BUG=b:150985246
TEST=Boot the mainboard.

Change-Id: I042ba70f78fca1a5b9eda30029df97b3f8e65656
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39852
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 19:31:18 +00:00
Morgan Jang ea9787a6b2 drivers/ipmi: Implement the function for logging system events into BMC
Implemented for functions that need to log system events into BMC,
the information of system events can be specific.

TEST=Use ipmitool and execute "ipmitool sel list" command to check
     if SEL is added into BMC.

Change-Id: I38f3acb958d12c196d33d34fd5cfa0b784f403b7
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-10 18:08:02 +00:00
Scott Chao e6d1c7fae8 spi: add Winbond W25Q64JW spi rom support
BUG=b:153515968
TEST=Able to boot to kernel

Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Change-Id: I699f6d7ba3af01436f10c9a59af4a22fc45aa300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40270
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 15:14:53 +00:00
Elyes HAOUAS 4d319c3d09 src/ec: Add missing "set_resources = noop_set_resources"
Change-Id: I4acfb9d9911e251a494b6d35d76226c06e7858d6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10 12:00:11 +00:00
Elyes HAOUAS 7eed98ac88 util/nvramtool: Remove 2nd initialization
'result' is already defined as 'unsigned long long result = 0;' so no
need to re-write 'result = 0;'.

Change-Id: Ie897453fb5e7b09af755ce8d61ee8e80943ffc1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-10 11:56:13 +00:00
Nico Huber 2f8ba69b0e Replace DEVICE_NOOP with noop_(set|read)_resources
`.read_resources` and `.set_resources` are the only two device
operations that are considered mandatory. Other function pointers
can be left NULL. Having dedicated no-op implementations for the
two mandatory fields should stop the leaking of no-op pointers to
other fields.

Change-Id: I6469a7568dc24317c95e238749d878e798b0a362
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 11:50:22 +00:00
Nico Huber a461b694a6 Drop unnecessary DEVICE_NOOP entries
Providing an explicit no-op function pointer is only necessary for
`.read_resources` and `.set_resources`. All other device-operation
pointers are optional and can be NULL.

Change-Id: I3d139f7be86180558cabec04b8566873062e33be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 11:25:04 +00:00
Varun Joshi 9734325f45 soc/intel/tigerlake: Add support to initialize DDR4 Memory
Support to configure DDR4 memory variant.
	-Add support to read SPD data based on different memory topology.
	-Initialize FSP UPD's for DQ and DQS mapping.

BUG=b:151702387

Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39847
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 01:57:27 +00:00
Elyes HAOUAS c2e796290a mb/*/*/hda_verb.c: Improve code formatting
Change-Id: I294ea867678ad77e454873ecf4948bf2d12c9f80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10 00:13:12 +00:00
Nico Huber db2c8dfecb assert.h: Simplify dead_code()
It turns out the linker's error message already includes the line
number of the dead_code() invocation. If we don't include the line
number in the identifier for our undefined reference, we don't need
individual identifiers at all and can work with a single, global
declaration.

Change-Id: Ib63868ce3114c3f839867a3bfb1b03bdb6facf16
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10 00:10:58 +00:00
Elyes HAOUAS 17419ff948 mb/intel/icelake_rvp/variants/icl_u: Improve code formatting
Change-Id: I2a87e5c0f598d665f1c64ac8cfe235918326d1d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09 23:49:47 +00:00
Elyes HAOUAS 3408a0ef0c mb/intel/d945gclf: Improve code formatting of devicetree
Change-Id: I3c8d430a10562edd4404d322e78f603cae191026
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09 23:49:12 +00:00
Evgeny Zinoviev 408fdeba7f Doc/mb/lenovo/ivb_internal_flashing: Fix a typo
unmount -> umount. My mistake.

Change-Id: I5d1b675f6ab7c027f2e646424adb1f255967c753
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09 23:44:21 +00:00
Christian Walter b2f8ce7591 soc/intel/cannonlake: Steal no memory for disabled IGD
Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct'
to do it like this, otherwise the FSP would always allocate memory for
the IGD even if it is disabled. In addition the FSP enables the graphics
panel power even if no IGD is present which leads to a crashing FSP.
Thus, if no IGD is present we switch off the panel via UPDs.

Refer to this issue on IntelFSP for details:
https://github.com/IntelFsp/FSP/issues/49

Tested on:
* CFL platform with IGD
* CFL platform without IGD

Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-09 21:49:01 +00:00