The driver structures live in special sections which have no
direct reference to the symbols. Therefore, when garbage
collecting sections in the linker the drivers are tossed out
resulting in no drivers being linked into ramstage. Fix this
by adding the KEEP() directive to those special sections.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and noted console starts working in ramstage.
Original-Change-Id: Iaa0fd428bf975c82d4e6b0e75a17e6fd231fbaa9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207261
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7c1a3e63e398755de0c77524a0483e6f1019aac0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1e30e73be754ec849cb3cfac3bcb12e95b0f60d4
Reviewed-on: http://review.coreboot.org/8584
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
1) In order to avoid stack from overflowing during ramstage decompression,
initialize stack right at the beginning of romstage.
2) Declare different Kconfig options for stack at each stage.
3) Provide a macro that does stack seeding if required and calls appropriate
function.
BUG=None
BRANCH=None
TEST=Compiles and runs successfully on rush.
Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206880
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd
Reviewed-on: http://review.coreboot.org/8583
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Still waiting on VDD_CPU value, etc. from board guys, but this is a start.
BUG=None
BRANCH=None
TEST=Built and flashed rush, saw 'PMIC init done' string OK.
Original-Change-Id: I6f8b16c4ebf1e9c159f8175d59262119ef0e498f
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206412
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 96a9ff8f632c2b9bf3f81f5b8fc4f3b6784a02bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9d3d7ff55f2d6ca88ebdcc8ad1d7de135f5136d2
Reviewed-on: http://review.coreboot.org/8582
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Once the MTS microcode is loaded the core complex can be
directed to decode the MTS and start running. The cores,
however, won't start executing until instructed to do so.
BUG=chrome-os-partner:29222
BRANCH=None
TEST=Built, booted, ran. Noted it took about 920ms for the
core complex to decode and handshake back.
Original-Change-Id: I0a9ed53e596eb65801461b2769d133710a92a48a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206075
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 6edb6e21a69d84ba5b23137e9e390954159e7887)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I179e561bb3a34b206620eecde6781a1c05a3744e
Reviewed-on: http://review.coreboot.org/8581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The armv8 cores need to have microcode loaded before they can
be taken out of reset. Locate and load the MTS microcode at the
fixed address of 0x82000000. The ccplex, once enabled, will
decode and transfer the microcode to the carveout region.
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and ran. Confirmed dump of MTS region after loading code.
Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206290
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df
Reviewed-on: http://review.coreboot.org/8580
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As a convenience, print the actual stage name when entering a stage.
Also unify the banner between bootblock / romstage and ramstage. No
reason for two different occurences.
Instead of this:
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting...
you will see this:
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting...
Roughly based on: https://chromium-review.googlesource.com/199671
Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8578
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The recommended settings for the size of the MTS region is 128MiB.
Therefore, provide this region 128MiB below the top of DRAM for
each configuration.
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and noted MTS carveout region at expected location.
Original-Change-Id: Iac17f210dfef8e8a36617c7b3dceba8c2134ee9b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206291
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit f1758c74330afe9dd7eaa8ff1fef5e4d18ed14ad)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I369a3897e31f3126d031d3582f52f9892350f658
Reviewed-on: http://review.coreboot.org/8579
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Use the Kconfig value to load the name of the stage instead of the
hard-coded fallback stage.
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1ac707efe38e29f109dbbe206de74fbfe7cb7b0b
Reviewed-on: http://review.coreboot.org/8576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
There's no reason to duplicate code in the mainboards. Therefore,
drive the flow of romstage boot in the SoC. This allows for
easier scaling with multiple devices.
BUG=None
BRANCH=None
TEST=Built and booted to same place as before.
Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205992
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19
Reviewed-on: http://review.coreboot.org/8575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Add support for initializing dram within romstage. This is an essential before we
move to the armv8 core.
BUG=None
BRANCH=None
TEST=Compiles succesfully for rush. Tried writing to and reading value from the
base of sdram and it worked fine. Also tested with primitive_memtest CL:
https://chromium-review.googlesource.com/#/c/186309/5
Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205823
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4baface2c109ca74f85f43a25508677c46c64159
Reviewed-on: http://review.coreboot.org/8574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Add basic romstage support for rush. Since, dram init needs to be done before we
can jump to armv8 core, romstage will run on armv4 core as well. Thus,
correcting the compiler selection options.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Prints romstage banner and initial printk
Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205763
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a
Reviewed-on: http://review.coreboot.org/8573
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We suspect that the code was stuck on init pllx (PLLX - acts as a clock source
for the CPU cluster). So, remove the init call for pllx. This needs to be added
later when required. Also, add a few more printks to display the progress.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Print messages seen on serial console.
Original-Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205680
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit d557d99edb855fbf7b32231c6746c676041bf62a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iaf56f2d587708c6e9fb01d4ced2edb5931075a81
Reviewed-on: http://review.coreboot.org/8571
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Pull in mainboard specific bootblock_init function from nyan into
rush. Additionally, pull in all files required for proper compilation of rush
after adding the bootblock_init function
BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205583
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795
Reviewed-on: http://review.coreboot.org/8570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Moved mctGetLogicalCPUID() to a separate file and made it available in
both romstage and ramstage.
Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
BUG=None
BRANCH=None
TEST=Compiles successfully
Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203143
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3)
This cherry-pick was modified to match the tegra124 uart.c, which
uses the idx and base address calculations instead of Kconfig settings.
This driver could use the 8250MEM driver when the ARM vs x86 IO
calling convention is worked out.
Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8517
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This is just dead code.
Should we decide that we want some of these calls made, they would
be implemented in the mainboard context.
Change-Id: I1f097c8da722f3afab9aa1c80b96590c7ca457d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8532
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now that we use the microcode updates in the blobs repository, remove
them from the main repo. Since the microcode updates are blobs, it
makes more sense to ship them in the blobs repo rather than the main
one.
The update-microcodes.sh script is also deleted, as a more current
version resides in 3rdparty.
Change-Id: Iee74a3ede3b5eb684ef0386d270120e70173c1b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4531
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now that microcode has been added to blobs, use that one instead of
the one included in the tree. Microcode from the tree will be
removed in a subsequent patch. Since the microcode updates are blobs,
they belong in the blobs repository.
This change may introduce a build failure if the "Generate from tree"
microcode option is selected, but the blobs repository is not
enabled. We have to live with this for now, until microcode is moved
to blobs for all CPUs, at which point we may adjust Kconfig
accordingly.
Leave the FSP cpu alone for now, as that will need approval from
SAGE.
Change-Id: Ia77ba2e26c083da092449b04ab2323b91a2ca15b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4530
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
During the development of commit bde6d30 (x86: Change MMIO addr
in readN(addr)/writeN(addr, val) to pointer), there were several iterations
and patterns tried. An intermediate pattern was the use of u32 pointers,
and division by sizeof(u32). Some of these did not get properly
changed to pointer types of length 1, causing a regression in
the Intel Ibex Peak SATA driver, fixed in commit 9b5f137
(Intel ibexpeak: Fix SATA configuration).
Other regressions of this pattern are fixed here. I audited all changes
to u32 types, and the other ones are safe.
Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Reviewed-on: http://review.coreboot.org/8530
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The Winbond W83793 fan controller is not automatically
configured correctly on power application, leading to
abnormal, and in some cases random, fan behaviour.
This commit enables the controller and sets sane default
values.
TEST: Booted mainboard and verified that the correct number
of fan speed sensors were visible from hwmon under Linux.
Also verified that, unlike before, the CPU fans were running
at a high enough speed to properly cool the CPUs. Verified
the 8 fan outputs under direct control of the W83793 device.
Verified voltage and temperature sensors and limits via output
of the 'sensors' command.
Change-Id: Ie3753bd3111d9d9eb46826da410c132caec4d9fe
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8503
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The version field for t132 cpus is 0x00130001. Update it to
the correct version.
BUG=chrome-os-partner:29882
BRANCH=None
TEST=Built and was able to see serial with subsequent changes.
Original-Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205435
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 14916b3ba5545ab2cb35b6a4a7fa231b895ede46)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I785069d3eb82ed24bafd52ef627d53505a35c09a
Reviewed-on: http://review.coreboot.org/8467
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
CONFIG_CONSOLE_SERIAL_UART has been updated to
CONFIG_DRIVER_UART. The UART may be used for more than serial console.
Change-Id: Ife6e6861d210126b2b9ba5eee9ff72e8a447c47f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8516
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The early_console.c file isn't used or built. It has been replaced
by the generic uart and console drivers.
Change-Id: I505b4e48d2369dbbfd92ef1dab364c5f2ed924df
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix up commit ce7ecf9c (baytrail: enable monotonic timer), which
selected `HAVE_MONOTONIC_TIMER` explicitly, although it is already
selected by `TSC_MONOTONIC_TIMER` (cf. `src/cpu/x86/Kconfig`).
Therefore remove the explicit selection of that Kconfig option.
Change-Id: I8964771947a6f7457dcdefe7a17be623ae0ef900
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
No real harm done (thanks to our free() implementation),
but let's do it right.
Change-Id: Ib98d28aabc043dff5c288728c33490a79f09f35a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8511
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add a new driver for Intel i210 MACPHY with the goal to
update the MAC address in i210 if it is found
during PCI scan.
Change-Id: I4d4e797543a9f278fb649596f63ae8e1f285b3c3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8404
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
DEFAULT_CONSOLE_LOGLEVEL_* is supposed to be selected by the user, and
should not be overriden by any other part of the tree. As such, remove
the selection of DEFAULT_CONSOLE_LOGLEVEL_7 from these two boards.
Change-Id: I194a71b371b184e81a16fec2bd21f1b0deb4ebbf
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8486
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
This option is already defined in console/Kconfig, and is intended
to be controlled by the user. Only six boards in the entire tree
redefined it, so remove the definition from those boards.
Change-Id: I3a65444f63c93c01d78569a9a7eb01158fb290bd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8457
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
SUPPORT_CPU_UCODE_IN_CBFS is a deprecated option now that all CPUs
with updateable microcode (except AGESA) load microcode from CBFS.
CPU_MICROCODE_ADDED_DURING_BUILD is a state variable that is set
based on user's choice in the microcode menu and should not be changed
directly.
Eliminate INCLUDE_MICROCODE_IN_BUILD variable, whose use directly
interferes with the microcode mechanism, remove selection of
CPU_MICROCODE_ADDED_DURING_BUILD, and do not depend
SUPPORT_CPU_UCODE_IN_CBFS on anything. This makes usage of the
microcode mechanism consistent with other CPUs in the tree.
This incorrect usage of the Kconfig variables was hiding the fact that
some of the microcode files present in fsp_baytrail/microcode_blob.c
were not present in the tree.
Change-Id: I71cb3f834c22c0363a20bd469797a9f51c215371
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done
to only advertise x1 lane width for PCIe link 0:15.0.
Hide functions of PCIe links that have no slots connected. Our PCI
infrastructure does not support bridge devices that are set off
in devicetree but remain visible in the PCI hardware tree.
Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8388
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Remove functions 0:12.1 and 0:13.1 that do not exist in the hardware.
Disable 0:14.1 IDE controller, as it would only be used with SATA ports
4 and 5 that are not populated with connectors in the hardware.
Disable 0:14.2 HD audio, as it is not implemented in the hardware
Disable 0:14.5 OHCI controller, as ports behind this USB1.1 -only controller
are not populated in the hardware.
Fix some alignment and whitespace.
To my knowledge these changes are not included with SAGE release
pcengines.apu_139_osp.tar.gz, but that tarball does not contain
either devicetree.cb or a pre-compiled static.c file so I cannot tell
for sure.
Change-Id: Idcb8e76645fce7e89a37ff7007531b668f472131
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8328
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Interrupts from USB controllers 0:16.0 and 0:16.2 were not routed
in PIC mode. The only affected peripheral was the SD card reader.
This patch is not included with SAGE release pcengines.apu_139_osp.tar.gz.
Change-Id: Ie7f0fa3751b46cca0132bd6dcada3628c6a45efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8327
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, we cannot mark 0:14.4
disabled in devicetree just yet.
Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8326
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
While we cannot recreate exact copies of PC Engines APU1 firmware images,
I shall upstream the vital changes for coreboot from the following tarballs
SAGE has published to meet GPL:
SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz
md5sum: ce5f54723e4fe3b63a1a3e35586728d4
pcengines.apu_139_osp.tar.gz
md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef
The patch here adds Kconfig, Makefile.inc and devicetree.cb files to
match 2014/04/05 release tarball config.h and static.c files.
Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8325
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Some GPIO pins are shared with PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, simply setting 0:14.4
disabled in the devicetree does not work here yet.
Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8495
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
The goto statement skipped all the code that is necessary
to fill in the data structures that are read right after
the jump.
Since there doesn't seem to be useful data, why write these
ACPI objects in the first place?
Change-Id: I1d06c11a7a31517b81e54159355d5c27e3cc3735
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
