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Author SHA1 Message Date
Subrata Banik
3e55044645 soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode 
Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.

TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.

Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-16 23:30:12 +00:00
Subrata Banik
588c2c42c3 soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition 
LPC pci config register BIOS Control (BC) - offset 0xDC bit 1
is for Lock Down.

Change-Id: I4780d2e41c833c0146640f715759dbb0a948c4ab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-15 23:12:22 +00:00
Lijian Zhao
2f764f7dfe soc/intel/cannonlake: Call into FSP siliconinit 
The following changes can make system call into FSP siliconinit and exit
from that until payloads.

1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.

This patch was merged too early, and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20581

Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20687
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-15 20:21:31 +00:00
Lijian Zhao
8465a81e81 soc/intel/cannonlake: Add postcar stage support 
Initialize postcar frame once finish FSP memoryinit

This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534

Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-15 20:21:22 +00:00
Aaron Durbin
a045fb9de8 soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macro 
The PCH_P2SB_EPMASK macro takes a parameter. Ensure parenthesis
are put around the parameter expansion.

Change-Id: I978e9397036ea3630434982fe4ecd698877fe0d6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2017-08-15 19:01:13 +00:00
Subrata Banik
6037b200d1 soc/intel/cannonlake: Remove unused systemagent registers 
This patch to make code cleaner and remove unused systemagent
register macros. [same as KBL implementation]

Change-Id: I13b9c83097fc98183ea138c9087b5fc7834efd58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-14 17:58:54 +00:00
Subrata Banik
4277667499 soc/intel/cannonlake: Initialize struct member to 0 
As per GCC 7.1 compiler struct reset_reply is considered
as uninitialized inside send_heci_reset_message function.

Change-Id: I01b95d31bfb1d2e9af1704a28dacb9cfd1cdcb50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-14 17:58:50 +00:00
Brandon Breitenstein
ae1548621a soc/cannonlake: Enable SMM code for Cannon Lake 
The minimum needed defines are included here and pm.h
will be updated when the PMC code for cannonlake is uploaded.

Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-11 16:04:42 +00:00
Furquan Shaikh
b58366a4c0 soc/intel/cannonlake: Add missing _PCH_DEV definitions 
Add all missing _PCH_DEV definitions to pci_devs.h

Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-11 15:54:26 +00:00
Lijian Zhao
aa3d78d5e6 soc/intel/cannonlake: Add ramstage SystemAgent support 
Revere memory resource within SA, also perform necessary routine for
initialization during ramstage.

Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20914
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-09 20:06:27 +00:00
Lijian Zhao
e88fa490a5 soc/intel/cannonlake: Add memory map support 
Calculate the top of ram from output of Fsp reserved memory range.

Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-07 17:53:13 +00:00
Lijian Zhao
dcf99b0445 soc/intel/cannonlake: Sort Kconfig for Cannonlake 
Look and feel update, sort the sequence in Kconfig.

Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-03 18:54:11 +00:00
Lijian Zhao
03e44f46b0 soc/intel/cannonlake: Correct gpio definition 
The following changes have been applied for GPIO:
1. Correct port id using by GPIO community 3 for CNL-LP.
2. Correct number of doubleword for each pad from 2 to 4.

Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2017-07-27 15:50:36 +00:00
Martin Roth
b4560cd523 Update files with no newline at the end 
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2017-07-24 15:08:16 +00:00
Martin Roth
467a87abce Fix files with multiple newlines at the end. 
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2017-07-24 15:08:08 +00:00
Martin Roth
3f6421e1fa soc/intel/cannonlake: Keep variable from going out of scope 
The variable p was going out of scope while still being pointed to by
*cpu_name.

Fix coverity ID 1378215 (Pointer to local outside scope)

Change-Id: I6ad7b1919104b4d97869efe5065e39c2a43de638
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
 2017-07-22 22:49:46 +00:00
Martin Roth
80358a1f47 Revert "soc/intel/cannonlake: Add postcar stage support" 
This reverts commit 399c022a8c.

This was merged too early.  I'll repost it.

Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-07-21 17:39:10 +00:00
Martin Roth
70de396958 Revert "soc/intel/cannonlake: Call into FSP siliconinit" 
This reverts commit dbe7f893c0.

This was merged too early.  I'll repost it.

Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-07-21 17:32:07 +00:00
Lijian Zhao
dbe7f893c0 soc/intel/cannonlake: Call into FSP siliconinit 
The following changes can make system call into FSP siliconinit and exit
from that until payloads.

1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.

Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-21 15:56:16 +00:00
Lijian Zhao
399c022a8c soc/intel/cannonlake: Add postcar stage support 
Initialize postcar frame once finish FSP memoryinit

Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-21 15:55:40 +00:00
Lijian Zhao
a77c68adf3 soc/intel/cannonlake: Make ramstage relocatable 
Relocate ramstage into CBMEM.

Change-Id: I0543d25d722c5872f4f139a98e5125a41cc40653
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-20 21:57:10 +00:00
Lijian Zhao
0ade3133a0 soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit 
The following minimal changes are needed to make system boot until FSP
memoryinit got called.
1. Program SA BARs
2. Assume previous power state is S0.

Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-19 23:06:07 +00:00
Lijian Zhao
acfc149f7b soc/intel/cannonlake: Add microcode support 
Microcode needs to be loaded prior to FSP initialization.

Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20484
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-07-19 16:16:44 +00:00
Lijian Zhao
6dc125f0e3 soc/intel/cannonlake: Fix Build break 
1.Replace outdated defination of TCO_EN to TCO_BASE_EN
2.Remove setmaxfreq() as not needed any more.

Change-Id: Id54fdfd14f1abaa592132195e6f9acfa5807626e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-18 19:17:04 +00:00
Andrey Petrov
c854b49db9 soc/intel/cannonlake: Use common GPIO driver 
Change-Id: I0bbdd641244f0c7baaa2146dcfde6431bde387c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-18 19:16:56 +00:00
Andrey Petrov
60a7e78de2 soc/intel/cannonlake: Add PMC headers 
Add register definitions used in PMC block.

Change-Id: I963f402a59d49dfc7b76224f719a315e1cc6dc74
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20071
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-07-18 15:53:07 +00:00
Aaron Durbin
3c874e9d04 soc/intel/cannonlake: remove top_of_32bit_ram() declaration 
It should never be globally exposed. Remove it.

Change-Id: I90e201ddd4df2cda89e7d3e4cb81bdc2a81cac83
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2017-07-17 14:59:51 +00:00
Andrey Petrov
fed4303b45 soc/intel/cannonlake: Add reset.c 
Add reset functionality. This implementation relies on CSE to trigger
global reset.

Change-Id: I7e6ae07a48f1cdc3d2f4cdb74246627d27253adf
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-13 21:04:47 +00:00
Andrey Petrov
9f244a5494 soc/intel/cannonlake: Add Makefile 
This enables building working bootblock and non-functional romstage
and ramstage.

Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-13 19:28:53 +00:00
Andrey Petrov
f35804ba6f soc/intel/cannonlake: Add bootblock PCH 
Add essential initialization needed for PCH in bootblock.

Change-Id: I3694e099e78c2989f7192c550cbba098e5df2032
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-13 19:28:34 +00:00
Andrey Petrov
3e2e0508c2 soc/intel/cannonlake: Add early CPU initialization 
Add basic CPU initialization for bootblock, as well as relevant headers.

Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-13 19:28:27 +00:00
Andrey Petrov
099f43a317 soc/intel/cannonlake: Add PCI dev macros and IDs 
Change-Id: I287404f1615c6c0b441dd1b98a40e79919920a02
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-12 23:22:27 +00:00
Andrey Petrov
a00e10474a soc/intel/cannonlake: Add report_platform.c 
Dump basic platform information early in bootblock.

Change-Id: I12d1c9dd9f0518c133de465a4db72a0664a94eef
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20068
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-07-12 23:20:52 +00:00
Andrey Petrov
ab85e2b816 soc/intel/cannonlake: Add bootblock.c 
Change-Id: Ia951a466479b1e98e49895705162a66aece7609b
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-02 18:51:29 +00:00
Andrey Petrov
d39c68a0c0 soc/intel/cannonlake: Add UART initialization 
Cannonlake has built-in UART driver as part of LPSS block. However port
mapped decoders are in use as well.

Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-06-29 14:59:32 +00:00
Lijian Zhao
81096041b8 soc/intel/cannonlake: Add initial dummy directory 
Add Cannon Lake SoC boilerplate directory with:

 * SoC directory
 * Base Kconfig
 * Dummy cbmem.c

Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-06-29 14:50:38 +00:00