Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing
so on each and every mainboard.
Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DEVICETREE` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.
Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a valid GPIO configuration based on the mainboard wiring.
Change-Id: I36f0e8292a405b4bac74fbc5fde62e5e414387e7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56519
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there is no SD card interface on this mainboard do not set the
card detect GPIO.
Change-Id: Ibe6799c5c540538f97d1726ec16e79f3edbb16fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56489
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE instead of
PCI_ALLOW_BUS_MASTER to enable PCIe bus master bit as requested in
CB:56441 during review.
Change-Id: I433dbae0d9b15e41d1d0750298868341ce3d6b46
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Since this mainboard does not use GSPI at all, disable all GSPI ports.
Change-Id: I60254e9f4047537d86c972151ec9e33552332959
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This mainboard uses I2C1 and I2C4 buses only. Disable all the others as
they are not connected at all.
Change-Id: I4743f6ea6b9a9987ad63b60f56ee9a597a08284b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Features like DevSLP and Aggressive Link Power Management are not
supported on this mainboard and are therefore disabled.
Change-Id: I3bc650ea78be8587889fb7abfe7075cd9a122198
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This board does not use CLKREQ-signaling for PCIe, so disable the pin
assignments. In addition only three clock outputs are used for PCIe,
therefore disable all others to improve EMI.
Change-Id: I545f890fa55a109df7f44d2c82170874fb769009
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56455
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are in total three USB ports that are used on mc_ehl1:
- Port 1: Type A connector connected to USB2/USB3 port 0
- Port 2: Type A connector connected to USB2/USB3 port 1
- Onboard: connected to USB2 port 2
None of the ports supports overcurrent reporting.
Adjust the appropriate UPDs in devicetree to match the hardware
configuration.
Change-Id: I220637b8e9f03efccacd0955e82cfc0c7a6f53ee
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56454
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since mc_ehl1 does not have a display attached nor have a display
connector available (pure headless design), remove display related
settings from the devicetree.
Change-Id: Id31c09fcfba15f55eed19134bd0c2fb887bd2478
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56453
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Take Kconfig switch PCI_ALLOW_BUS_MASTER into account and set the PCI
bus master bit for legacy devices only if it is allowed.
Change-Id: I7798a767d528419bb093f301140ab68cc8b9c5ae
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Since the variants can have different memory move the SPD related
content to the variant directory.
Change-Id: I38aa5e7514437bfcc61c38d64f0ba6f19350810d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56036
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SaGv is only available on ULT/ULX processors, which use PCH-LP. Given
that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it
does not use ULT/ULX processors, and thus does not support SaGv. Drop
the `SaGv` setting from the devicetrees, as it has no effect.
Change-Id: I5be518cce08206ad149efd1665e44a7111b24202
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown.
Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56198
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a 16 MB flash chip on mc_ehl. Set the ROM size accordingly and
provide a flashmap for partitioning. Select the used flashmap on variant
level to allow different layouts for different variants.
Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Remove Kconfig switches that are not needed for mc_ehl based mainboards.
Change-Id: If231f37f06c6763d52a821799e87fdb3010af0aa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
There will be more variants of this mainboard so prepare the scheme for
Kconfig to handle the variants properly.
Change-Id: If1cf418836d77a45955ee55d30ba670db8ff2533
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add a new mainboard called mc_ehl which is based on Intel's
'elkhartlake_crb'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Follow-up commits will
introduce the needed changes for the new mainboard.
Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
New kconfig parsers interpret $(var) themselves, leading to empty
fields. Old kconfig understands \$(var), so use that.
Change-Id: I927fc9dc7a66211bfe51d4324cf7c51b555ea3a8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55912
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only I2C controller 3 is used on this mainboard. Disable all other
controllers.
Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The I2C bus at which the external RTC is attached to is operated at
standard speed (100 kHz) at coreboot runtime. The OS can choose to run it
at fast speed since it uses its own driver and controller setup.
Report additional bus timings for fast mode so that OS can do it right.
Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55089
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Already released Linux versions did not have the needed ACPI-extension
in the RTC driver. If the ACPI-Support is enabled for the RTC, this
older Linux will not be able to use this device as it will be claimed by
the PNP-drivers. As there is no way to avoid that an older Linux kernel
meets a newer coreboot in the field, we need to disable the ACPI
support for the RTC for the mc_apl-based mainboards.
Change-Id: I9f9939ba3234dc3654a4ef8a498649453941ebdf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55004
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variant mc_apl1 is the only one that uses gpio.c from baseboard. For
this reason, gpio.c is moved from baseboard to mc_apl1.
Change-Id: Ie2ba8181dfe887df9abbbd648f2cbdc6ffc65530
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
With commit 405f229689 (soc/intel/*: drop UART pad configuration from
common code) the UART pad configuration was dropped from common SoC
code. Through a second commit 5ff17ed393 (mb/siemens/mc_apl1: do UART
pad configuration at board-level) the UART pad configuration was made
for mc_apl1 baseboard. This change is also needed for all other mc_apl
boards.
Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
All the boards in the patch have a constraint for the I2C bus to operate
on 100 kHz. Provide dedicated values for rise time, fall time and data
hold time on mainboard level to get a proper timing which takes the bus
load into account. Giving these values the driver computes the needed
timings correctly.
TEST=Measure I2C frequency on all boards while coreboot accesses
external RTC and make sure it is 100 kHz.
Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52721
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore,
default to 512 in the SoC Kconfig and drop it from related mainboard
Kconfigs.
Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With a new HW revision of this board, the connection of the external RTC
RX6110SA was changed from I2C bus 0 to I2C bus 3.
Change-Id: I10dd44949973ea490b3c7e4ad83d56ce2e566adf
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49442
Tested-by: siemens-bot
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to a bootblock gpio table for the board as a
first step. Common UART pad config code then gets dropped in CB:48829.
Change-Id: Iad40b6315a29e7aea612a3e1a169372d296d1d6c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49443
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Until now some FSP-S parameters were configured for Siemens APL
mainboards via the Binary Configuration Tool (BCT). For simplification,
the original APL FSP binary should now be used. For this purpose, the
corresponding FSP-S parameters are set via devicetree, respectively via
mainboard_silicon_init_params accordingly.
The following parameters are affected:
- Disable CPU power states (C-states)
- Set lowest Max Pkg Cstate - PkgC0C1
- Disable PCIe Hot Plug for all enabled RPs
- Disable PCIe Transmitter Half Swing for all RPs
- Disable PCIe Active State Power Management (ASPM) for all RPs
- Disable PCIe L1 Substates for all RPs
TEST:
- Compare old with new coreboot log on mc_apl5, found no differences
- Boot Linux v4.4 and check output of 'lspci'
Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Do LPC/eSPI pad configuration at board-level to match other platforms.
Early gpio configuration was done in romstage, while LPC pads were
configured in bootblock. Instead of adding another dedicated gpio table
for bootblock, move early gpio configuration completely to bootblock on
these boards. This won't hurt, since there is no code touching the pads
in between.
The soc code gets dropped in CB:49410.
Change-Id: I2a614afb305036b0581eac8ed6a723a3f80747b3
Tested-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built chili/base with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I5e2a09db80232457b2f78ad9b100c468d281f753
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The PCI devices P2SB and PMC are hidden by the FSP and cannot be
unhidden, because the FSP locks their configuration. Thus, setting them
to `on` is not correct. Therefore, set their state to hidden.
Change-Id: Ib7c019cd7f389b2e487829e5550cc236ee5645b7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48388
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: Ib4e7ec948ca4d019ad82ebc5abe39fc408281cf4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48299
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get rid of variant_gpio_table() and configure GPIOs in gpio.c instead
of passing data around.
Change-Id: Ib158d6bdbcbceb3c1dc4f47fc7c3e098b9c7e5c4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47974
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's one copy of this function for all variants except mc_apl4. Move
one copy into common mainboard.c and exit early if running on mc_apl4.
Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A MAC address that is neither 00:00:00:00:00:00 nor ff:ff:ff:ff:ff:ff is
considered valid. Instead of using a temporary buffer and memcmp(), use
a single loop that exits as soon as the MAC cannot possibly be invalid.
Change-Id: I2b15b510092860fbbefd150c9060da38aeb13311
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Define and use the MAC_ADDR_LEN macro in place of the `6` magic value.
Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47404
Tested-by: siemens-bot
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The option `HeciEnabled` was partly replaced by use of the device on/off
state in the devicetree in commit 3de90d1. The option has been removed
from the corresponding boards, so `HeciEnabled` is always 0 and ME
always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM`
is set.
Replace the option in the finalize function by the same dt state check
that sets the FSP option and drop the remaints of `HeciEnabled`.
Devicetrees still having `HeciEnabled` have been adapted to keep the
current behaviour.
Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The Chili base board is a ruggedized laptop with additional industrial
interfaces. So far, only booting and basic interfaces (USB, UART,
Video) are working with the original model, the "base" variant.
No further development is planned for this variant, as our primary
target was another one that will be added in a follow-up.
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let
Intel common cse block code can use this device.
Calling me_read_config32(offset) function from ramstage:
Without this CL :
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!
With this CL :
HECI: Global Reset(Type:1) Command
HECI: Global Reset success!
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Use the 96 character limit for pad macros.
Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
GPIO Driver mode is used for configuration interrupt routing for
external devices through GPI. But there is no point in configuring
this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro
with others that do not set the corresponding bit in the Host Software
Pad Ownership register.
Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The three Intel Apollo Lake boards (apl_rvp, leafhill and minnow3) do
not define MAX_CPUS, which would then default to 1. Since this is most
likely an oversight, use the same value as other Apollo Lake boards.
To ensure this does not happen again, factor out MAX_CPUS to SoC scope.
Change-Id: I5ed98a6b592c8010b59eca7ff773ae1ccc4cd7b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
APL does not support Hyper-Threading, and has at most four CPU cores.
Change-Id: Ib2ffadc0c31cdd96bec8eed5364c984acb2e1250
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45143
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common fast SPI driver has a function to set up the SPI OPCODE menu.
Use this function here instead of coding it again as it results in the
very same register values being written.
TEST=Compare register values in both cases and make sure they match.
Change-Id: I98457a0b0652f746734ee4204e10acd09b6e5fda
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43166
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I7b656f0244774cb174a90d97c5ae1c725802b636
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Currently, those who want to use measured boot implemented within
vboot should enable verified boot first, along with sections such
as GBB and RW slots defined with manually written fmd files, even
if they do not actually want to verify anything.
As discussed in CB:34977, measured boot should be decoupled from
verified boot and make them two fully independent options. Crypto
routines necessary for measurement could be reused, and TPM and CRTM
init should be done somewhere other than vboot_logic_executed() if
verified boot is not enabled.
In this revision, only TCPA log is initialized during bootblock.
Before TPM gets set up, digests are not measured into tpm immediately,
but cached in TCPA log, and measured into determined PCRs right after
TPM is up.
This change allows those who do not want to use the verified boot
scheme implemented by vboot as well as its requirement of a more
complex partition scheme designed for chromeos to make use of the
measured boot functionality implemented within vboot library to
measure the boot process.
TODO: Measure MRC Cache somewhere, as MRC Cache has never resided in
CBFS any more, so it cannot be covered by tspi_measure_cbfs_hook().
Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I18e513cefc373b1cd70d31d1159928cc948a8476
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.
Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Due to build rules, dummy acpi_tables source files were added in many
mainboards. With commit 1e83e5c61a
("src/arch/x86: Build mainboard acpi_tables source if present"),
the build system will build mainboard acpi_tables only if present. Remove
the dummy/empty/blank acpi_tables source files.
BUG=None
TEST=Build test with some google mainboards.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0cef34368e2e5f5e3b946b22658ca10c7caad90a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
It provides no useful information, so it might as well vanish.
Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch replaces and cleans up the redundant PTN3460 driver files in
/mainboard/siemens directories by using the now available driver in
src/drivers/i2c/ptn3460 and providing mainboard specific functions to
the driver.
TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...).
Change-Id: I976a502e7176a356bab772758250db3cdff529b9
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36643
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard needs VT-d to be enabled. Do so in devicetree.
Change-Id: I9f2f733163be019ac329660d7633b48c5d7896f1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The TPM chip needs to be added to the devicetree so that the ACPI tables
will be generated for it. These ACPI table entry is used by the OS to get
the location of the TPM chip.
Change-Id: Ic40d1cf236dd849f04f088808d94b6dd81e3238a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This mainboard variant uses SD-card and not eMMC. Therefore eMMC
controller is disabled while SDHCI is enabled.
Change-Id: I40b314905730b5d74c674d2251f8a4e5c807805f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36676
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this mainboard variant the PCIe-2-PCI bridge is used a bit different.
Adjust the switched off clock lines to match the mainboard
configuration.
Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch adds a new mainboard variant called mc_apl6 which is based
on mc_apl3. So far only the names have been adjusted with no further
changes. Following commits will introduce the needed changes for this
mainboard variant.
Change-Id: Ic935f6cc1f037947b2c167696d40da8309e4d4f0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As fmaptool can now handle the offset computation for every mentioned
region in the fmap file on its own there is no need to provide the
offset in the fmd file anymore. This patch clears this out so that the
files are way more readable now.
Change-Id: I1dc841604fdb662e08cb6690ff4bf6dd311e01d8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Refactor I2C driver for fsp_baytrail to match the coreboot supported I2C
bus device structure. The internal I2C controllers are now handled by
the generic PCI driver approach and generic I2C access is enabled.
As orientation for the I2C code the actual solution from
soc/intel/apollolake I2C was taken. All the I2C specific parts were
removed from lpss.c and have been implemented in the I2C driver.
Future merge to soc/intel/common/block/i2c/i2c.c would be possible.
With this patch I2C chip devices can now be used in devicetree.
TEST=Booted siemens/tcu3 and verified that access to PTN3460 worked.
Change-Id: I3b87bd7c27e4c1afcce7cd4225cca02599f43c60
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The two GPIO functions variant_gpio_table() and
variant_early_gpio_table() provide the pointer to the variants GPIO
table for late and early GPIO init. As these functions are variant
dependent the keyword __weak must not be used as otherwise the linker
might choose the tables from the baseboard.
This patch removes the __weak definition making these functions
overriding the general ones in baseboard/gpio.c.
Change-Id: Ic7fc816d40cb112d7ab51089c3962a77798c08a8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36094
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.
Change-Id: Iee12a5d1781c869b20bc14a52ecbf23474caa3fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Sort the names of all variant mainboards in an ascending order.
Change-Id: I19d502298744c0e0cbc91eb836c62ca90cdb9a5c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.
Change-Id: I3d58094256d2730dbd249291a8f1ed8df9dfe62d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
