Commit Graph

16292 Commits

Author SHA1 Message Date
Nico Huber 81b09f4008 Makefile: Make full use of src-to-obj macro
There were several spots in the tree where the path to a per class
object file was hardcoded. To make use of the src-to-obj macro for
this, it had to be moved before the inclusion of subdirs. Which is
fine, as it doesn't have dependencies beside $(obj).

Tested by verifying that the resulting coreboot.rom files didn't change
for all of Jenkins' abuild configurations.

Change-Id: I2eb1beeb8ae55872edfd95f750d7d5a1cee474c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28 00:31:00 +01:00
Kane Chen 116d67323b intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue.
LPC_CLKRUNB pin needs to be set to PU_20K to prevent leakage

TEST=Test on Strago and make sure the leakage is gone

Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: Id2bf7511806cdc52b505bb469238a9465b356352
Original-Reviewed-on: https://chromium-review.googlesource.com/317020
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13175
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 00:04:19 +01:00
Divagar Mohandass 2abcffcc40 intel/strago: EC_IN_RW gpio input configuration.
Configure EC_IN_RW signal as gpio input.

TEST=Boot to Chrome OS in normal mode and enter recovery mode
use ctrl-d to switch to Dev mode.

Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/304040
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-by: Gomathi Kumar <gomathi.kumar@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/13124
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 00:03:12 +01:00
Divagar Mohandass 39f84fa662 intel/strago: Clean up DDR configuration.
This change includes following changes:
- Clean up the DDR configuration and flow.
- Removing support for non LPDDR3 boards.
- Supporting only LPDDR3 and PMIC config.

TEST=Build/flash CB and boot the platform to OS.

Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297941
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13122
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 00:02:15 +01:00
Divagar Mohandass 4f4c6e88be intel/strago: Disable unused devices.
This change will disable unused devices in
device tree to improve boot performance.

TEST=Build/Flash CB and boot to OS.
verify Touch screen, Audio, WIFI and Track pad functionality.

Change-Id: Ib5ae31c96d75f9a5b0f8d8b72d058e18fe7d7e67
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/300943
Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Gomathi Kumar <gomathi.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/13423
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 00:00:32 +01:00
Shobhit Srivastava 97f09c3f19 soc/braswell: Fix leakage on V1P8S rail
Tristate MMC1_RCLK pin to fix leakage on V1P8S rail.

Original-Reviewed-on: https://chromium-review.googlesource.com/292043
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>

Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/12730
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-01-27 23:59:39 +01:00
Hannah Williams fc5489fc5e soc/braswell: Add macro NATIVE_INT_PU20K
Change-Id: I04db02d37a76f0643a73ae4d67b839e5cd61f7e3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13054
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-01-27 23:59:03 +01:00
Hannah Williams d4b26b2923 intel/strago: Fix GPIO config
Fix GPIO config for this board:
- SD card detect to GPI
- SATA GPI to not used
- GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination
- I2C4 SDA and SCL from not used to Native

Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13431
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 23:58:11 +01:00
Hannah Williams b11591064b soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEn
Change-Id: I42200feafed613136f23e37d4ab4c90931698821
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13038
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 23:56:50 +01:00
Lee Leahy a608969ebb drivers/intel/fsp1_1: Enable builds without MRC cache
Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to
cache the MRC settings.

TEST=Build and run on Galileo

Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13437
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 21:33:18 +01:00
Martin Roth 4b7a00867a intel/sklrvp: Remove mainboard
The Intel Skylake RVP3 mainboard is not building, and according
to Intel, there is no plan to continue working on it for coreboot.

The intel/kunimitsu board is the Skylake reference design for
coreboot.org.

Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13469
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-01-27 17:36:10 +01:00
Andrey Korolyov 393d9322ba ectool: fix NetBSD compilation
Since NetBSD does not support uname -o, push check for CygWin
inside separate non-failing condition in Makefile.

Change-Id: Ibd264384f49b33412f0ef8554bd9c9fb8f60a892
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/12831
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-27 17:15:56 +01:00
Julius Werner ffc2260d74 chromeos: vpd: Avoid reading uninitialized VPDs
This patch adds a check to the VPD parsing code to avoid reading the
whole thing if the first byte ('type' of the first VPD entry) is 0x00
or 0xff. These values match the TERMINATOR and IMPLICIT_TERMINATOR types
which should never occur as the first entry, so this usually means that
the VPD FMAP section has simply never been initialized correctly. This
early abort avoids wasting time to read the whole section from SPI flash
(which we'd otherwise have to since we're not going to find a Google VPD
2.0 header either).

BRANCH=None
BUG=None
TEST=Booted Oak, confirmed that VPD read times dropped from 100ms to
1.5ms.

Change-Id: I9fc473e06440aef4e1023238fb9e53d45097ee9d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20a726237e03941ad626a6146700170a45ee7720
Original-Change-Id: I09bfec3c24d24214fa4e9180878b58d00454f399
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322897
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/13467
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 16:27:27 +01:00
Julius Werner 4f7a3614cd chromeos: Add timestamps to measure VPD read times
This patch adds three timestamps to coreboot and the cbmem utility that
track the time required to read in the Chrome OS Vital Product Data
(VPD) blocks (RO and RW). It's useful to account for these like all
other large flash accesses, since their size is variable.

BRANCH=None
BUG=None
TEST=Booted Oak, found my weird 100ms gap at the start of ramstage
properly accounted for.

Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234
Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322831
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 16:27:18 +01:00
Werner Zeh 95bfcaecf9 cbfstool: Fix broken alignment because of flashmap
With the introduction of flashmap cbfs alignment of files gets
broken because flashmap is located at the beginning of the flash
and cbfstool didn't take care about that offset.
This commit fixes the alignment in cbfs.

Change-Id: Idebb86d4c691b49a351a402ef79c62d31622c773
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13417
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-27 07:05:41 +01:00
Patrick Georgi dd4b66e228 build system: Fix UPDATE_IMAGE
A quote was missing in a command.

Change-Id: I04148538007e5c450c6be113aab8a7fbb534db26
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reported-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13474
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-27 03:50:29 +01:00
Stefan Reinauer 7ee6cd5901 arch/x86: Drop arch/pciconf.h
It's unused, so get rid of it.

Change-Id: I28c6dc0208686edc3aabaf624773ea70350c1c8f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13177
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-26 20:22:44 +01:00
Patrick Georgi d6577e1cb8 xcompile: fill in power8 64bit LE
Change-Id: Id0316042f665ec9c095887cf6a37a7949ed8e861
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13421
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2016-01-26 18:10:34 +01:00
Patrick Georgi a1a6f7535b xcompile: also look for *-linux compiler triplet
Not just *-linux-gnu.

Change-Id: Ib817c6d207d3b69ce7595505f2b45f3be35b7d2f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13420
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2016-01-26 18:10:21 +01:00
Patrick Georgi 74c86456af xcompile: document all the variables!
What's the exact difference between TARCH, TSUPP and TBFDARCHS? Fear no
more, it's documented.

Change-Id: I18717eb1e20b1c0a82a485d391de2794a77c59ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13419
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2016-01-26 18:09:52 +01:00
Aaron Durbin 2dd5f4cce6 cbfstool: provide buffer_offset()
Instead of people open coding the offset field access within a
struct buffer provide buffer_offset() so that the implementation
can change if needed without high touch in the code base.

Change-Id: I751c7145687a8529ab549d87e412b7f2d1fb90ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13468
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-01-26 17:28:21 +01:00
Patrick Georgi 0a97d7eeba crossgcc: Enable powerpc64-linux target without ppc64-linux headers
It may still fail on non-Linux, and the compiler may do fancy things,
but it builds.

Change-Id: If3456f5fef8d01082a49978dc7cda5450f96f5cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13416
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-26 15:35:07 +01:00
Werner Zeh 998671c125 cbfstool: Fix compile issue for older gcc versions
gcc 4.4.7 fails to compile due to the missing initializers
for all struct members. Add initializers for all fields.

Change-Id: If1ad4fff0f965ccd7e821820c0703853c1e5c590
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13418
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-26 06:48:15 +01:00
Subrata Banik ed7275f2c3 Braswell: Implement Gpio library functions to read RAMID
Added GPIO library code to allow all BSW board specific code
to use memory configuration GPIOs in GPIO Input mode and read
them to determine which memory type is on the board.

Also added other GPIO related APIs to support GPIO access
in BSW.

Original-Reviewed-on: https://chromium-review.googlesource.com/294893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Idd65136c0449f0cdebfae12a510985e29889fa2b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12735
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-26 05:12:02 +01:00
Damien Zammit 2cfab90baa nb/intel/pineview: Increase MMCONF decoding to 256 busses
Linux kernel detects 256 busses but previously only 64 were
allocated.  Removes warning in OS.

Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13033
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-26 04:51:38 +01:00
Martin Roth b8f8cdbd9e Makefile.inc: error if UPDATE_IMAGE is enabled with no coreboot.rom
Instead of just failing with the statement:
'mv: cannot stat ‘coreboot.rom’: No such file or directory',
fail with an error that helps the user understand the issue.

Change-Id: Ie693d45710f599991514e0803a7c444636e473c9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13065
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-26 04:48:05 +01:00
Andrey Korolyov decefea272 superiotool: fix out-of-box NetBSD Makefile support
Add NetBSD-specific locations under pkg/ and missing linker flag
for libpciutils.

Change-Id: I812817a374aaba561b28d8a22f20d238c9dca32b
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/12830
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-26 04:47:25 +01:00
Nico Huber de45c59080 buildgcc: Help GMP build with 32-bit NetBSD
GMP's configure tries to build for 64-bit with a 32-bit userspace on
NetBSD too. Help it by forcing ABI=32.

Change-Id: I290ea0ef1626fdd88dc3ff74fadb9578ef6a1c9c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13067
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-26 04:45:57 +01:00
Martin Roth 4af5886ab1 src/arch: Update license headers missing paragraph 2
For the coreboot license header, we want to use two paragraphs.
See the section 'Common License Header' in the coreboot wiki
for more details.

Change-Id: I4a43f3573364a17b5d7f63b1f83b8ae424981b18
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13118
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-26 04:44:20 +01:00
Martin Roth 345f2b7d6b ga-g41m-es2l: Instead of forcing native VGA, make it selectable
This allows the native VGA to be disabled for debug, or if someone wants
to use the vbios.

Change-Id: I59a94fa0d02bfe254c8a598e15d3d9d73ecfe650
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12848
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-01-26 04:43:22 +01:00
Damien Zammit 2950cd2de1 mainboard/intel/d510mo: Licence fixes and azalia verb table
Azalia verb table replicated from vendor bios.
Licence headers added where appropriate.

Change-Id: I29e4fe433dee6c5f30fe36055fc9a8bf2062fef5
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12621
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-26 04:42:09 +01:00
Patrick Georgi 546f29dbf1 arch/x86: move SetCodeSelector to .text segment
It ended up in .data, and that doesn't seem to be actually necessary.

Change-Id: Ib17d6f9870379d1b7ad7bbd3f16a0839b28f72c8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-26 04:40:44 +01:00
Nico Huber ca41a6ab0a util: Look for python2 binary instead of python
Make the requirement of python2 explicit in scripts that are incompatible
with python3.

Change-Id: I77f150bdb3aab316fc3c3a21b911db397fa0106f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13286
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-26 00:25:19 +01:00
Nico Huber 32c4a06a43 Revert "util/crossgcc: Build Ada frontend by default"
This reverts commit 89798bcb0c.

Disable building gnat again as it turned out that many distros don't
ship with a sufficient recent version of gnat. We'll have to find a
reliable way to check for the installed gnat version and query the
user or bootstrap gcc in that case.

Change-Id: Ife7cf7c9d1567aca898ce308b120a7b9e146e5f5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/13422
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
2016-01-25 21:24:34 +01:00
Nico Huber 10b7ceface Makefile: Don't copy thin archives around
We can't just copy archives around as they may be thin archives which
contain relative paths. Using ar to create another thin archive should
result in the same archive with fixed paths.

Tested by verifying that the resulting coreboot.rom files didn't change
for all of Jenkins' abuild configurations.

Change-Id: Ic5743da2f4b5eb246fafd02181d66c5d40e7f00c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13179
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-25 14:24:10 +01:00
Werner Zeh 2bb574e52c mc_tcu3: Enable auto generated attributes in cbfs
Use CBFS_AUTOGEN_ATTRIBUTES for mc_tcu3 to enable position
and alignment attributes in cbfs.

Change-Id: I6c39bb02ab641d7e22e20e77a72a577f159549dd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13123
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-01-25 13:58:17 +01:00
Nico Huber 7224e87d10 util: Use /usr/bin/env as wrapper to look up python
This way users are not constrained to have it installed as
/usr/bin/python.

Change-Id: I822b6c402004aad8f2353e71afbd8ee3f9d26d45
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13285
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-25 01:28:52 +01:00
Timothy Pearson db84a99011 nb/amd/mct_ddr3: Properly set MR0 WR value
The existing code accidentally truncated the MSB from the MR0
WR value.  While this probably had a minimal effect in reality,
it should be configured correctly for maximal system stability.

Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13147
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-24 23:26:59 +01:00
Timothy Pearson ad9a2bb0de nb/amd/mct_ddr3: Add additional verbose-level debug statements
Change-Id: Ie91c990d9c2bcab8292a75d87523a46d5694a34a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13146
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:26:13 +01:00
Timothy Pearson 2d500ba598 nb/amd/mct_ddr3: Update drive strength configuration
The existing drive strength calibration code did not strictly
follow the BKDG-defined setup process.  Bring the calibration
code in line with the BKDG recommendations.

Change-Id: I122eeb93958d88de59d0c3b2979f607afa2c52c3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13145
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:25:18 +01:00
Timothy Pearson a2df081d44 northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devices
When an Extended Temperature Range DIMM is installed on a channel
the refresh rate should be increased per the BKDG recommendations
to allow correct operation at higher temperature ranges.

Set fast refresh on a channel if an ETR DIMM is installed on that
channel.

Change-Id: I7a085d34efc78f3f0794a5cb33b88f27a5e6d54e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13144
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:24:33 +01:00
Timothy Pearson ba2af2e21d cpu/amd/family_10h-family_15h: Move CBMEM storage out of CC6 save region
The existing CBMEM TOM calculations did not account for the CC6 save region
(when enabled); this resulted in CBMEM storage being placed on top of the
CC6 save region, which resulted in corrupt CBMEM data and a boot hang.

Change-Id: I32399da0438d7b16e05192449be625f9aa675b18
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13143
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:23:23 +01:00
Timothy Pearson 39495bae5f cpu/amd/family_10h-family_15h: Set LDT tristate correctly on C32 sockets
The existing code unconditionally cleared the LDT tristate enable bit,
which was incorrect for C32 sockets.  Update the code to be in line
with the BKDG recommendations.

Change-Id: I8095931973ea10f1467a6621092e88c6c494565a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13142
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-24 23:22:34 +01:00
Timothy Pearson 6aa6eab98b northbridge/amd/amdmct: Add termination and timing values for C32 sockets
The existing MCT initialization code was largely missing C32 socket-
specific configuration data.  Add C32 socket-specific timing and ODT
values as specified in the BKDG.

Change-Id: I8eef8d5c8581f03d269663a338d5542744c5cdd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13141
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:20:31 +01:00
Timothy Pearson 19ce16ae69 northbridge/amd/amdfam10: Update DRAM speed limits for C32 sockets
The existing code applied G34-specific speed limits to all socket
types.  Update G34 and C32 specific speed limits to be in line with
BKDG recommendations.

Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13140
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:20:02 +01:00
Martin Roth a39e6d1cf9 purism/librem13: Fix select of EC_PURISM_LIBREM
This was misspelled as EC_PURISM_LIBEM, causing the EC to not
get included in the build.

Change-Id: Iffbfb504926e1b90070c2dbf61c0c44ca8fb46bc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13178
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-24 17:04:17 +01:00
Martin Roth c4c7f166c2 Makefile.inc: Comment some 'else' and 'endif' statements
Help figure out which 'else' or 'endif' is attached to which 'if'.

Change-Id: I5ad068eb7c69f2dae57856f0e886f786563f7783
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13064
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-23 21:25:48 +01:00
Aaron Durbin eb907b3c90 arch/x86: link bootblock like other stages for C_ENVIRONMENT_BOOTBLOCK
When C_ENVIRONMENT_BOOTBLOCK is selected link bootblock using the
memlayout.ld scripts and infrastructure. This allows bootblock on
x86 to utilize all the other coreboot infrastructure without
relying romcc.

Change-Id: Ie3e077d553360853bf33f30cf8a347ba1df1e389
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13069
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-23 18:25:48 +01:00
Aaron Durbin 1b915b8904 lib/memrange: allow stack allocated free list
Instead of solely relying on malloc for building up an address space
for the range_entry objects allow one to supply a list of free entries
to memranges_init_empty(). Doing this and only calling malloc() in
ramstage allows a memranges oboject to be used in a malloc()-free
environment.

Change-Id: I96c0f744fc04031a7ec228620a690b20bad36804
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13020
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-01-23 18:25:26 +01:00
Patrick Georgi 4a30ab9096 cpu/amd: remove .intel_syntax
Replace with the more familiar AT&T syntax.
Tested by sha1sum(1)ing the object files, and checking the objdump that
the code in question was actually compiled.

Change-Id: Ibdc024ad90c178c4846d82c5308a146dd1405165
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13133
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-23 17:01:53 +01:00