Commit Graph

4345 Commits

Author SHA1 Message Date
Patrick Georgi 91bd3068a7 ACPI: More ../../.. removal
CPP is ran with src/ as part of its search path, so
using <northbridge/...> and the like is safe.

Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/649
Tested-by: build bot (Jenkins)
2012-02-22 22:16:15 +01:00
Patrick Georgi b05bf5bca9 amd/sb600: Move HAVE_HARD_RESET to southbridge
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/660
Tested-by: build bot (Jenkins)
2012-02-22 22:08:59 +01:00
Marc Jones fff8cdfcde Remove old AMD fam10 fixme comment
The family10 code had a very slow decompress before the cache settings were
fixed. This has been fixed for some time. Remove all the old messages from the
serial stream.

Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/672
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-02-22 11:35:17 +01:00
Dave Frodin c877d22a20 Force SB600 bootblock to use I/O for PCI config
If PCI config cycles use MMIO instead of I/O in the SB600 bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O and
configures the southbridge decode range to what is defined by the
mainboards Kconfig.

Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/632
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20 18:58:30 +01:00
Dave Frodin 5257c27cf7 Force SB700 bootblock code to use I/O for PCI config cycles.
If PCI config cycles use MMIO instead of I/O in the SB700
bootblock code the cycles will go nowhere since the MMIO feature
hasn't been configured yet. This change forces the cycles to use
I/O and configures the southbridge decode range to what is specified
by the mainboards Kconfig.

Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/631
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20 18:58:20 +01:00
Dave Frodin 2eacc0eec2 Force SB800 bootblock to use I/O for PCI config
If PCI config cycles use MMIO instead of I/O in the bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O.

Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/630
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20 18:58:07 +01:00
Marc Jones d8d8c63cf7 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
The MTRR check for WB TOM2 setting was only checking revF, not extended family
revisions. All families above revf indicate 0xf in the family field and have
additional bits in the extended family field.

Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/627
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20 05:37:26 +01:00
Martin Roth dc0bdbab2d Torpedo mainboard changes to fix warnings.
Fixes the warnings generated in the torpedo mainboard build.  Most of these
changes are similar to fixes already implemented in the persimmon mainboard.

Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5
Signed-off-by: Martin L Roth <martin@se-eng.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20 05:36:40 +01:00
Dave Frodin da52aed20d Fixes Fam10/SR5650 cpu not recognized message.
Extend the Family10 revisions checked byt the printk message.

Change-Id: Ia94daeefb1aabfb128c577b1e0aa52cf63d5cf44
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20 05:36:10 +01:00
Dave Frodin e42d639718 IEI-Kino Fam10 MPtable fix.
Make changes to MPtable to match the ACPI tables.

Change-Id: Icc18c9a25695d01d88d6ee5367064d527cc42bc1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/629
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20 05:35:12 +01:00
Dave Frodin 3aea95803d IEI Kino Fam10 ACPI table fixes.
Fix the ACPI IRQ routing. Also, fix the SSDT generations and TOM2 fixup.

Change-Id: Ica4a992d11bab63a510238dcd468b9fe80136def
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/628
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20 05:34:59 +01:00
Patrick Georgi a22f78b828 nvidia/mcp55: Move HAVE_HARD_RESET to southbridge
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/659
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-02-17 22:41:58 +01:00
Patrick Georgi 0e992be2b7 amd/sb700: Move HAVE_HARD_RESET to southbridge
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/661
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-02-17 22:41:52 +01:00
Patrick Georgi c46f450801 intel/i82801cx: Move HAVE_HARD_RESET to southbridge
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/662
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-02-17 22:41:49 +01:00
Patrick Georgi e0ddbc7b80 sis/sis966: Move HAVE_HARD_RESET to southbridge
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I9762ef01fc10c453ef643599c1c5dc8ee78081c3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/663
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-02-17 22:41:46 +01:00
Patrick Georgi 7389378b4f intel/i82801ex: Move HAVE_HARD_RESET to southbridge
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/664
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-02-17 22:41:43 +01:00
Patrick Georgi 62246f7121 intel/sch: Move HAVE_HARD_RESET to southbridge
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/665
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-02-17 22:41:40 +01:00
Patrick Georgi 024d8d9c22 amd/sb800: Move HAVE_HARD_RESET to southbridge
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge. (cimx/sb800 is a "different"
chipset)

Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/666
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-02-17 22:41:37 +01:00
Patrick Georgi c726e03624 broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.

Change-Id: Id95660f088c8240606d45abf326cd5eefca30da3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/658
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-02-17 20:09:24 +01:00
Patrick Georgi 334328a51f Avoid ../../.. paths in ASL files
The current directory is always part of the search path of cpp when
using #include "..."

Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 19:25:35 +01:00
Patrick Georgi fdcd135b96 Rename i945 ACPI files to not carry an i945_ prefix
In the spirit of the earlier renames.

Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/647
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 19:24:30 +01:00
Patrick Georgi f01291dd64 nvidia/ck804: Move HAVE_HARD_RESET to southbridge
No in-tree ck804-using board has it not selected, so move
selection from boards to southbridge.

Change-Id: I3064b406cfd5ad18067c597bd5b5866a720f7e87
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/657
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 19:23:39 +01:00
Patrick Georgi 472efa6041 Remove whitespace.
Fix issues reported by new lint test.

Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 19:04:31 +01:00
Patrick Georgi 152738f2eb amd/amd8111: Move HAVE_HARD_RESET to southbridge
No in-tree amd8111-using board has it not selected, so move
selection from boards to southbridge.

Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/654
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2012-02-17 19:00:14 +01:00
Patrick Georgi 4eee42f1d0 via/cx700: Move HAVE_HARD_RESET to northbridge
No in-tree cx700-using board has it not selected, so move
selection from boards to northbridge.

Change-Id: Ifa79954a48cf99b5f7e49960eafce805401e571c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/656
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 18:59:28 +01:00
Patrick Georgi a842aecabc intel/82801dx: Move HAVE_HARD_RESET to southbridge
No in-tree 82801dx-using board has it not selected, so move
selection from boards to southbridge.

Change-Id: I69671cb6411a6cd9c791059ae9546dff3aff702c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/655
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 18:58:17 +01:00
zbao 93dd07f3d5 Exit building if romstage.bin is larger than size of XIP
When the romstage.bin becomes bigger than the size of XIP, the
cbfstool can not allocate the romstage in the CBFS. But it doesn't
report an error. It will take quite a while to find out the root
cause.

Change-Id: I5be2a46a8b57934f14c5a0d4596f3bec4251e0aa
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/650
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-17 17:45:23 +01:00
Kerry Sheh 6d6d18efe8 Mainboard: Add AMD dinar mainboard.
Dinar mainboard is an AMD evaluation board for
Orochi Platform family15 model 00-0f processor.

The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets.
16 cores InterLagos Opteron processor are supported.
Windows 7 are verified on this platform.

Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/564
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-17 17:39:51 +01:00
Kerry Sheh 3c71a8579b SIO: Add smsc sio1036 superio
Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/563
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-17 17:19:34 +01:00
Kerry Sheh c94940cd64 SIO: Add smsc/sch4037 superio support
Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/562
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-17 17:18:17 +01:00
Denis 'GNUtoo' Carikli ea52223f53 M4A785-M,M4A785T-M: fix SSDT tables
This commit is based on the commit 94fa3db366
    (AMD Mahogany Fam10 ACPI table fixes.)

Change-Id: I9a9bf955de0a2a7accdbce8561b23596a8641af4
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/636
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 22:41:28 +01:00
Denis 'GNUtoo' Carikli 250f655127 M4A785T-M: fix TOM2.
This commit is based on the commit 94fa3db366
(AMD Mahogany Fam10 ACPI table fixes.)

With commit permit to boot without pci=nocrs on the M4A785T-M board.

Before the fix dmesg contained the following:
  [    0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
  (20110112/psargs-359)
  [    0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
  (20110112/psargs-359)
  [    0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
  (20110112/psargs-359)

Now it only contains:
  [    0.312102] TOM: 0000000080000000 aka 2048M

Change-Id: I5d517604abe938af19b70d57d92c1f973114c1cd
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/635
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 22:36:18 +01:00
Kerry Sheh 131c936b45 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper
Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/561
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 22:31:53 +01:00
Kerry Sheh 6811f75457 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper
Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/556
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 21:26:14 +01:00
Kerry Sheh 134d8a94de HWM: Nuvoton W83795G/ADG HWM support
Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans,
they are controled by a separate W83795G Hardware Monitor chip.
This patch adds Nuvoton W83795G/ADG HWM support.

Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/569
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 21:22:41 +01:00
Kerry Sheh a3f060748b Mainboard: Supermicro/h8qgi mainboard update
1. Supermicro H8QGI mainboard update to support both family10 Revison D
   processor and family15 model 00-0fh processor in one binary image.
2. RD890/SR56X0 IO hub CIMX wrapper support.
3. SP5100/SB700 southbridge CIMX wrapper support.

Both 8 cores and 16 Cores InterLagos Opteron Processor are
tested on this platform.
Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested.

Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/567
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 21:19:09 +01:00
Kerry Sheh c55f5a0e07 SIO: Winbond w83627dhg update
1. Stop include c file.
2. W83627dhg Pin 89, Pin 90 are multi function pins,
   add support to select them to I2C function.

Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/565
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 21:08:50 +01:00
Kerry Sheh 6b909f21af RD890: AMD RD890/SR56X0 CIMX wrapper
Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0,
RD890 and 990FX chipsets.

Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/559
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 19:35:09 +01:00
Kerry Sheh e41745e5d6 pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids
Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/609
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 19:27:29 +01:00
Kerry Sheh d3e990c6e5 AGESA F15: AGESA family15 model 00-0fh cpu wrapper
Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/555
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 19:26:32 +01:00
Kyösti Mälkki 53c1d204ed Intel cpus: use CPU_PHYSMASK_HI define in CAR
Unifies models 6ex, 6fx and 106cx.

Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/638
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-16 01:55:50 +01:00
Kyösti Mälkki adf105fe45 Intel model_106cx: Use symbolic names for MTRR bits
Change-Id: I6ea5ca631c22fe870224a498b68d77d85798b3f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/637
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-15 18:04:33 +01:00
Kyösti Mälkki 7916f4cef6 AMD Geode cpus: apply un-written naming rules
Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.

Rename directories and Kconfig as follows:
   model_lx  -> geode_lx
   model_gx1 -> geode_gx1
   model_gx2 -> geode_gx2

Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-13 21:56:38 +01:00
Kyösti Mälkki e13632a939 Intel cpus: apply un-written naming rules
Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.

Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x.

Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/618
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-10 23:40:07 +01:00
Sven Schnelle bdc8c83614 Remove non-existent include
Change-Id: I702d59371b4a57ce22623cbab6e936b653d57edf
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/619
Tested-by: build bot (Jenkins)
2012-02-10 14:54:36 +01:00
Sven Schnelle 332a7e91c7 i5000: halt second BSP
If both FSBs on i5000 are equipped with CPU packages, one CPU
from each package is elected as BSP. To prevent races between
both BSPs, hlt the second BSP.

Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/615
Tested-by: build bot (Jenkins)
2012-02-10 10:28:18 +01:00
Sven Schnelle 6d64adeaa6 Add Intel Socket LGA771
Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/492
Tested-by: build bot (Jenkins)
2012-02-09 21:12:34 +01:00
Kyösti Mälkki 12b72624ee VIA cpus: apply un-written naming rules
Rename files and directories:
  model_c3 -> c3
  model_c7 -> c7

Change-Id: If144fc501e8ae44b347ac44fa90c689c33a8e126
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/614
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-09 19:45:49 +01:00
Kyösti Mälkki c466287d4d Remove no-op Makefiles under mainboard directory
Patch removes following files:

    src/mainboard/amd/serengeti_cheetah/Makefile.inc
    src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
    src/mainboard/broadcom/blast/Makefile.inc
    src/mainboard/hp/dl145_g1/Makefile.inc
    src/mainboard/msi/ms9282/Makefile.inc
    src/mainboard/supermicro/h8dme/Makefile.inc
    src/mainboard/tyan/s2881/Makefile.inc
    src/mainboard/tyan/s2892/Makefile.inc
    src/mainboard/via/epia-m700/Makefile.inc

Change-Id: I020776313abff1772be38afc896af51ca5ab6453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/612
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-09 01:38:27 +01:00
Kyösti Mälkki 9dd3ef165a Don't loop infinitely long on serial comm failures
If serial uart (8250/16x50) takes abnormally long to respond, give
up on logging to serial console and instead let the system boot.

Also reference bit in LSR register with correct name.

Change-Id: I3796efc3e8690425f04a130af4bc99541b64d335
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/611
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-02-07 20:37:20 +01:00