Commit Graph

4345 Commits

Author SHA1 Message Date
Sven Schnelle b2f173e168 i82801gx: Fix port status in AHCI mode
The code used PCI register 0x92 to enable sata ports,
which is wrong. The ICH7 documentation states:

"This register is only used in systems that do not
support AHCI. In AHCI enabled systems, bits[3:0] must
always be set (ICH7R only) / bits[2,0] must always be set
(Mobile only), and the status of the port is controlled
through AHCI memory space."

Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write
0x0f for both variants. This patch makes sata_ahci work on
my Thinkpad T60 and X60s.

Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/340
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27 18:27:07 +02:00
Sven Schnelle 6eb8bef25e X60: enable Cx power saving modes
Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/331
Tested-by: build bot (Jenkins)
2011-10-25 21:03:30 +02:00
Sven Schnelle f02c396f26 T60: add _CST table
Used by power management code to enable Cx powersaving modes.

Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/322
Tested-by: build bot (Jenkins)
2011-10-25 20:38:44 +02:00
Sven Schnelle d2bc117f79 T60: enable C4onC3 mode
It is safe to enable this setting on these Boards.

Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/330
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25 20:13:30 +02:00
Sven Schnelle fe40c5067e T60: use ICS954309 clock driver
Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/328
Tested-by: build bot (Jenkins)
2011-10-25 20:13:16 +02:00
Sven Schnelle f488165a3d Add driver for ICS954309 clock generator
Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/327
Tested-by: build bot (Jenkins)
2011-10-25 19:22:22 +02:00
Sven Schnelle 906f9ae784 i82801gx: Add setting for C4onC3 mode
If this bit is set, ich7 will enter C4 mode if possible instead of
C3. See ich7 specification (LPC controller, Power management control
registers) for more details.

Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25 19:20:34 +02:00
Sven Schnelle 5460097041 SPEEDSTEP: write _CST tables
Change-Id: Idb4b57044808918de343d31519768d0986840f01
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/321
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25 18:59:10 +02:00
Sven Schnelle 0b86c76cfc ACPI: Add function for writing _CST tables
Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/312
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25 18:58:50 +02:00
Christoph Grenz d17f3d7019 w83627hf: correct typo in ASL include, correct indexed registers and remove unneccesary _PR0 defs
Correct a typo in devtree.asl which causes AML processors to fail executing
the DSDT with AE_NO_MEMORY or (in case of acpiexec) Divide By Zero.
Also removes an superfluous item in the register IndexField and removes
unneccessary _PR0 definitions which could confuse AML processors.

Change-Id: I02cb9ce4e8f2101cfff8cec4abba7e070fd66364
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/296
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25 17:52:06 +02:00
Sven Schnelle d0ea6789e6 Lenovo H8: Fix h8_set_audio_mute()
Logic is inverted (if argument is true, one would expect that
mute is enabled) and the wrong bit was used (1 instead 0)

Change-Id: I71133ba639f1fb0d3c3582f16211dd266a11cc64
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/334
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25 17:48:41 +02:00
Sven Schnelle 2b1fbbbc89 X60/T60: remove superflous h8_set_audio_mute()
muting is handled by h8 code, no need to do it here.

Change-Id: I3f152e99f30701cd032b03105cbe3ae778865305
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25 17:47:10 +02:00
Sven Schnelle 718afbed82 i82801gx: Add write and read/write block functions
Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/326
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25 17:35:44 +02:00
Sven Schnelle 3c976791b0 i82801gx: Don't set I/O base address to static value
Doing it this way will break all subsequent smbus calls, because
the smbus code still uses res->base, which points to the old base
address. Fix this by allocating a proper resource.

Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/325
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
2011-10-23 23:05:44 +02:00
Christoph Grenz 5cfd583c5c console: support integrated 7-segment displays for POST codes
Add a configuration option POST_PORT which defaults to 0x80 and
can be redefined by boards which have integrated POST displays
on another I/O port. Change post.c to output POST codes to this
port instead of 0x80 hardcoded.

Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/221
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-23 17:25:04 +02:00
Kerry Sheh f3b0500050 SB800: Hide unused gpp ports
Add configure option SB_GPP_UNHIDE_PORTS for mainboard
to hide/unhide the unused sb800 gpp ports.
Certain gpp port should be hidden, if no device was detected and
hotplug feature is disabled for such port.
Hidden unused ports makes lspci -vvv get more accurate information under Linux.
Test on avalue/eax-785e mainboard.

Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-23 14:08:20 +02:00
Stefan Reinauer d1bc331855 Extend coreboot table entry for serial ports
Add information about memory mapped/io mapped base addresses.

and fix up libpayload to use the same structures

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb
Reviewed-on: http://review.coreboot.org/261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-21 23:34:30 +02:00
Kyösti Mälkki b6010b8e70 Remove redunancy in Kconfig
Socket Kconfig unconditionally selects CPU_INTEL_CORE.

Change-Id: I5eb7dd17047a2a031dd7345390d7f5f756055e18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/307
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-21 21:52:42 +02:00
Patrick Georgi 1465385db0 sch: strip quotes around cmc.bin filename
This was mentioned several times already, how about we get it in?
It avoids cbfstool to fail because path/to/"file" doesn't work.

Change-Id: Ia01acbd78f81a5db890fd1573a2f3cbe1450562f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/305
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-21 16:14:38 +02:00
Stefan Reinauer 02e75b2b67 Use ntohll where appropriate.
also clean out a local copy of ntohl in yabel.

Change-Id: Iffe85a53c9ea25abeb3ac663870eb7eb4874a704
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/288
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-21 14:14:32 +02:00
Stefan Reinauer 9ea33e9318 Add macros for 64bit byte order swapping
Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/275
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-21 14:13:19 +02:00
Sven Schnelle b538110532 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.

To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.

Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/282
Tested-by: build bot (Jenkins)
2011-10-20 16:06:35 +02:00
Kyösti Mälkki 2588db496d i82801dx: Replace romstage printk's
Patch is required to compile this with romcc.

Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/291
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-20 01:50:11 +02:00
Peter Stuge 096161a5e4 asrock/e350m1: Enable the superio ACPI device in devicetree.cb
This makes the power_on_after_fail NVRAM option work correctly.

Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/292
Tested-by: build bot (Jenkins)
2011-10-19 16:36:11 +02:00
Kyösti Mälkki 939103c622 IOAPIC: fix bitmask
APIC ID is bits 27..24, not 19..16.

Change-Id: Ib53a480bf4328901094ca2c4713e8317321962a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/299
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19 06:49:38 +02:00
Stefan Reinauer 76c44aeea9 sconfig: check whether component directory actually exists
and add drivers/generic/generic back (empty), since it is used by many
devicetree.cb files.

Without this patch typos in component names in devicetree.cb cause
the component to be silently ignored.

Change-Id: I3cfca2725816f0cd7d72139ae53af815009e8ab4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/270
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19 03:31:21 +02:00
Stefan Reinauer 6a11333133 Drop eh_frame instead of moving it into the image.
That's what SeaBIOS does, too, and it works just fine.

Change-Id: I3e17c15848aca86f775fc86f4ad906c820625887
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/269
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19 03:25:09 +02:00
Sven Schnelle 5563959b09 I945: replace #if defined() by #if
config.h defines also unset config options (as "0") so #ifdef
matches both settings, which isn't what we want.

Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/293
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-19 00:09:23 +02:00
Kyösti Mälkki 19fd2112f7 Append logical PME/GPIO device. Fix MPU device number.
A mainboard may require configuration of the superio pins to fully
support some features. Things like A20# gate, leds, fans, infra-red
and bootstrap jumpers may be configured and controlled through the
logical PME device.

Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/289
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-18 00:11:33 +02:00
Kyösti Mälkki 521d8c2573 Activate older Xeon P4 microcodes
As new microcode files were included, the table was not updated with
families 0f25 and 0f26.

Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/290
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-18 00:10:51 +02:00
Stefan Reinauer d87dfc0c38 Fix our CMOS checksum algorithm so it matches what /dev/nvram expects
Our cmos checksum is inverted to what the Linux /dev/nvram device expects (and
BIOSes use). This makes it impossible to use /dev/nvram with coreboot. Fix it!

Change-Id: I239f7e3aca05d3691aee16490dd801df2ccaefd1
Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/279
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17 17:51:52 +02:00
Stefan Reinauer 1babddb202 rework RTC driver output to make it more consistent.
Also add a meaningful define (Not hooked up in Kconfig, that might
or might not follow)

Change-Id: I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/278
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17 17:51:40 +02:00
Oskar Enoksson a9a8b80191 Re-worked devicetree.cb for DL145 G1
After a lot of experimentation this commit improves some hardware
features that were not recognized or incorrectly configured before.
The only thing not tested is SCSI-option board (I dont have one).
Misleading errors in comments have been corrected.
(Note BTW that the DL145 G1 mainboard is identical to AMD Serenade
which was supported in early versions of coreboot but was dropped
for some reason.)

Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e
Reviewed-on: http://review.coreboot.org/237
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17 09:44:56 +02:00
Oskar Enoksson e2c05da300 Fixes several issues with amd k8 SSDT P-state generation
First issue fixed:
For multi-socket CPU the current implementation emitted
Processor objects for cores in the first CPU only. This
commit fixes the bug by really emitting one Processor
object for each core. However, the unlikely case of mixed
CPU models is still not handled correctly.

Second issue fixed:
One loop was wrong in case a processor in the table declares
no P-states at all. The rewritten loop is safe. Some possibly
dangerous array lengths were also fixed.

Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV
according to the BKDG. The current implementation always set it
to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS.

Fourth issue: If a processor without PowerNow! support was inserted in a
system with coreboot configured with SET_FIDVID then the boot process hanged
mysteriously and very early. Apparently because init_fidvid_ap tampers with
non-existing registers. This commit fixes the bug by bailing out
from init_fidvid_ap if PowerNow! capability is missing.

Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417
Reviewed-on: http://review.coreboot.org/239
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17 09:30:25 +02:00
Stefan Reinauer 3128685a91 SMM: Move wbinvd after pmode jump
According to Rudolf Marek putting a memory instruction between
the CR0 write and the jmp in protected mode switching might hang the
machine. Move it after the jmp.

There might be a better solution for this, such as enabling the cache, as
keeping it disabled does not prevent cache poisoning attacks, so there is no
real point.

However, Intel docs say that SMM code in ASEG is always running uncached, so
we might want to consider running SMM out of TSEG instead, as well.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Id396acf3c8a79a9f1abcc557af6e0cce099955ec
Reviewed-on: http://review.coreboot.org/283
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Tested-by: build bot (Jenkins)
2011-10-15 21:16:37 +02:00
Stefan Reinauer 1377491ac7 use byteorder.h instead of implementing another byte swap function
Change-Id: Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/277
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-15 16:21:06 +02:00
Stefan Reinauer 328a694a3f AMD CPU and chipset fixes for compilation with gcc 4.6
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/266
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15 13:40:17 +02:00
Stefan Reinauer ab87254b61 use acpi.h include instead of manually adding acpi_slp_type.
Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/276
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15 12:30:02 +02:00
Stefan Reinauer 2d17299395 cbfs_and_run_core() is not part of the API, make it static.
It's only used in cbfs_and_run.c

Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/273
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-10-15 12:27:52 +02:00
Stefan Reinauer f830752c87 reformat Makefile.bootblock.inc (>80 lines per char)
Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/274
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15 12:25:20 +02:00
Stefan Reinauer 971ebd8ee6 Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6
Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/268
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14 22:57:11 +02:00
Stefan Reinauer 86fc9848ae Fix compilation of AMD GX2 northbridge code with gcc 4.6
Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/267
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14 22:54:06 +02:00
Stefan Reinauer 89fcdec972 Fix compilation of VIA CN700 northbridge code with gcc 4.6
Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14 19:12:10 +02:00
Stefan Reinauer b9d60c9ac8 fix compilation of intel/sch northbridge code with gcc 4.6
Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/264
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14 08:12:25 +02:00
Stefan Reinauer 499af708ca Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6
Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/263
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14 08:12:06 +02:00
Stefan Reinauer 513eb5a956 Prevent build breakage without consoles enabled
If all console types are disabled, coreboot will fail to compile because
static code is unused. This patch fixes the issue.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2
Reviewed-on: http://review.coreboot.org/260
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 20:11:33 +02:00
Stefan Reinauer 71496bea9b Load an IDT with NULL limit
Load an IDT with NULL limit to prevent the 16bit IDT being used
in protected mode before c_start.S sets up a 32bit IDT when entering
ram stage.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e
Reviewed-on: http://review.coreboot.org/259
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 20:02:46 +02:00
Stefan Reinauer d17fe51d9a Fix compilation of x86emu with gcc 4.6.x
gcc 4.6 complains about unused but set variables in x86emu.
Particularly some variables are always set but only used in
debug mode, or when FPU support is enabled.

Change-Id: Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/258
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 20:01:47 +02:00
Stefan Reinauer b6b8871dd3 Fix native x86 option rom initialization
- Intel option roms want an initialized i8259 or they will
  throw an exception 6. This should be done in the southbridge
  code, but that is executed much later than the VGA init, so
  initialize the i8259 in src/devices/oprom/x86.c.
  In the long run this will allow getting rid of some of the
  ugly hacks in some AMD boards' romstage.c
- Don't overwrite the mode when copying mode info information back
  from 0x600.

Change-Id: Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/257
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 20:01:37 +02:00
Stefan Reinauer c1efb90384 refactor vesa mode setting code and bootsplash code
- adds possibility to set a vesa mode without showing a bootsplash
- make bootsplash / mode setting code available in real mode.

Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/256
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 20:00:50 +02:00
Stefan Reinauer 216fa4633a Refactor option rom initialization code in coreboot.
- move int15 handler out of the generic code into the mainboard directories
  of those mainboards that actually use it.
- move vbe headers to vbe.h
- move function prototypes used in native oprom code to x86.h

Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/255
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 20:00:37 +02:00
Stefan Reinauer 491e2a29b9 Enable/fix compilation of i8254 code in ram stage.
Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/254
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 20:00:22 +02:00
Stefan Reinauer a251dee1ee Use default table creator macro for all SSDTs
Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/262
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 19:59:45 +02:00
Stefan Reinauer 8d427ece81 Fix romstage creation with gcc 4.6 and CAR targets
newer gcc versions generate ".section .text" instead of just ".text"
in their assembler output. This patch makes sure that we don't end up
with a superfluous ".section" that makes the build fail.

Add -Wno-unused-but-set-variable to CFLAGS if the flag exists.

Change-Id: I7f24c987433cc5886dde2af27498d3331cbda303
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/252
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-13 14:20:12 +02:00
Patrick Georgi 4e2d542a64 siemens/sitemp_g1p1: Don't mess with virtual wire settings
That function broke SMP on Linux 2.4, now it works.

Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/243
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 11:07:27 +02:00
Patrick Georgi c5ae30617a siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
Each variable is essentially unused or incorrect.

Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/242
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 11:07:23 +02:00
Patrick Georgi 390a3374ca amd/sb600: Enable COM2 at all times in early setup
Otherwise with a coreboot log on COM2 (which doesn't work) the boot
process takes eons.

Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/241
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2011-10-13 11:04:36 +02:00
Patrick Georgi b0a9c5ccf3 mptable: Refactor mptable generation some more
The last couple of lines of every mptable function were mostly
identical. Refactor into common code, a new function mptable_finalize.

Coccinelle script:
  @@
  identifier mc;
  @@
  (
  -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
  -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
  -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
  -return smp_next_mpe_entry(mc);
  +return mptable_finalize(mc);
  |
  -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
  -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
  -return smp_next_mpe_entry(mc);
  +return mptable_finalize(mc);
  )

Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/246
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:11:08 +02:00
Patrick Georgi c75c79bd02 mptable: Get rid of fixup_virtual_wire
As stated in some code files, fixup_virtual_wire was established
to avoid touching 200 invocations of the mptable code.

Let Coccinelle do it:
  @@
  type T;
  identifier v;
  @@
  -void fixup_virtual_wire(T v)
  -{ ... }

  @@
  expression A;
  identifier v;
  @@
  -v = smp_write_floating_table(A);
  +v = smp_write_floating_table(A, 0);

  @@
  expression A;
  identifier v;
  @@
  -v = smp_write_floating_table(A, 0);
  -fixup_virtual_wire(v);
  +v = smp_write_floating_table(A, 1);

Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/245
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:10:44 +02:00
Patrick Georgi 6eb7a53169 mptable: Refactor lintsrc generation
We copied pretty much the same code for generating mptable entries for
local interrupts (with some notable exceptions).
This change moves these lines into a generic function "mptable_lintsrc"
and makes use of it in many places.

The remaining uses of smp_write_lintsrc should be reviewed and replaced
by mptable_lintsrc calls where possible, and smp_write_lintsrc made static.

This patch was generated using Coccinelle:
  @@
  expression mc;
  expression isa_bus;
  @@
  -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
  -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
  +mptable_lintsrc(mc, isa_bus);

  @@
  expression mc;
  expression isa_bus;
  @@
  -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
  -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
  +mptable_lintsrc(mc, isa_bus);

  @m@
  identifier mc;
  expression BUS;
  @@
  -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin));
  ...
  -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
  -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
  +mptable_lintsrc(mc, BUS);

Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/244
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:10:31 +02:00
Rudolf Marek 3a1fe9dec1 Make Asus A8V-E SE better ACPI citizen.
Use the SSDT autogen infrastructure to support the automatic reserved resources,
automatic P-state generation and automatic _CRS PCI0 method.

Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/251
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-13 01:09:50 +02:00
Christoph Grenz 8ae574c805 w83627hf: ASL include containing virtual device tree of the SuperIO
Add a ACPI Source Language snippet to superio/w83627hf which maps the
SuperIO and most of the logical devices to PnP devices, exposing
configuration options and chip power management to the OS.
Written using the Winbond W83627HF/F datasheet.

Change-Id: I1108d29b341ef78fe7f1e574f98b680aada39daf
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/223
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:56:29 +02:00
Christoph Grenz 80311eab8c amdk8: ASL include for K8 temperature sensor support in ACPI
Add a ACPI Source Language snippet which if included as
shown in the comments in the file, exposes the 4 possible
temperature sensors in the CPU as ACPI thermal zones.

Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/222
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:54:25 +02:00
Kerry Sheh 55437c57a9 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
SB800 RAID ROM require to put the misc ROM to specific position,
this patch enable user to put the RAID misc ROM to the right place
in the coreboot image.

Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/249
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:45:09 +02:00
Kerry Sheh 0e6344e1cf SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
In order to make sure AHCI/RAID ROM works correctly
For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should
enable bus master and the ahci also should be enabled.

Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:43:48 +02:00
Kerry Sheh 56ed40acb2 avalue/eax-785e: Get SATA Mode from Kconfig option
Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/233
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 03:42:51 +02:00
Kerry Sheh d7e856b9cb sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
Add this option to enable/disable SATA IDE Combined Mode feature

Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/231
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 03:41:38 +02:00
Kerry Sheh 2c7c37a016 persimmon: complete the sb800 devicetree
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
enable_dev() function. If the devicetree don't have this device,
then sb_Before_Pci_Init will not get called.
So the missing sb800 USB3 devicees was add to the mainboard devicetree.
Because of no physical usb connector connected to USB3, the USB3 device setting was off.

Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/232
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 03:40:18 +02:00
Oskar Enoksson 07bf911931 Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB to
mark dram memory above 4GB as WB. However, AMD K8
rev E and earlier don't implement this bit and therefore need
MTRR spanning dram memory above 4GB. The current implementation
of amd_setup_mtrrs never generate MTRR above 4GB.
This caused memory > 4GB not to be recognized in e.g. Linux on those
rev E or older platforms. This commit should fix that bug.

Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1
Reviewed-on: http://review.coreboot.org/238
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 08:49:59 +02:00
Kerry Sheh 75df1062a1 mainboard: complete the sb800 devicetree even device is off
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
enable_dev() function. If the devicetree don't have this device,
then sb_Before_Pci_Init will not get called.

Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/230
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 08:11:59 +02:00
Kerry Sheh 4e9c4c8cc2 sb800: sata combine mode configure fix
Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to
configure SataIdeCombinedMode is wrong.

sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller
  0: IDE controller is exposed and Combined Mode is enabled.
     SATA controller has control over Port0 through Port3,
     IDE controller has control over Port4 and Port5
  1: IDE controller is hidden and Combined Mode is disabled,
     SATA controller has full control of all 6 Ports when operating in non-IDE mode

Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/229
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 08:07:21 +02:00
Kerry Sheh 1386fa747d persimmon: sb800 sata mode configure update
persimmon configure sb800 sata mode according to the
southbridge kconfig selection.

Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/227
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 07:59:43 +02:00
Kerry Sheh d4a0e7d0b6 sb800: Add sata ahci/raid mode kconfig option
If sb800 sata was configured as ahci or raid mode,
give the option to add ROM files.

Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/225
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 07:59:12 +02:00
Kerry Sheh f8adf7a129 pci_ids: Add sb800 SATA device raid mode device id
sb800 SATA device have different device id with different configure
mode, 4392h for RAID mode, 4393h for RAID5 mode

Change-Id: If54f7751f531c94ee725309a2a5c255390935ead
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/226
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03 23:27:22 +02:00
enok71 af90275a41 TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms
The hp/dl145_g1 motherboard did not work since commit
1f7d3c5672 (svn 6124). That commit added
TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process
stopped very early (no console output whatsoever). The same symptom was
reported on other AMDK8 based boards with amd8111 southbridge chips. This
commit seems to fix the bug. It adds a bootblock.c under
src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the
problem was that enum_ht_chains needs to be called before the southbridge
bootblock.c function, not after.

Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/235
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03 23:17:33 +02:00
QingPei Wang 8eb4273290 Add AMD Family 10h PH-E0 support
the patch file comes from
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE
/F10MicrocodePatch010000bf.c

Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/202
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-24 15:58:12 +02:00
Stefan Reinauer 03f82bd787 Use ACPI text fields consistently with all other boards
LXBIOS and LXB-DSDT are not used in other parts of the tree.
Make names consistent across the tree.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43
Reviewed-on: http://review.coreboot.org/224
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-21 00:31:45 +02:00
Marc Jones 8487229b91 Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.
Change-Id: Ic960fe09fbed2c8a31c7c9ac2c54f6c88efebed3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/219
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
Tested-by: build bot (Jenkins)
2011-09-17 20:28:19 +02:00
Marc Jones 96be74c7f6 Enable SATA AHCI for faster boot with SeaBIOS.
Change-Id: Ibd87422680350c112eabe1bb73b237031c3e9d6b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/220
Tested-by: build bot (Jenkins)
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
2011-09-17 01:53:41 +02:00
efdesign98 d7a696d0f2 Persimmon updates for AMD F14 rev C0
These are the changes for the AMD Persimmon mainboard
required to support the update of the AMD Family 14
cpu to rev C0.  There are many warning fixes; the agesa-
wrapper.c file has been changed to fix the amdinitlate
and amdlaterunaptask routines, and more.

Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/137
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-16 01:51:00 +02:00
efdesign98 83d59b945c Build warning fix for AMD Family 12
This trivial change adds a prototype to an existing
header file to fix a build warning for the AMD family
12 cpus.

Change-Id: Ic666bfbef867d17607eaa0f59570aea987a31f93
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/218
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 19:55:35 +02:00
efdesign98 d91c9b7e3c AMD Inagua platform updates
These changes update the Inagua platform.  The changes
include modifying the Kconfig to suggest video bios
and ahci rom implementations, changing the dimm spd
code to use the correct bus addresses, cleaning up the
makefile a bit, and fixing a duplicate definition
warning associated with the BIOS_SIZE value.

Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/136
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 19:23:56 +02:00
efdesign98 2c66060169 AMD Torpedo platform updates
This update fixes warnings and supports as necessary
the Agesa infrastructure changes required to support
the AMD Family 14 cpu update to rev C0.

Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/138
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 17:30:07 +02:00
efdesign98 4d2d5d5b3e AMD Agesa macro expansion fix
This change fixes the use of a macro that was
previously modified to fix a warning.  The macro
was used in a manner that doubly incremented a
pointer.  The pointer increment was removed from
the macro call and moved elsewhere.  In addition,
an unused macro was removed from both Family 12
and Family 14 code.

Change-Id: I577794bbc55d18f21170dda1d0bbdc6d776ce392
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/217
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-15 09:56:08 +02:00
efdesign98 3c59158810 AMD SB800 early console use fix
This change removes printk's that occur before
console init is called.  In the best case, these
would cause an extremely slow boot, and in the
worst case would cause a complete post failure.

Change-Id: I50388e71225e95db602aa45835c39126c1c920a3
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/216
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 00:44:09 +02:00
efdesign98 0bcfff7908 AMD Agesa changes to fix F14 boot issues
This collection of changes fixes a buffer addressing
issue by removing one level of indirection, fixes an
Agesa HT mailbox retrieval bug, and fixes a buffer
location-by-signature issue.

Change-Id: Ic8a8cb3f9abddd9ad59343a85dbbee5aa7633be3
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/215
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2011-09-15 00:24:00 +02:00
efdesign98 3f5ebd6533 AMD F14 Northbridge updates
This change is warning and whitespace fixes in the
northbridge code for AMD Family 14 rev C0 cpu update.
This does not address warnings in the mainboard,
Agesa, Cimx, or southbridge code.

Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/134
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 23:45:40 +02:00
efdesign98 99b6674bd2 Update to Asrock E350m1 for AMD F14 C0
This updates the E350m1 Agesa wrapper code to fix an
issue with AmdLateRunApTask.  It now passes the function
parameter through to the Agesa routine.  There is also
a change to the platform_cfg.h file that makes the
definition of BIOS_SIZE dependent on whether or not
it was defined earlier.

Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/139
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 22:59:14 +02:00
Kerry She 7b7b2c9ef9 mainboard: add avalue/eax-785 ITX mainboard
It's AM3 Socket, 880M + SB850 chipset, similar with advansus/a785e-i.
Onboard device UART, VGA, SATA, PCI Slot, 2 X16 PCIe slot, 4 X1 Pcie
slot, Lan, audio, PS2 keyboard/mouse and USB are verified.

Change-Id: I483363f5ff9fbfc5cda2f0521660751212f3e326
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/208
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 19:49:48 +02:00
Kerry Sheh 8c69b1d13b rs780: hide unused gfx ports and gpp ports
Hide the unused gfx ports and gpp ports if they are not configured as hotplug.
lspci -vvv will get more accurate information under Linux,
tested on avalue/eax-785e.

Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-14 07:47:30 +02:00
QingPei Wang e169f82edf Add IT8721F support
only the serial port is tested, keyboard/mouse are gonna
to be tested later, it may also need some more patches
to make it work completely.

Change-Id: Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/204
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 04:47:26 +02:00
Tobias Diedrich 4e22a3bc58 Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
uses the same acpi wakeup vector as S3.
Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
the power LED while sleeping.
acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
it is used in both romstage and ramstage after patch 3/3, whereas
i82371eb_early_pm.c is used only in romstage.
I used the name acpi_get_sleep_type instead of  acpi_is_wakeup_early
because I think acpi_is_wakeup_early is a bit misleading as a name since it
doesn't return a boolean value.

Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
added check for acpi_slp_type == 2 (resume from S2) should not
change behaviour of other boards:
northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:238:  acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
southbridge/via/vt8237r/vt8237r_lpc.c:239:  printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);

Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/188
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-12 15:56:12 +02:00
efdesign98 78834b794d Miscellaneous AMD F14 warning fixes
This commit adds in some more fixes to AMD F14 compile
warnings.  The change in the mtrr.c file is in prep-
aration for changes yet to com, but it is currently
innocuous.

Change-Id: I6b204fe0af16a97d982f46f0dfeaccc4b8eb883e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/133
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-12 14:55:24 +02:00
Noe Rubinstein 03169d3e1c Replace while with do; while to avoid repetition
Cosmetic only; replaces some 'while' loops with 'do; while' loops to
avoid repetition.

Replacement performed by the Ruby expression:
t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
	"\\1do \\2\n\\1\\3;")

Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/183
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:48 +02:00
Patrick Georgi ac624a638d Crank up CPU speed on Intel Core and Core2 CPUs
The CPUs start on their slowest speed, and were left that way by
coreboot. This change will speed up coreboot a bit, as well as
systems that don't change the clock for whatever reason.

Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/176
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:30 +02:00
Stefan Reinauer 7981b940a6 Report GSE chipset and warn if the code has been compiled for the wrong chipset.
It would be nicer to unify the code so that it does all detection at runtime
instead of compile time (but that would also significantly increase code size)
so if someone else wants to give it a shot...

Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/184
Tested-by: build bot (Jenkins)
2011-09-09 11:40:04 +02:00
Rudolf Marek 7f0e93060e Add support for the tracing infastructure in coreboot.
The compiler is forced to emmit special functions on every
entry/exit of the function. Add a compile time option
to support it. Function entries will be printed in
the console. The CONFIG_TRACE has more documentation.

Patch for userspace tools will follow.

Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/178
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:26:47 +02:00
Kerry She f73535c089 AMD F14 Rev C0 update
Add AMD Family14 Rev C0 cpu id

Change-Id: Iacd1c7b20e889da61a2085188766285f27e5c018
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/160
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:10:29 +02:00
Kerry She 6209c8299a AMD SB800 southbridge update
This patch enables access to the registers of the hardware monitor
logical device in the superio via isa ports 0x295/0x296.
Previously this was not enabled in the SB8xx LPC device.
This is required for initialisation in init_hwm() in
src/superio/winbond/w83627hf/superio.c and also by OS-level
sensor monitoring such as lm-sensors to access temperature,
fan monitoring and control and voltage registers.
asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.

Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
Signed-off-by: Per Hansen <perh52@runbox.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/159
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:10:05 +02:00
Kerry She feed329a0c AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.

Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:08:57 +02:00
Wang Qing Pei 16d3ec6a58 Adjust some code/comment of sb700 sata init
The inline comment of sata_init function seems not placed correctly.
Rearrange it.

Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/186
Tested-by: build bot (Jenkins)
2011-09-04 12:22:09 +02:00
Wang Qing Pei f6e37316d0 Disable dev3 on ma78gm-us2h
Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot.

Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/187
Tested-by: build bot (Jenkins)
2011-09-04 12:22:00 +02:00
Sven Schnelle ff31692e08 X60/T60: remove obsolete dmi.h
Change-Id: Id0e8bcc1b93a629f0620b84a060d7ff99a82de78
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/174
Tested-by: build bot (Jenkins)
2011-08-26 22:35:43 +02:00
Sven Schnelle 164bcfdd1b Add automatic SMBIOS table generation
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/152
Tested-by: build bot (Jenkins)
2011-08-26 20:08:52 +02:00
Alec Ari bc081cdf6d Minor ma785gmt clean-up
Change-Id: I9e889a6c475fb3283fa11f8b3de5baaf54235589
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/167
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-25 15:43:10 +02:00
Alec Ari e1562bdccb Fix up various dsdt.asl files
Change-Id: I46eb27847deb3a903ac9af347992a9954e50ff6e
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/166
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-25 15:42:14 +02:00
Alec Ari 0e615007ec Remove dead code
Remove dead code, copy and pasted from
tilapia's mainboard.c file into various
asus mainboard.c files

Change-Id: Ic715ccaad8ac0210401d4a99ecb11e943f6afe58
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/168
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-24 19:04:54 +02:00
Sven Schnelle 6901b561eb Lenovo H8: Always clear audio mute
The mute bit is set by ACPI before poweroff/going to suspend.
So clear it after resume, to have working volume control
even if the ACPI doesn't clear it on resume.

OSPM should control Audio mute with ec bit 0x30:6, so it is
safe to clear this bit even if the user has audio muted.

Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/162
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2011-08-19 14:17:06 +02:00
Sven Schnelle 8d0b86c9ab X60: use EC events 0x50/0x58 instead of GPIO GPE for Docking/Undocking
Change-Id: I674e5166f5fb7ba299e6f1231f30434a5bf731c5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/161
Tested-by: build bot (Jenkins)
2011-08-18 20:50:55 +02:00
Sven Schnelle d819853f85 export get_cbfs_header()
Change-Id: I4b6afcee3d0d169e03165a7fb48cfaef2e8253e2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/157
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-18 11:34:53 +02:00
Alexandru Gagniuc 1a2b318625 Do not compile nuvoton superio for all board
The nuvoton WPCM450 code is compiled for all boards regardless of
whether or not they use it. Compile it only for boards needing it.

Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/129
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-09 20:11:01 +02:00
efdesign98 9f6cbde890 AMD Family 14 Agesa warning fix
This change fixes one Agesa warning.  Originally this commit
included some changes that I later deemed unnecessary.

Change-Id: I31ad13bb92509228b89921561c340c95e5136370
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/132
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-09 19:59:49 +02:00
Jonathan A. Kollasch ebbfbd5911 ms7135: add ACPI support
Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/140
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-06 18:17:07 +02:00
efdesign98 84cbce2364 Update AMD F14 Agesa to support Rev C0 cpus
This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-06 18:06:18 +02:00
Jonathan A. Kollasch 0df0e14fb5 Add voltage control of southbridge and RAM on ms7135
Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/126
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 17:28:36 +02:00
Keith Hui e089a3f68d northbridge/intel/i440bx: Registered SDRAM modules support and fixes
Adds support for initializing registered SDRAM modules on
Intel 440BX northbridge.

Drops unneeded romcc-inspired programming tricks.

Only set nbxecc flags (see 440BX datasheet, page 3-16) when
a non-ECC module has been detected in a row via SPD; also
drops an unneeded intermediate variable used in setting them.

Boot tested on ASUS P2B-LS with regular and registered ECC
SDRAM under Linux and memtest86+.

Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: http://review.coreboot.org/128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 08:15:49 +02:00
Patrick Georgi b88351537b split CBFS support into shared core and extended functions
The core is data structures and basic file finding capabilities,
while option ROM handling, and loading stages and payloads is
"extended".

The core is rewritten to be BSD-l (its header already was), so
can be copied to libpayload verbatim.
It's also more robust in finding files in corrupted images, eg.
after partial erase or update.

Change-Id: Ic6923debf8bdf3c67c75746d3b31f3addab3dd74
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/114
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 08:10:54 +02:00
Keith Hui 1ac19e28ee cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
Bring from coreboot v1 support for initializing L2 cache on Slot 1
Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.

Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
Pentium III 600MHz, Katmai core.

Also add missing include of model_68x in slot_1, to address a
similar problem fixed for model_6bx by r5945.

Also change Deschutes CPU init sequence to match Katmai.

Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: http://review.coreboot.org/122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 08:10:12 +02:00
Jonathan A. Kollasch 8e9f156f48 Remove debugging code, or convert it to be selected by kconfig
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/130
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-03 21:28:14 +02:00
Jonathan A. Kollasch c2ffc6739c Use preferred style of fixed-width integer types
Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/125
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-08-03 17:56:42 +02:00
efdesign98 3ddb6b85f1 Add xhcbios and ahcibios rom handling
This change adds xhci and ahci bios rom handling that
is similar to the vgabios rom handling in the arch/x86
Makefile.inc to the Persimmon and Torpedo mainboards.
It also adds the basis for AHCI BIOS rom handling to
the Persimmon Kconfig.

Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/109
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 20:02:22 +02:00
efdesign98 95b6611c18 Add the SuperMicro H8QGI platform
This set adds support for the SuperMicro H8QGI mainboard.
It is a publicly available 4 socket board using AMD Family
10 cpus and AMD SR5650 and SB700 bridges.

Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/108
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 19:58:55 +02:00
efdesign98 3cab93ce8e Add SSE3 dependent code
This change separates out changes that were initially found
in the commit for XHCI and AHCI changes to "arch/x86/Makefile.
inc".  It also corrects a comment.  The SSE3 dependent code
adds a pair of CR4 access functions and a blob of code that
re-sets CR4.OSFXSR and CR4.OSXMMEXCPT.

Change-Id: Id97256978da81589d97dcae97981a049101b5258
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/113
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-22 08:22:59 +02:00
efdesign98 00c8c4a316 Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes.  The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements.  This particular change
affects all mainboards that use the SB700, and their changes are
include herein.  These mainboards are:
  Advansus a785e,
  AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
  Asrock 939a785gmh,
  Asus m4a78-em, m4a785-m,
  Gigabyte ma785gm,
  Iei Kino-780am2-fam10
  Jetway pa78vm5
  Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.

Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 00:20:59 +02:00
efdesign98 4b508341bc Add AMD Family 10 support to cpu folder
This change adds the AMD Family 10 cpu support to the
cpu folder.  It also updates the makefiles of the Families
12 and 14 to take advantage of a pair of shared files that
are moved to the cpu/agesa folder.

Change-Id: Ibd3a50ea7a3028bd6a2d2583f021506b73e2fce2
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/97
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-18 21:59:14 +02:00
efdesign98 b58640c5ef Add AMD Family 10 cpu support to northbridge folder
This change adds the AMD Family 10 cpu support to the northbridge
folder.  The northbridge/amd/agesa Kconfig and Makefile.inc are
changed as well.

Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/98
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-18 21:55:59 +02:00
Rudolf Marek 43358a5e24 Workaround the errata #181.
We use LDTSTOP# to trigger the FID/VID change on K8M890, because the
FID/VID SMAF is blocked by not yet configured internal VGA.
The memory controller is enabled later, nor the workaround makes any
harm to non-affected CPUs.

This update unbreaks compilation by declaring the tmp variable.

Change-Id: Icf5d126b8c8cd9ece6af41d3129315a777c8cef2
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/69
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-16 11:13:37 +02:00
efdesign98 229f7cb6d6 Add the AMD Family10 Agesa code
This change officially adds the Agesa code for the AMD Family 10
cpus.  This code supports the G34 and C32 sockets.

Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-15 14:17:00 +02:00
Scott Duplichan 4edbe004b8 Move AMD SB800 early clock setup.
Move the AMD SB800 early clock setup code that is needed for early
serial port operation from mainboard/romstage.c to sb800/bootblock.c.
This prevents code duplication and simplifies porting.

Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/96
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-14 04:16:23 +02:00
Marc Jones 5a91692466 Set SB800 ROM decode size based on kconfig.
Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/94
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-14 00:43:02 +02:00
Rudolf Marek 2a561a18de Enable SMI on M2V-MX SE
Finally the SMI routines are in good shape on AMD, lets enable this and later
implement ACPI on/off SMI commands.

Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/83
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-13 02:01:46 +02:00
Rudolf Marek b5b3b3bf8c Make AMD SMM SMP aware
Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE define,
later all 0xa0000 could be changed to use it. Remove the unnecessary test if
the smm_init routine is called once (it is called by BSP only) and also remove
if lock bit is set becuase this bit is cleared by INIT it seems.
Add the defines for fam10h and famfh to respective files, we do not have any
shared AMD MSR header file.

Tested on M2V-MX SE with dualcore CPU.

Change-Id: I1b2bf157d1cc79c566c9089689a9bfd9310f5683
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/82
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-13 02:01:35 +02:00
Kevin O'Connor a68555f48d Do full flush on uart8250 only at end of printk.
The previous code does a full flush of the uart after every character.
Unfortunately, this can cause transmission delays on some serial
ports.

This patch changes the code so that it does a flush at the end of
every printk instead of at the end of every character.  This reduces
the time it takes to transmit serial messages (up to 9% on my Asrock
e350m1 board).  It also makes the transmission time more consistent
which is important when performing timing tests via serial
transmissions.

Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-on: http://review.coreboot.org/90
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-07-12 11:36:20 +02:00
Sven Schnelle 40d99bc781 T60: enable GPIO before using GPIO I/O port range
Change-Id: I39369e6f8a39f53f58a4b7fbe357637a79f5b596
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/93
Tested-by: build bot (Jenkins)
2011-07-11 15:50:03 +02:00
Sven Schnelle 14c93ec269 T60: dont use X60 USB init flag
ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch
initialization. Don't touch it on T60.

Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/92
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2011-07-11 15:18:00 +02:00
Scott Duplichan 7d6f0bf10e ASRock E350M1: ACPI-related BSOD fix
On installing/starting Windows (tested with Win7 Ultimate)
the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error.

From Scott Duplichan:
To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT
must be corrected. The attached patch does this. It uses the older
patching method, and not the (possibly preferred) AML generation
method. To simplify the patching operation, I moved the AML item
'TOM1' to the start of the SSDT. The patch also includes code to
confirm the AML variable TOM1 is at the expected offset before patching.

Also tested & working with Linux.

Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/91
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-10 18:31:29 +02:00
Cristian Măgherușan-Stanciu 1fe6c64ba1 Fix memory size reporting on AMD family 14h systems for >= 4GB
Applying Scott Duplichan's fix for memory >=4GB

Adjusted it to the new directory structure (agesa_wrapper was renamed to
just agesa).

Boot-tested and confirmed to work, on my board Linux can now access the
whole RAM.

Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/48
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-09 01:51:42 +02:00
Sven Schnelle 61cd5bfae4 T60: handle EC events in SMM if ACPI is disabled
Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/89
Tested-by: build bot (Jenkins)
2011-07-07 15:47:29 +02:00
Rudolf Marek 7f76290e2d Small SMM fixups
Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG).
While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just
spinlocking. The rep nop could not be used because "as" complains that rep is used
without string instructions.

Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/81
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-04 08:36:42 +02:00
Cristian Măgherușan-Stanciu ba48281faf whitespace-only changes in acpi.c, replaced spaces with tabs
Change-Id: Ibd598813bec0c93d77afbce8aee330498afbe5f6
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/74
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-07-02 15:48:54 +02:00
Cristian Măgherușan-Stanciu 9f52ea4c3c added a config option for ACPI debugging
Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/36
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-07-02 00:49:53 +02:00
Rudolf Marek 23b215272d Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and
for the transmit clock driving control. Unfortunately this is not enough
to make the HT1000 work reliably, therefore blacklist this for now in CPU
HT code. If ever anyone figure out what is wrong, it could be removed. The
downgrading now makes the board work on HT800, which is certainly better than
not at all with a HT1000 CPU.

Change-Id: I949bfd9b0b48ee12bd0234c2fb1deaaa773bd235
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/68
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-30 19:16:37 +02:00
Mark Norman 0d21cd36b7 Added support for Aaeon PFM-540I RevB PC104 SBC
The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU.
More infomation about the board available at www.aaeon.com.

Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/30
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29 18:32:59 +02:00
Sven Schnelle 811787abd5 i82801gx: read RTC status register to prevent IRQ storm
My Thinkpad appeared dead. After investigation, it turned out
that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI
handler didn't read the status register, so it was triggered again.

This is a really nasty situation, as it means you have to dissemble
your Notebook just to unplug the RTC battery.

Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/67
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-29 16:54:14 +02:00
Kerry She 3e706b63c0 amd southbirdge sb800 wrapper, pci bridge fix
sb800 pci bridge SHOULD enabled by default according to the chipset document,
but actually not enabled on some mainboard.
enable sb800 pci bridge when told to enable in devicetree.cb.
tested on ibase persimmon mainboard.

Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/63
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29 00:22:16 +02:00
efdesign98 770b877796 Add the AMD Torpedo mainboard
The Torpedo mainboard is the reference platform for
the AMD Family 12 cpus and the AMD Hudson-2 (SB900)
southbridge.

Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/54
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28 23:09:37 +02:00
efdesign98 7c0c64e103 Addition of Family12/SB900 wrapper code
This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.

Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28 23:09:25 +02:00
Sven Schnelle 180f81e9a9 SMM: add guard and include types.h in cpu/x86/smm.h
Change-Id: I002845cf7a37cd6885456131826ae0ba681823ef
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/64
Tested-by: build bot (Jenkins)
2011-06-28 11:23:11 +02:00
Sven Schnelle edcf9f4fe6 X60: remove pci config register save/restore
SMM code already makes sure this register is saved and restored,
so we don't have to do it.

Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/65
Tested-by: build bot (Jenkins)
2011-06-28 11:22:51 +02:00
Sven Schnelle d8b60a0f2d T60: undock on external power loss
If power is unplugged/lost, we should undock the docking station.
The power loss can also be caused by the fact that the user removed
the thinkpad from the docking station without pressing the Undock button/hotkey
first. Without undocking it on this event, the thinkpad LPC switch will still
connect the Docking connector, which causes crashes when docking it again.

Change-Id: I9ed783e491827bde20264868eab2b3a79c232922
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/62
Tested-by: build bot (Jenkins)
2011-06-23 14:12:26 +02:00
Sven Schnelle f8aa185c6f T60: enable userspace EC events
EC events 0x50-0x5f are never triggered by the EC. Instead they
can be generated by writing the wanted events to register 0x2a.

Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/61
Tested-by: build bot (Jenkins)
2011-06-23 14:07:26 +02:00
Sven Schnelle 8c17a63118 T60: add additional EC events
We missed a few bits, i.e the battery and some hotkey events.

Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/60
Tested-by: build bot (Jenkins)
2011-06-23 12:37:57 +02:00
Sven Schnelle 0326165a01 Add ThinkPad models
Change-Id: I4f1a5d99486929eb0be76a0ab3bf0158a23c7d36
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/59
Tested-by: build bot (Jenkins)
2011-06-23 11:35:52 +02:00
Sven Schnelle d266b6a999 T60: add missing License Header
Change-Id: I03636deac7b6d8e01654cf978b1aac79cba10641
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/58
Tested-by: build bot (Jenkins)
2011-06-23 10:38:42 +02:00
Sven Schnelle 3352b293d6 X60: add missing License Header
Change-Id: I9d6e80a633990e86dd3adfa2a761d09f62978349
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/57
Tested-by: build bot (Jenkins)
2011-06-22 17:53:38 +02:00
Sven Schnelle 3aefab54e1 H8: add missing License Header
Change-Id: If472e1e8bb93d64cc52a9084ad33fb9abbf0fb33
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/56
Tested-by: build bot (Jenkins)
2011-06-22 17:11:38 +02:00
Sven Schnelle d74f97e310 PMH7: add missing License Header
Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/55
Tested-by: build bot (Jenkins)
2011-06-22 17:02:03 +02:00
Scott Duplichan 3c74a2ab2c Move SB800 clock init earlier
Committing Scott's e350m1 changes (svn r6585):
Move SB800 clock init earlier,
Fixes problem where initial serial port output is garbled.

Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/32
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 06:46:14 +02:00
Cristian Măgherușan-Stanciu d367b00c5b Add the coreboot config to CBFS
The CBFS will contain a new file, named 'config' of type 'raw' that is a
stripped-down version of the .config file that was used to build the
current coreboot image. For space savings, all the comments and empty
lines were removed from the original config, except for one that lists
the coreboot git revision that's built into the image.

This is done in order to easily reproduce the work of  someone else when
only having their ROM image. In theory the reproduce could even be
automated by a new dedicated make target.

This should work even with abuild now.

Change-Id: I784989aac0227d3679d30314b06dadaec402749e
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/46
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 06:43:23 +02:00
efdesign98 621ca384a7 Move existing AMD Ffamily14 code to f14 folder
This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.

Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/52
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 01:35:45 +02:00
efdesign98 05a89ab922 Rename {CPU|NB|SB}/amd/*_wrapper folders
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.

Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 01:27:46 +02:00
efdesign98 ee39ea7e7e Add AMD SB900 CIMx code
This code is added to support the AMD SB900 southbridge.

Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/41
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-21 22:38:39 +02:00
efdesign98 b0969d65e6 Add AMD Family 12 cpu Agesa code
This is the addition of the AMD Family 12 cpu code.

Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c
Signed-off-by: Frank Vibrans<frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/40
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-21 22:37:51 +02:00
Stefan Reinauer d1cb0eecd1 sb800: move spi prefetch and fast read mode to sb bootblock.
So we don't waste time on the first cbfs scan.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
 in bootblock code: it doesn't like MEMACCESS[idx] |= value;]

Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20 19:08:05 +02:00
Cristian Măgherușan-Stanciu 46b033e8cb Introduced support for 8MB and 16MB flash sizes
Change-Id: I217ff84be3575ec09781710f19ad272c88227663
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/49
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20 18:15:44 +02:00
Marshall Buschman b531e4e8de ASRock E350M1: Enable USB3 support
Requires Scott Duplichan's patch for NIC support.
Enables required PCIe port for USB3 - does not interfere
with normal operations on non-USB3 model.

Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/45
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20 17:12:11 +02:00
Scott Duplichan 8fed77ae4c ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
Scott Duplichan's patch from the mailing list:
sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function
once, after determining device 0x15 function enables.

1) Update the asrock e350m1 devicetree.cb to match the hardware.
2) Change the way the sb800 cimx wrapper code works. The original
cimx code calls sb800 cimx function sbBeforePciInit() once. When
ported to coreboot, the gpp component of this function was called
once for each gpp port, as the gpp port's enable/disable state
became known. A 05/15/2011 change makes the early gpp code run
only once, triggered by processing the 4th gpp port. This method
is not general enough because the 4th gpp port is not enabled on
all boards. With the current change, the early gpp code runs when
the first gpp port is processed. If any gpp ports are enabled, the
first must be enabled. Tested with Win7 and linux on asrock e350m1.
This change will also affect amd inagua, and has not been tested
on that board.

Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/44
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-19 02:50:32 +02:00
Sven Schnelle 47b3fb403d SMM: flush caches after disabling caching
Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction.
For reference, the mail i've sent to ML with the bugreport:

whenever i've docked/undocked the thinkpad from the docking station,
i had to do that twice to get the action actually to happen.

First i thought that would be some error in the ACPI code. Here's a
short explanation how docking/undocking works:

1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock)
2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows:

   a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range
   b) Store(0, 0x808)   // Generates I/O Trap to SMM
   c) // SMM is executed
   d) Return (SMIF)    // Return Result in SMIF

I've verified that a) is really executed with ACPI debugging in the
Linux Kernel. It writes the correct value to GNVS Memory. After that,
i've logged the SMIF value in SMM, which contains some random (or
former) value of SMIF.

So i've added the GNVS area to /proc/mtrr which made things work.
I've also tried a wbinvd() in SMM code, with the same result.

After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized
that it starts with:

        movw    $(smm_gdtptr16 - smm_handler_start +
        SMM_HANDLER_OFFSET), %bx
        data32  lgdt %cs:(%bx)

        movl    %cr0, %eax
        andl    $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
        orl     $0x60000001, %eax /* CD, NW, PE = 1 */
        movl    %eax, %cr0

        /* Enable protected mode */
        data32  ljmp    $0x08, $1f

...which disables caching in SMM code, but doesn't flush the cache.

So the problem is:

- the linux axpi write to the SMIF GNVS Area will be written to Cache,
  because GNVS is WB
- the SMM code runs with cache disabled, and fetches SMIF directly from
  Memory, which is some other value

Possible Solutions:

- enable cache in SMM (yeah, cache poisoning...)

- flush caches in SMM (really expensive)

- mark GNVS as UC in Memory Map (will only work if OS
  really marks that Area as UC. Checked various vendor BIOSes, none
  of them are marking NVS as UC. So this seems rather uncommon.)

- flush only the cache line which contains GNVS. Would fix this
  particular problem, but users/developers could see other Bugs like
  this. And not everyone likes to debug such problems. So i won't like
  this solution.

Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/39
Tested-by: build bot (Jenkins)
2011-06-18 10:02:22 +02:00
Sven Schnelle 00d46499a2 T60: set dock LED's in mainboard.c
The docking takes place in romstage to have early serial I/O for debugging.
But to keep romstage small and prevent linking the EC code to romstage, set the
status LED's in ramstage.

Change-Id: I89fadbd61b6bfd9aff8c22370e51c84325f24751
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/42
Tested-by: build bot (Jenkins)
2011-06-18 10:02:09 +02:00
Sven Schnelle c045b4cc45 X60/T60: disable USB power during suspend
Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/38
Tested-by: build bot (Jenkins)
2011-06-16 17:20:56 +02:00
Sven Schnelle 86e1aea3e6 Lenovo H8 EC: add usb_power_enable()
Can be used to disable/enable Power output on USB ports.

Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/37
Tested-by: build bot (Jenkins)
2011-06-16 17:00:12 +02:00
Sven Schnelle bfe8e5186e SMM: don't overwrite SMM memory on resume
Overwriting the SMM Area on resume leaves us with
all variables cleared out, i.e., the GNVS pointer
is no longer available, which makes SMIF function
calls impossible.

Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/34
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15 23:11:44 +02:00
Sven Schnelle b629d14bec i945 GMA: restore tft brightness from cmos
Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/24
Tested-by: build bot (Jenkins)
2011-06-15 19:40:24 +02:00
Sven Schnelle d4dc9a5a03 Remove old ACPI code
it isn't used anywhere, and could be fetched from git/svn history if
needed.

Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/35
Tested-by: build bot (Jenkins)
2011-06-15 19:03:39 +02:00
Sven Schnelle d8c68a9d08 i82801gx: replace cafed00d/cafebabe by defines
We're using '0xcafed00d' all over the code as magic for ACPI S3
resume. Let's add a define for that. Also replace 0xcafebabe by
a define.

Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/33
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-15 15:15:07 +02:00
Sven Schnelle 8b39e07d04 X60: handle EC events in SMM if ACPI is disabled
Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/27
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15 08:51:36 +02:00
Sven Schnelle 4297a9a101 X60: trigger save cmos on volume/brightness change
Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/25
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15 08:51:18 +02:00
Sven Schnelle d29e5bb933 CMOS: add set_option()
Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/23
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-15 08:44:15 +02:00
Sven Schnelle d40d4f7712 X60/T60: set CMOS defaults
Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/26
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-13 21:58:52 +02:00
Marshall Buschman eab1db192f ASRock/E350M1: Skip memory clear for boot time reduction
Applying Scott's patches to e350m1, svn r6600:
Memory clear is not required for non-ECC boards.

Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/20
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-12 19:27:34 +02:00
Sven Schnelle 0f9cd43514 X60/T60: fix return value of mainboard_io_trap_handler()
The handler should return 1 if it handled the request. The current
code returns 0, which causes 'Unknown function' logs.

Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/29
Tested-by: build bot (Jenkins)
2011-06-12 17:28:10 +02:00
Sven Schnelle 5d9a83c9f0 log ec data with DEBUG_SPEW
Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/28
Tested-by: build bot (Jenkins)
2011-06-12 17:13:51 +02:00
Jonathan A. Kollasch fed129b0d5 Add ACPI automatic PIC/APIC interrupt routing logic for ck804
Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/13
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-10 19:44:04 +02:00
Sven Schnelle 1b8068e244 H8 EC: add volume CMOS setting
Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/12
Tested-by: build bot (Jenkins)
2011-06-09 10:05:46 +02:00
Marc Jones 486e03228e Revert changes to set the sb800 to AHCI mode.
Seabios doesn't have this support included yet,
which causes the generic Persimmon and other CIMx
sb800 platforms to not boot.

Change-Id: If07328b7c62d7fc314647adce8fab983ed327854
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/14
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-09 01:07:01 +02:00
Sven Schnelle 51e1bc3a7b T60/PMH7: move 'touchpad' option to pmh7
This option is PMH7 specific, and should be moved there,
so all Notebook utilizing a PMH7 have this option.
For Thinkpads without Touchpad (like the X60), simply
don't add 'touchpad' to cmos.layout.

Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/6
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-07 22:43:14 +02:00
Sven Schnelle e261807bac i82801gx: enable ACPI during S3 resume
disabling ACPI during S3 wakeup breaks ACPI wakeup, as the
Host OS is assuming that ACPI is enabled.

Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/7
Tested-by: build bot (Jenkins)
2011-06-07 22:11:46 +02:00
Sven Schnelle f4dc1a73e4 SMM: add defines for APM_CNT register
in the current code, the defines for the APM_CNT (0xb2) register
are duplicated in almost every place where it is used. define those
values in cpu/x86/smm.h, and only include this file.

And while at it, fixup whitespace.

Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/4
Tested-by: build bot (Jenkins)
2011-06-07 22:01:29 +02:00
Sven Schnelle b924eb45f1 T60: fix touchpad option
Code used 'int' as return type, but the cmos option is only one
bit. get_option returned with the value in bit 0-7, but all remaining
bits were left unitialized by get_option(). fix this by using char
as type.

Change-Id: I60e609164277380f936f66c99ef9508fa6a6b67c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/5
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-07 12:50:42 +02:00
Stefan Reinauer 44c1d3111b re-indent, so files conform to coding guidelines.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab
Reviewed-on: http://review.coreboot.org/8
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-07 11:58:31 +02:00
Sven Schnelle c21b054acc SMM: add mainboard_apm_cnt() callback
motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.

Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/3
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-06-06 17:56:13 +02:00
Stefan Reinauer fb38eb01ca WARNINGS_ARE_ERRORS is y per default, don't set it twice.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 16:30:27 +00:00
Peter Stuge d1760c834a Port persimmon r6594 to e350m1: Cosmetic cleanup
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:48:14 +00:00
Peter Stuge f8e33e356f Port persimmon r6593 to e350m1: Remove unused Kconfig options
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:47:56 +00:00
Peter Stuge 2334c8d2b7 Port persimmon r6592 to e350m1: Update GPP port configuration
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:47:30 +00:00
Marshall Buschman 314f4a2077 Port persimmon r6591 to e350m1: ROM cache early
Enable rom cache early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:47:05 +00:00
Marshall Buschman 1a7699f42a Port persimmon r6590 to e350m1: Work around memory allocation problem
Fix memory allocation problem in amdInitLate. Disabled until further debug.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:46:50 +00:00
Marshall Buschman bb2ca2bafd Port persimmon r6589 to e350m1: Strip down AGESA options
Remove some non-essential agesa options to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:46:32 +00:00
Marshall Buschman af85315707 Port persimmon r6588 to e350m1: VGA framebuffer
Declare legacy video frame buffer so that Windows generic VGA driver will work.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:46:13 +00:00
Marshall Buschman adc89b033e Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible
Declare RTC as not PIIX4 compatible to match AMD hardware.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:45:46 +00:00
Marshall Buschman ac4bef4907 Port persimmon r6586 to e350m1: FADT revision
Make fadt revision match its length. Solves Windows 7 checked build assert.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:45:29 +00:00
Marshall Buschman 552ad9f75e Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:45:12 +00:00
Marshall Buschman fd460e620e Port persimmon r6583 to e350m1: pstate 0 early
Switch processor cores to pstate 0 early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:44:54 +00:00
Marshall Buschman b3ee0d6bd6 Port persimmon r6582 to e350m1: 33 MHz SPI read early
Enable 33 MHz fast mode SPI read early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:44:31 +00:00
Peter Stuge 69e1bfcf34 Port persimmon r6578 and r6596 to e350m1: MMCONF base
Remove multiple mmconf settings and just use kconfig setting.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:44:14 +00:00
Marshall Buschman eb92b5ad64 Port persimmon r6574 to e350m1: MMCONF size
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:43:56 +00:00
Marshall Buschman 5a403191cb Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:43:38 +00:00
Marshall Buschman 6d5ee2d80a Port persimmon r6572 to e350m1: I/O APIC ID
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:43:15 +00:00
Peter Stuge e1898b5fa1 vt8237r: Simplify bootblock init to work around nested if() romcc problem
During the hackathon in Prague we discovered that romcc has a problem
compiling the previous nested if() statements correctly. This patch
makes the code a little simpler, and indeed works around the romcc issue.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:40:12 +00:00
Marc Jones 471f103e53 This patch sets max freq defaults for ddr2 and ddr3for fam10.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03 19:59:52 +00:00
Alexandru Gagniuc 23d3dfaa96 Correct wrong PCI ID for VIA K8M890 Chrome.
With the K8T800/M800 patch from r6367 the PCI IDs for the VIA chrome were
moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly.
(3220 instead of 3230). This patch defines the correct PCI ID for this device.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03 19:46:25 +00:00
Kerry She 3bf2708664 advansus/a785e-i mainboard enable warning as error
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03 10:14:56 +00:00
Kerry She 76d53b22d3 trivial remove blanks at the end of line
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-01 02:00:30 +00:00
Kerry She 991f880893 This patch fix a AMD sb800 wrapper compile warning:
src/southbridge/amd/cimx_wrapper/sb800/late
 call clear_ioapic but not include the prototype declare header file.

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-01 01:56:49 +00:00
Stefan Reinauer b2ecd81514 We don't have pausing versions of single-IO instructions.
Hence remove the wrong comment.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-23 22:48:13 +00:00
Stefan Reinauer 9cb175632d AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-23 22:43:43 +00:00
Jonathan Kollasch 4053e1412f Correct implementation of r6608.
(.align actually takes its argument in bytes)

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-23 17:55:20 +00:00
Jonathan Kollasch 6409a22586 Ensure ck804 romstrap is 16-byte aligned.
This alignment seems to be necessary for the chip to recognize it.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-22 15:39:25 +00:00
Scott Duplichan fb93178f13 Correct amd persimmon romstage code for early SPI prefetch enable.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-20 17:50:14 +00:00
Scott Duplichan 20aad25e6e Move the ACPI FACP table to the front of the RSDT list. This is done to work around a Windows XP or Server 2003 setup failure where an error message such as: "An unexpected error (805262864) occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c" occurs. This change updates AMD reference board projects, but could applied to others as well.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-20 00:06:09 +00:00
Peter Stuge 3f0075b3d2 cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-16 00:05:50 +00:00
Marc Jones 44d3c3dade Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 23:13:54 +00:00
Peter Stuge 16c8e37a2d agesa_wrapper: Avoid repetitive Kconfig depends, trivial
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:40:40 +00:00
Scott Duplichan 8c46263721 Cosmetic cleanup.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:10:15 +00:00
Scott Duplichan 5d878ad312 1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:09:09 +00:00
Scott Duplichan a64ab46b62 Update gpp port configuration.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:07:56 +00:00
Scott Duplichan 769527e523 Enable rom cache early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:06:09 +00:00
Scott Duplichan 3c639e7df8 Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:05:00 +00:00
Scott Duplichan 0b886ae3c3 Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:03:45 +00:00
Scott Duplichan dbbbca3f33 Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:02:27 +00:00
Scott Duplichan 0ebefd27c8 Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:00:23 +00:00
Scott Duplichan 254a6d6ea7 Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:59:19 +00:00
Scott Duplichan b7e068305c Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:56:03 +00:00
Scott Duplichan 2cc5f550c7 Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:54:04 +00:00
Scott Duplichan d9a634c756 Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:51:31 +00:00
Scott Duplichan e73fc20886 Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:48:22 +00:00
Scott Duplichan 9ab3c6c3a9 Build device paths for AP cores so that coreboot will report them to the OS.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:45:46 +00:00
Scott Duplichan be8fae1c71 Program the I/O APIC ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:41:00 +00:00
Scott Duplichan f191c72038 Enable AHCI mode and hide IDE controller to reduce boot time.
Note: enable AHCI in seabios and apply seabios patch:
http://www.mail-archive.com/seabios@seabios.org/msg00437.html

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:38:08 +00:00
Scott Duplichan dc312cca53 Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:26:04 +00:00
Scott Duplichan 2b9143afcc Fix ACPI shutdown function by removing reliance on SMI.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:19:54 +00:00
Scott Duplichan e78ae24eb1 Configure CIMx to use 33 MHz fast mode for SPD read.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:18:59 +00:00
Scott Duplichan 444c49c68c Match DIMM SPD addressing to implemented slots.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:13:00 +00:00
Scott Duplichan 6719c23a47 Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:11:41 +00:00
Scott Duplichan b0b4063d6a 1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:10:20 +00:00
Scott Duplichan 6f7375c24c 1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:07:43 +00:00
Scott Duplichan 6d6a456c9a Correct the number of MCA error reporting banks cleared.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:06:30 +00:00
Scott Duplichan a72425a7e6 1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
2) Remove coreboot variable MTRR initialization because AMD reference code handles it.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:01:42 +00:00
Josef Kellermann eb97e9688f siemens/sitemp_g1p1: Adapt read_option() to latest changes
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-13 06:25:16 +00:00
Patrick Georgi ceccd8dd67 Remove uart_init() in Siemens sitemp-g1p1
uart_init() was moved to common code in r6531, but I
missed that when integrating the new mainboard code.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-12 06:53:52 +00:00