Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9. This code is based on the output of autoport.
The file `data.vbt` matches the VBT in the latest version of the vendor
firmware (version 4601).
This board works well under coreboot. A list of what works and what
doesn't can be found in the documentation part of this commit. To
summarise: the only known issues are that S3 suspend/resume doesn't
work, and that there is no automatic fan control via the super I/O.
Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
By defining SUPERIO_KBC_PS2M, ACPI code is added to show the PS/2 mouse.
This has been tested on an ASUS P8H61-M LX with Linux 4.9.110 and
4.17.8. In each case, the PS/2 mouse works automatically, whereas it was
not detected before.
Change-Id: I7983f85b3fd23547950f1f75a81bbca63c63d52b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When compiling for the ASUS P8H61-M LX, IASL 20180531 emits the
following remark: "Control Method should be made Serialized (due to
creation of named objects within)". Making the appropriate methods
Serialized eliminates these remarks.
Change-Id: I8e95d9a00a629a2f904c79b78fac20810327ed37
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27796
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Exposing the parallel port via ACPI causes Linux to automatically detect
the parallel port and load the appropriate modules. Tested on an ASUS
P8H61-M LX with Linux 4.9.110 and 4.17.8.
However, no parallel port device has been tested.
Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Commit ef8c559e53
[nb/intel/sandybridge/report_platform: Move remaining code to sb folder]
moved reporting code to the southbridge, but missed a reference in the
non-default MRC raminit path (so testing missed it).
Remove invalid reference to fix compilation error.
Test: build google/link with MRC raminit option selected
Change-Id: I270a95ac53fbc9f8792f375908cf91585261f6a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The constant used in the ACPI code is NCT6776_SHOW_KBC, so update
the comments to reflect that.
Change-Id: I9ba69384866088f84a516557d76864104a024968
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
timer_monotonic_get() was only compiled in a !__PRE_RAM__ environment.
Clean up the code paths by employing CAR_GLOBAL for the global state
which allows the same code to be used in all stages.
Change-Id: I08fd1795508f76abdab1618585366bf9d06482ff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards require polling vs interrupts, so remove the IRQ definition to
prevent it being added to the SSDT device entry.
Test: Boot Linux on various auron and cyan variants, verify no error for
'TPM interrupt not working' present in kernel boot log.
Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to #574725, report Whiskey Lake CPUID, MCH device ID and
graphics device ID in bootblock stage.
BUG=N/A
TEST=Build and boot up whiskey lake rvp platform and check serial log to
see proper CPU/MCH/GFX/PCH got recognized.
Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
This patch makes sure we deassert the USB hub reset pin so the hub will
work with the next board revision that drops the external pull-up.
(Actual USB support comes in a later patch.)
Change-Id: I1efdc3594cfa3229891d42d445a21c1739170b79
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27790
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the required callbacks to read all strapping IDs on
Cheza.
Change-Id: I6437bbd03bdd00dfeedcafebabeb00b13588d052
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Check if an argument is given and if not print the usage.
Check if all arguments are handled by getopt and if not print the usage.
Change-Id: I40dbd2a51d018eb549e9b2fa4365b3e4f9355bff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
Check if all arguments are handled by getopt and if not print the usage.
Change-Id: Iccbb65ca768a62791af54afd9b7903495bc690af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Extracted from live running Thinkpad x1 carbon gen1 with vendor firmware.
Thanks to Igor Lee.
Change-Id: Id59517d9040c98e67a42fbce537f42f6b0c6db2d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: Igor Lee <getrun@gmail.com>
Reviewed-on: https://review.coreboot.org/27782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tuning of fan speed for different temperature values. Earlier while
running few benchmarks, fan was always getting on and starting at
higher speed. With this change fan will start with lower speed and
slowly speed gets increased if temperature continue going high.
Thermal team provided these data after fine tuning of fan speed.
BUG=None.
TEST=Verified on Nami running with different benchmarks and observed
fan speed.
Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a potential IMVP8 issue for KBL that affects Intersil VRs
Nami is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.
BUG=b:112081534
BRANCH=None
TEST=Build and boot Nami
Verify that suspend/resume and consecutive reboots are working
Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/27780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adapted from chromium commit adcb858
[cyan: Configure WLAN_CLKREQ as GPIO and always assert low]
This is a workaround for issue b/35648315 as proposed by Intel to
ensure that WLAN_CLKREQ always stays low.
BUG=b:35648315
Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1055652
Original-Reviewed-by: Rajat Jain <rajatja@chromium.org>
Original-Tested-by: Rajat Jain <rajatja@chromium.org>
Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from chromium commit 3750e09
[Strago: mark GpioInt() resources as PullDefault]
coreboot considers GPIO resources first-class citizens and initializes
all pads according to their intended use, with necessary pull settings
applied. Therefore let's use PullDefault as pull qualifier in AML,
letting the kernel know that it should not attempt to alter pull settings
when using GPIOs.
TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices.
Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/898259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27760
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adapted from chromium commit 126d352
[Strago: switch Touchpad and Touchscreen interrupts to be level-triggered]
The Elan and other touch controllers found in this device work much
more reliably if used with level-triggered interrupts rather than
edge-triggered.
TEST=Boot several cyan boards, verify that touchpad and touchscreen
work.
Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894689
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from chromium commit ee7a150
[Strago: do not hardcode virtual interrupt numbers]
Instead of hardcoding virtual interrupt numbers that may change as
the kernel changes, use GpioInt() resources to describe keyboard,
touchpad, and touchscreen interrupt lines.
TEST=Build and boot several cyan variant boards, verify keyboard,
touchpad and touchscreen work with newer kernels (4.14+).
Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894687
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Iecfb45be433249d274532eb746588483fedb3f52
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since this works on Yorp and Bip, we should enable EC SW sync for all
known boards so that it doesn't get forgotten.
BUG=None
TEST=None
Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27755
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduces new and required GPIO APIs, using common pinmux
definitions for GPIO configuration.
TEST=build & run
Change-Id: I8cef9dae2072da32cb0678efefeb8f0070cdde9c
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.
Test: boot various google/samsung boards, verify SSDT created with
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux
Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To install this hook, run
make install-git-commit-clangfmt
This will install a pre-commit-msg hook that runs clang-format
on all .c and .h files that are staged.
It will add a clang-formatted-by: <git username>
line to the commit message to indicate that clang-format
was run on the files and that further processing of them
is not needed.
Change-Id: I1773f55b5b4677dad8f4bea017b6328fd93df20c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27779
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This effectively means it is possible to run another bootblock located at
top_of_flash - 64K.
The i82801gx southbridge has the ability to swap the two top 64K ranges by
flipping the BUC.TS bit (RCBA[3414] bit0).
This allows coreboot to build roms with a bootblock at the top swap offset by
selecting CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK.
Change-Id: Id96e10aea3e5fd955d45287134eb8643be414de9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
src/arch/riscv/stages.c is an entry of romstage/ramstage, and does not
needs to be bootblock.
src/arch/riscv/id.S src/arch/riscv/id.ld is used to generate some
compile/board/time information, which is repeated with src/lib/version.c
Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27557
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2 bits of LPC host control were originally not public, and wrongly
identified as IMC related. Now that the bits are available in public BKDG,
fix the naming of the bits.
BUG=b:111912080
TEST=build and boot grunt.
Change-Id: I1921f46c6be54eda6329c98267cec27004caadd5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27744
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a function to overwrite AC/DC loadlines for differnt
projects.
BUG=b:111761175
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump
AC/DC loadline settings. Tested on Vayne and Akali.
Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch doesn't change the hash of a timeless build.
Change-Id: I5d329f65be0eee741fd330c0926881ff4f956624
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This patch contains the parts that changed the hash of the generated binary;
probably due to the compiler optimizing things slightly different.
Change-Id: Ide0b3296864e24edb646956e47221bfef8182e3d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27725
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the
resulting binary doesn't change with applying this commit.
Change-Id: I2b1dc8befa3381f3edac06704e31e7ef50f86fa4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27724
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pci ops happen to work on this struct device since the device_path is an union.
This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.
Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27242
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pci ops happen to work on this struct device since the device_path is an union.
This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.
Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27243
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pci ops happen to work on this struct device since the device_path is an union.
This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.
Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27245
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pci ops happen to work on this struct device since the device_path is an union.
This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.
Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27244
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specifically PCI device ID for graphics and PCI device ID for northbridge.
Change-Id: Ide237d3274df0543409c8a23b9bb50c8e0a6b7a3
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/27519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
These additions make a better fit to our style, they
are adapted from those done for Linux.
Change-Id: I664c9d1503e3bb7bedcd617e15d2d2c57e19bdff
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27752
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change f849972 (security/vboot: Enable TCPA log extension) enabled
support for adding TCPA log to CBMEM. However, if CBMEM is not online,
this function doesn't do anything and returns early. This condition is
not really a valid error condition as it depends on when the call to
tcpa_log_add_table_entry is made. Since tcpa_log_add_table_entry
returns -1 when cbmem is not online, tpm_extend_pcr prints an error
message with prefix "ERROR:". This can confuse any scripts trying to
catch errors in boot flow.
This CL makes the following changes:
1. Removes the print in tpm_extend_pcr since tcpa_log_add_table_entry
already prints out appropriate ERROR messages in case of failure to
add log entry.
2. Since the return value of tcpa_log_add_table_entry is not used
anymore, return type for tcpa_log_add_table_entry is changed to void.
BUG=b:112030232
Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This never got enabled for fleex; we should enable this to make it
easier to have updated EC firmware.
With this commit, here's the relevant console messages:
sync_one_ec: devidx=0 select_rw=4
update_ec: Updating RW(active)...
Trying to locate 'ecrw' in CBFS
update_ec: image len = 137580
EFS: EC is verifying updated image...
send_packet: CrosEC result code 1
EFS: EC doesn't support EFS_VERIFY command
vboot_hash_image: No valid hash (status=0 size=0). Compute one...
print_hash: RW(active) hash: 35ba735cf97dd990f6f7f0895264382aa20beb4e7ba57270b0a7b24686e26afd
Trying to locate 'ecrw.hash' in CBFS
sync_one_ec: jumping to EC-RW
send_packet: CrosEC result code 12
EC returned from reboot after 27753us
BUG=b:112038021
TEST=Successful boot after EC update via sync
Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add short explanation of Utility list
Change-Id: I5fc45ebe29cd42c1aa18c59dabc3ac3db3107bd7
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tristan Corrick