The flags used to compile libgcc may make it incompatible with the code it's
linked against, and/or the hardware it's going to run on. Rather than try to
tease the right libgcc from the compiler, lets just leave it out and use our
own implementations of the necessary functions.
Most of these implementations were taken from the Linux kernel, except for
uldivmod.S which was taken from a CL originally written for U-Boot by
Che-Liang Chiou in December of 2010. It was modified to not use the CLZ
instruction on machines that don't have it, anything earlier than ARMv5. The
top block was taken from an earlier version of the same CL which didn't use
CLZ in that spot. The later block was written from scratch.
BUG=None
TEST=Built and booted into the bootblock on nyan. Ran a series of tests which
divided and modded a 64 bit value by various 32 bit values which were powers
of 2. Confirmed that this function was used and that the returned value was
correct. Printed decimal and hex versions of some values and verified that
they equaled each other. Built and booted on pit with serial enabled.
BRANCH=None
Original-Change-Id: I7527e28af411b7aa7f94579be95a6b352a91a224
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/172401
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit be8c7a8f3292a7d7651b7c6dafc9a2c53afbd402)
*** This second patch is cherry-picked and squashed again to
*** pick up the libgcc changes that were skipped previously.
arm: Move libgcc assembly macros to arch/asm.h
libgcc/macros.h contains some useful assembly macros that are common in
Linux kernel code and facilitate things such as unified ARM/THUMB
assembly. This patch moves it to a more general place where it can be
used by other code as well.
BUG=None
TEST=Snow still boots.
Original-Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/182178
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit a780670def94a969829811fa8cf257f12b88f085)
*** Additional changes for stage specific builds
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie3e48f34ebf6fbe20c3dd76ecbcbea7844e9466e
Reviewed-on: http://review.coreboot.org/7322
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Do all the handling in SB code with few parameters from devicetree.cb
instead of having mobo callbacks.
Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7199
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Bring code inline to be consistent with the rest of coreboot.
See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase,
'expressions that refer to functions get converted to pointers to
those functions'
Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7290
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We already have these implemented under superio/common, use
those instead of this copy-paste syndrom.
Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7310
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We don't want segment for .car.data section to be considered while elf_to_stage
transformation is being done. Thus, use -S option for add-stage.
Change-Id: I04868c892e3aa94113189b012d284d52bacea5f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7305
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
That takes them out of .data
Change-Id: Idf88ddaacb2f78ba6a0260e3511b34edc269731d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7313
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Apply commit 283ba78415 to f12 (literally, plus one adaptation).
Change-Id: Ied7891806e269320caf968cae3de3dc792c5f8fd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7312
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Breaks abuild and is dependent on WIP, is WIP itself.
This reverts commit d7d0c81348.
Change-Id: I8b589b41632696aa4570abcceab5f3a3b0784649
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7319
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This is based on LENOVO X230 port. Board boots to linux via SATA.
Remaining Issues:
1. Native raminit sometimes fails with "timC write discovery failed"
even without changing the ram configuration.
I suggest altering the native raminit code so that it reboots
if that message appears to give a chance for the boot process to recover.
2. VGA does not work.
Native graphics initialization only supports LVDS and the
VGA Option ROM still hangs when run in SeaBIOS
3. USB does not work.
SeaBIOS/GRUB2 do not detect devices connected to USB ports
4. Sound needs corrected codec verb settings
Change-Id: Ib465a4824ef1a71ab6aa17bd40fc281215c6d44f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7020
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Super I/O manufactures have found new and innovative ways to enter
and exit out of LDN config in PNP config space.
Change-Id: Id3f5882664f1b2b18b49f32373430cf4b037ad22
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7308
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Rather than everyone writing their own adhoc device operation
NOP shim, we provide some formalism. We later make use of this
to reduce the loc count down trivially.
Change-Id: I2d04bfb50e76f367a0ee258dab97d7caa12ec99e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7283
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
On the ASRock E350M1 a Nuvoton NCT5572D is used as SuperIO-chip. The coreboot
port to this board however used the driver of the Winbond W83627HF SuperIO,
which is compatible enough to get most stuff working, but which clears bit 6 in
register 0x2B. This switches the function of pin 38 of the NCT5572D from
RSTOUT1# output to GP36. The PERST# pin of the ethernet chip and the
unpopulated miniPCIe slot are connected to this pin, so they didn't get reset
during a reboot.
Using the newly added driver for the Nuvoton NCT5572D fixes this problem.
There is also a trace from the pin 37 of the SuperIO, which can be configured
as RSTOUT2#, to pin 82 of the USB3-chip with unknown function.
As with the wrong driver, PS/2 keyboard and mouse do work in SeaBIOS and GRUB
but not in Linux.
Change-Id: I4bc78406afd3b0e10a1b04b561147e0ed94cc494
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/6266
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add support for both NCT6776D and NCT6776F devices.
Change-Id: If6686ea0a1cd6be537e286699b4ee8f88ba8ad7c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/5450
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Change-Id: I3b720cf879bf5326be885d2d3a3f9cfba0a27c7e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/6229
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Minnowboard Max was broken by
commit 454625c5 - intel/fsp_baytrail: Fix SMM/SMI
because TSEG wasn't set to 8MB by the FSP.
The default in the FSP is 1MB.
Change-Id: I2e671a6ca0240e931399920c62439c36133789aa
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7240
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Correct mask to select bits 4-6 inclusively as per comment and use
bitwise operations while working with bits. Be sure to write back out
the data on the retrain.
Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Found-by: Clang
Reviewed-on: http://review.coreboot.org/6147
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: I167d2c9ad3f690de41fee51dd7800ce76b328e41
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7231
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Currently clang/llvm builds are not fully supported. As such,
let us tone down treating errors as warnings until we actually
build the entire tree.
Change-Id: If7f90f9887e27250f5e6d73d1692505676be9d47
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7230
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: Id5c5d68048169b0cd400926cead2d1835194d1a5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: Ibbcdbb44c7586ac8d445870789647f8ff9585452
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7232
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
With following settings
1.Coreboot 25Mhz
2.Maxim codec configured with MCLK=25Mhz
2.I2C 400Khz fixed
4.Including Enable/Disable SHDN bit when LRCLK starts/Stops
5.Removed PLL toggle workaround routine.
audio playing is smooth before/after S3, no noise when recording so change
MCLK from 19.2 back to 25Mhz.
BUG=chrome-os-partner:26948
BRANCH=firmware-rambi-5216
TEST=test audio play and record on Rambi, works fine.
Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/193881
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7219
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
- The hotplug register doesn't work in the way we describe. Just leave
it at default.
- The backlight registers will be configured by the OS driver.
BUG=chrome-os-partner:27304
TEST=Manual on Rambi. Boot system in both dev and normal mode, verify
that display comes up. Also verify that display functions after warm
reboot and suspend / resume.
BRANCH=rambi+squawks
Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193830
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 3f287cc31e41fabef755c37361e2e65ca413c88c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7217
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
bit: 7 6 5 4 3 2 1 0
LFP2 EFP2 EFP3 CRT2 LFP EFP TV CRT
so int 15 0x5f35 need to return 0x8(LFP/eDP) instead of 0x2(TV).
BUG=chrome-os-partner:26365
BUG=chrome-os-partner:27505
BRANCH=rambi
TEST=Booted with and without HDMI connected monitor. DEV screen
always showed on eDP panel on Rambi.
Change-Id: I8f876e78383424f517689eb25e9229a27739957b
Original-Change-Id: I77edbeb3c86549f90302b4296b5a2f50313ca675
Signed-off-by: Kein Yuan <kein.yuan@intle.com>
Reviewed-on: https://chromium-review.googlesource.com/193303
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit dd375462147f182331f336ba826108e58b4e0a47)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7216
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Provide the option to embed MRC as an ELF file and not just
binary blob. This allows for MRC to be relocated.
BUG=chrome-os-partner:27654
BRANCH=rambi
TEST=Built and booted rambi.
Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192893
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 89c97d5e2023b8c5cc780e1b1d532d0a586512f9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7214
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Moving the cache-as-ram base address to 0xfe000000 will
provide more breathing room in the physical address space.
It will also allow for larger SPI roms in the future.
BUG=chrome-os-partner:27045
BRANCH=baytrail
CQ-DEPEND=CL:*157278
TEST=Built and booted. Suspended and resumes. Vboot works, MRC
settings are being saved as well.
Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190700
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 73c07a319d678f3e9be2fac64599c94f91c9ad9c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7212
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP
status.
BUG=chrome-os-partner:26777
TEST=Manual on Rambi with all patches in sequence:
`crossystem sw_wpsw_boot` prints 0
`flashrom --wp-enable` + reboot
`crossystem sw_wpsw_boot` prints 1
BRANCH=Rambi
Original-Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190097
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5bba447654417c42952c49542ed047b4867d04d1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I739cbb8fca5f02462cf78c81f9b364aabfd3fe86
Reviewed-on: http://review.coreboot.org/7211
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Ensure that the SMM build stage links properly using the compiler-rt
runtime under a Clang build.
Change-Id: Iead28c46d63f5bbb27757b7dc66fe06b4813d03c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6462
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Make use of '-print-librt-file-name' over '-print-libgcc-file-name'
to use Compiler-RT runtime glue over libgcc glue.
NOTE: *** Requires at least clang 3.6.x
Change-Id: I7f63284473d6067bf775409970c8dd98f5d5a8d5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6144
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Edward O'Callaghan