Commit Graph

11307 Commits

Author SHA1 Message Date
Patrick Rudolph 6f7ce9b217 intel raminit: fix timB high adjust calculation
Issue observed:
Any memory DIMM placed in channel0 slots stops at "c320c discovery failed".
The same memory DIMM works when placed in channel1 slots.

Test system:
 * Intel Pentium CPU G2130
 * Gigabyte GA-B75M-D3H
 * DIMMs:
  * elixir 1GB 1Rx8 PC3-10600U M2Y1G64CB88A5N
  * crucial 2GB 256Mx64 CT2566aBA160BJ
  * corsair 8GB CMZ16GX3M2A1866C9

Problem description:
In case of good timmings (all bits are set) an offset of 3*64 was applied.
The following test (c320c discovery) failed only on those byte-lanes.

Problem solution:
Don't modify timB in case of good timings measured.

Final testing result:
The system boots with every DIMM placed in channel 0 slots.

Change-Id: Iea426ea4470640ce254f16e958a395644ff1a55c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10889
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-13 01:59:43 +02:00
Patrick Rudolph 073b017bed intel raminit: whitespace fixes
Remove whitespace errors.

Change-Id: If69244a5d47424e3e984fdf782ea9d2d3c466d86
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10888
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-13 01:59:11 +02:00
Patrick Rudolph 03a88d3773 intel sandybridge: add VGA pci device id
Add VGA pci device id 0x0152 for Intel IvyBridge CPUs.

Test system:
* Intel Pentium CPU G2130
* Gigabyte GA-B75M-D3H

Change-Id: Ia546fdf0cc3bbd4c0ef6b5fd969232f105bceb22
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10798
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-13 01:58:29 +02:00
Martin Roth 46cf9f7b7a Verify Kconfigs symbols are not zero for hex and int type symbols
For hex and int type kconfig symbols, IS_ENABLED() doesn't work. Instead
check to make sure they're defined and not zero.  In some cases, zero
might be a valid value, but it didn't look like zero was valid in these
cases.

Change-Id: Ib51fb31b3babffbf25ed3ae4ed11a2dc9a4be709
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-12 19:06:44 +02:00
Martin Roth ba566bdc8b southbridge/amd/pi/hudson: Fix HUDSON_DISABLE_IMC kconfig warning
Platforms selecting the HUDSON_DISABLE_IMC symbol were showing the
warning:

warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
CPU_AMD_AGESA_BINARY_PI) selects HUDSON_DISABLE_IMC which has unmet
direct dependencies (SOUTHBRIDGE_AMD_PI_AVALON ||
SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN)

By moving the definition of the symbol outside of the if block
and removing the default n, we can get rid of the warning without
changing the value for any platform.

Change-Id: I5c1bdfbcf3c5c44ee05b8c5e679f6854d784d8dc
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10680
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-07-12 19:05:28 +02:00
Martin Roth 3a391fd20c x86emu/debug.h: remove #ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVEL
This protection didn't make sense to me - it seems like things would
probably break if printf wasn't defined anyway.

Change-Id: Ifb6bad46e193b35c13b7ad4946511fec74beff92
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-12 19:04:48 +02:00
Martin Roth c4e49f6262 Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()
Kconfigs symbols of type bool are always defined, and can be tested with
the IS_ENABLED() macro.

symbol type except string.

Change-Id: Ic4ba79f519ee2a53d39c10859bbfa9c32015b19d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-12 18:14:23 +02:00
Martin Roth d139c48a23 amd/.../hudson: Warn if HUDSON_FWM_POSITION is not inside CBFS
Display a warning if CONFIG_HUDSON_FWM_POSITION is not inside CBFS.

This can be extended to other Kconfig values for CBFS.

Change-Id: I2423f7b361dda8aac5dab409fa7b656de486f635
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10683
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-11 22:13:54 +02:00
Martin Roth d12d65fc54 Calculate HUDSON_FWM_POSITION and display warning on mismatch
This patch calculates the address where the chipset firmware descriptor
should be located and compares it against the actual value from Kconfig.
If the two don't match, it puts up a warning.

This could probably replace the config variable completely, but I wanted
to see how other people felt before doing that.  I seem to recall that
the value used to be calculated, so I figure that there must be a reason
it's done this way at this point.

If we do want to keep the Kconfig setting, this patch could also be
modified to just verify that the HUDSON_FWM_POSITION is inside the ROM
space.

Change-Id: I94addf463e2c694a94eef218ec855103a3bb5da5
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10682
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-11 22:13:25 +02:00
Martin Roth 16bc7e82d8 arch/x86/Makefile.inc: Calculate CBFS_BASE_ADDRESS variable
The CBFS_BASE_ADDRESS can be compared against values used with cbfstool
to generate warnings.  This can help cut down on mistakes and debug
time.

Change-Id: I149007dd637661f799a0f2cdb079d11df726ca86
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10681
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-11 22:12:00 +02:00
Aaron Durbin bd1499d338 timestamps: don't drop ramstage timestamps with EARLY_CBMEM_INIT
While running ramstage with the EARLY_CBMEM_INIT config the timestamp
cache was re-initialized and subsequently used. The result was that
the ramstage timestamps would be dropped from cbmem.  The reason
is that the ramstage timestamps perpetually lived in ramstage BSS
never getting sync'd back into cbmem. The fix is to honor the
cache state in ramstage in the timestamp_init() path.

Also, make cache_state a fixed bit width to allow for different
architectures across the pre-ramstage stages.

TEST=Used qemu-armv7 as a test harness with debugging info.

Change-Id: Ibb276e513278e81cb741b1e1f6dbd1e8051cc907
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10880
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-10 15:23:53 +02:00
Paul Menzel acf411d364 include/cbmem_id.h: Add name for `CBMEM_ID_TCPA_LOG`
Fix up commit f44ac13d (Add TCPA table.) by adding an entry for
`CBMEM_ID_TCPA_LOG` to the macro `CBMEM_ID_TO_NAME_TABLE`.

Currently, printing the CBMEM table of contents the name is missing.

	$ sudo cbmem -l
	CBMEM table of contents:
	    ID           START      LENGTH
	[…]
	 6. 54435041   c7fa8ff8   00010000
	[…]

Adding an entry and rebuilding the utility cbmem, the name `TCPA_LOG` is
shown.

	$ sudo cbmem -l
	CBMEM table of contents:
	    ID           START      LENGTH
	[…]
	 6. TCPA LOG     c7fa8ff8   00010000
	[…]

Change-Id: I089ea714349e07b322330bc11f723cc031c61c56
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10856
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-10 08:14:16 +02:00
Paul Menzel 6757267d6b include/cbmem_id.h: Sort `CBMEM_ID_TCPA_LOG` entry
Fix up commit f44ac13d (Add TCPA table.) by moving the entry to the
correct position so that all entries are sorted.

Change-Id: Ib68deb525a942051e1063ea2ec0a3e3b4a937024
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10855
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-10 08:13:50 +02:00
Lee Leahy 72dd90946f Braswell: Move the microcode into a subdirectory
Include the microcode files from the microcode subdirectory.

BRANCH=none
BUG=None
TEST=Build and run on cyan.

Change-Id: I4c8bf64d221d9ead18f1b7d6e1f01f61d88c9b25
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10873
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-07-10 02:11:47 +02:00
Lee Leahy 9a8e4f9f94 FSP 1.1: Update the CBFS image type
Update Makefile.inc to use the simplified CBFS image type.

BRANCH=none
BUG=None
TEST=Build and run on cyan

Change-Id: Ibb8413ab90b147e9d26d32639a8822c57ca54a46
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10871
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-07-10 02:11:27 +02:00
Stefan Reinauer db03c2259a arm: add __umoddi3() to libgcc implementation
Change-Id: Ida01506406d1d74211f0155a84c2b25dbaac5f1c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10860
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-09 00:31:39 +02:00
Stefan Reinauer a3f1a2e2bf rk3288: Fix & vs && mix up in hdmi driver
Change-Id: I54650671adaef3bc129c662d6e972474c869afaa
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10859
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-07-09 00:31:14 +02:00
Stefan Reinauer b538a69936 device: remove unused x86 include from common code
The include breaks compilation on ARM with clang.

Change-Id: I1ce0d58dbcbb8785c23739670c8c9574c329a81c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10858
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-07-09 00:30:56 +02:00
Stefan Reinauer 808f784db5 arm: enhance eabi compat functions
This fixes issues with our clang reference toolchain on ARM.

Change-Id: Ib754941059285f15332bc694814aff6285969545
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10857
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-07-09 00:30:41 +02:00
Vadim Bendebury 62b4de13c6 ipq8064: enable timestamp collection
One kilobyte of SRAM needs to be allocated and the feature enabled.

BRANCH=storm
BUG=chrome-os-partner:34161
TEST=timer error messages do not show up in the coreboot log any more

Change-Id: I1d5e5521bf9ae495d4f4f50ff017c846a8420719
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ffb9bfb0cdfab1391f8ae07669a2ab6b24d88dd7
Original-Change-Id: I60066672334db36f5e7adbef6794d7afd177d292
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/235893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10847
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09 00:11:37 +02:00
David Hendricks c55d839000 veyron_{brain,danger,mickey,romy}: Select PHYSICAL_REC_SWITCH
BUG=chrome-os-partner:42220
BRANCH=veyron
TEST=Used physical recovery button to enter dev mode on mickey

Change-Id: I78332f516b042be9c0cef6d8a59af44b670fc260
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fcd79a133dc750dffd5d23e0b84a109e7b7cb8d
Original-Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/283546
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09 00:10:05 +02:00
Furquan Shaikh 9761a7a295 smaug: Update PMIC settings
Update PMIC settings as per table provided by hardware eng team.

Change-Id: I17a8a1a44fa8c9093e13e8d7e4a2f5b07a3b1f1f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c49afd0d1a17b73f2192206ff7389e2f7930fec
Original-Change-Id: I027febb6849f1c4d15bf56d8bcd29c431655c7b6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/283543
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10843
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09 00:09:53 +02:00
Furquan Shaikh dc197619cd arm64: Print sp value when dumping registers for exception
BUG=None
BRANCH=None
TEST=Compiles successfully, sp verified during exception

Change-Id: Idbeb93b1dbf163e2d86cd42369941ff98a3d2d9e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca73b40f0248497143b6ab42bd0f5cc6cddf7713
Original-Change-Id: I38ee403200acb0e3d9015231c274568930b58987
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/283542
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10842
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09 00:09:40 +02:00
Yen Lin cad9e7a6ec t210: set CAR2PMC_CPU_ACK_WIDTH to 0
HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0.

BUG=None
BRANCH=None
TEST=Tested on Smaug; still boot to kernel

Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd
Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/282416
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10841
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09 00:09:16 +02:00
Yen Lin 13fb74927e t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to work
I2C6 controller needs SOR_SAFE and DPAUX1 clocks to work. These 2 clocks
are mistakenly enabled by MBIST. MBIST fix will be submitted next, which
will disable these 2 clocks as initial states. Enable these 2 clocks now
so I2C6 will continue to work after MBIST fix.

BUG=None
BRANCH=None
TEST=Tested on Smaug, make sure that panel shows display
     (I2C6 is used to turn on backlight)

Change-Id: Id47453e784d53fd6831e8d19a8d57c04c4e1f82f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 83e935f100be85e1e831a3f9f16962304f7cd7d6
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Change-Id: If312881c94570066bdc54f0f5c48226e862bddc6
Original-Reviewed-on: https://chromium-review.googlesource.com/282415
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10840
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09 00:09:08 +02:00
David Hendricks cc74221581 veyron_danger: Enable developer mode switch
Danger has a physical developer mode switch, it was just never
set up. This patch defines it, sets it up in fill_lb_gpios(),
and disables VIRTUAL_DEV_SWITCH.

Note: For now at least, dev mode is a bit wonky on Danger. It's
connected to both a DIP switch and a button. The button is normally
open, pulling dev mode high (defaulting to ON). The switch's "ON"
position will pull the value low, so we invert the value in coreboot
to see the expected behavior. Dev mode is enabled by holding the
button down during boot or by setting switch 2 in the DIP bank to
the ON position.

BUG=none
BRANCH=none
TEST=toggled dev switch on Danger and saw dev screen show up (or
not) as expected

Change-Id: I9369b96b6c9b54553d969b919ed663abdc704dd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dce53f1a31919f15f6e46c4a7d1c5ce541c2b318
Original-Change-Id: I737f165d7704e2f73375099367f012b365e3e77d
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280852
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09 00:08:59 +02:00
Patrick Georgi c88b8c24d9 vboot: Don't count boot attempts if lid is closed
This can be a problem with freshly updated devices that are periodically
powered on while closed (as explained in the bug report).

In this case, just don't count down. In case of actual errors (where we
want the system to fall back to the old code), this now means that the
retries have to happen with the lid open.

Bump vboot's submodule revision for the vboot-side support of this.

BUG=chromium:446945
TEST=to test the OS update side, follow the test protocol in
https://code.google.com/p/chromium/issues/detail?id=446945#c43
With a servo, it can be sped up using the EC console interface to start
the closed system - no need to wait 60min and plugging in power to get
to that state.

Change-Id: I0e39aadc52195fe53ee4a29a828ed9a40d28f5e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10851
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-08 19:40:24 +02:00
Lee Leahy d05a6c80c7 vendorcode/intel/edk2: Fix EFI_PEI_GRAPHICS_INFO_HOB structure
Change the FrameBufferSize field from UINT64 to UINT32 to match the
Platform Initialization 2.4 specification.

BRANCH=none
BUG=None
TEST=Build and run on cyan

Change-Id: I28dc0608675ed5840863ecd15bd2f57e6b2f4c1d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10834
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-08 17:46:07 +02:00
Lee Leahy 45980bd9f7 Braswell: Fix error in the warranty statement
Fix a cut and paste error in the warranty statement.

BRANCH=none
BUG=None
TEST=Build and run on cyan

Change-Id: If64b02f2c0fc2970932f23b99ad64beab5ab754e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10835
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-07-08 17:35:00 +02:00
Stefan Reinauer 8e3997552a memlayout: Add timestamp regions for t210 and cygnus
This is needed to make those SOCs compile with timestamps enabled.

Change-Id: Iac20cb9911e1c76a18c8530385c9d7b8b46399e5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10833
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-07-08 08:08:42 +02:00
Stefan Reinauer 9eb6180963 stddef.h: Disable check_member() macro when compiling with CLANG
CLANG assumes that _Static_assert() is a C++11 only feature and
errs out when encountering the check_member macro complaining about
a reinterpret_cast.

Change-Id: Id8c6b47b4f5716e6184aec9e0bc4b0e1c7aaf17c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10827
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-07-07 23:30:31 +02:00
Stefan Reinauer 0fa5d8f219 payloads: Reorganize Makefile.incs for external payloads
This is not going as far as I would like it to go, but
some of the external payloads have to be fixed up first.
Long term, I would like to  directly add payloads/external/*
to subdirs-y and remove one layer of indirection from the
build process.

For now, moving the payload Makefile targets into payloads/
is already a small improvement.

Change-Id: Ie4eb492eb804e0aaaf1a4d90af2f876f27a32a75
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10829
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07 22:50:15 +02:00
Stefan Reinauer 1a8b7bfe50 payloads: Reorganize Kconfig for external payloads
The integration of external payloads in coreboot
is a bit messy. You have to change the to level Kconfig
file for every payload (something that we recently fixed
for mainboards and chipsets). This means that updating
e.g. the SeaBIOS version requires a change outside of the
SeaBIOS directory.

With this patch you can create a new directory under
payloads/external and place a Kconfig and Kconfig.name
file in there, and the payload will automatically show
up when you do "make menuconfig".

Change-Id: I293abcb8eae581d4b3934e64897c0d339a27e7c1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10828
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07 22:49:47 +02:00
Aaron Durbin 06f1f8fed6 timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS
Empty functions are provided when !CONFIG_COLLECT_TIMESTAMPS
so stop guarding the compilation.

BUG=None
BRANCH=None
TEST=Built

Original-Change-Id: Ib0f23e1204e048a9b928568da02e9661f6aa0a35
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228190
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>

(cherry picked from commit 9aa69fd43d77f5f7acdc9f361016c595dd16104e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I14418c8ef3ccb57ac6fce05b422e1c21b1d38392
Reviewed-on: http://review.coreboot.org/10742
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-07 20:07:49 +02:00
Patrick Georgi 3957ddc414 marvel/bg4cd: move timestamp init to SoC code
No need to repeat this in the mainboard code (even if there's only one right
now).

Change-Id: Iaa3508c27f8c38cfa343ab1d8a094ce922dec157
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/10825
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-07-07 20:07:41 +02:00
Aaron Durbin 1936f6cf25 timestamp: add generic cache region
In order to accommodate tracking timestamps in all the
__PRE_RAM__ stages (bootblock, verstage, romstage, etc)
of a platform one needs to provide a way to specify
a persistent region of SRAM or cache-as-ram to store
the timestamps until cbmem comes online. Provide that
infrastructure.

Based on original patches from chromium.org:
Original-Change-Id: I4d78653c0595523eeeb02115423e7fecceea5e1e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223348
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>

Original-Change-Id: Ie5ffda3112d626068bd1904afcc5a09bc4916d16
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/224024
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>

Change-Id: I8779526136e89ae61a6f177ce5c74a6530469ae1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10790
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-07-07 20:07:27 +02:00
Furquan Shaikh d17a8623a5 rk3288: Use timestamp region for pre-cbmem timestamps
BUG=None
BRANCH=None
TEST=Compiles successfully for veyron_pinky

Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/227243
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>

(cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7
Reviewed-on: http://review.coreboot.org/10740
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-07-07 20:07:13 +02:00
Furquan Shaikh 8e584aed2a t132: Add timestamp collection support in t132
Add a region TIMESTAMP to store all the timestamps starting from bootblock to
end of romstage. At the end of romstage take all the timestamps in TIMESTAMP
region and put it into cbmem

BUG=chrome-os-partner:32973
BRANCH=None
TEST=Compiles successfully and cbmem -t prints all timestamps

Original-Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223110
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>

(cherry picked from commit b8ccf5731df9ca149a2a0661362e7745515bfe5e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I266e46ed691ebe5f0a20ed28b89e6e74399487a1
Reviewed-on: http://review.coreboot.org/10736
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-07-07 20:05:09 +02:00
Marc Jones ac630f7070 x86 makefile: Use preprocessed linker files
The top level Makefile runs the $stage-src .ld scripts through
the preprocessor and puts them in $(obj). Use the preprocessed
.ld files and cat them together into x86 romstage_null.ld.

Change-Id: If71240fbf7231df2b1333a1f8e5160cb8694f6ce
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10743
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-07 20:04:55 +02:00
Patrick Georgi 10ef872cdb smbios: fix copy&paste error
While extending the SMBIOS code to write a proper maximum structure size,
the call to elog_smbios_write_type15() was botched.
Fix the name and arguments.

Change-Id: I4c93490b09ddf4da240ff8f2bd8f8cc3f2abd96e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10823
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-07 19:07:08 +02:00
Stefan Reinauer 4a45ec43fe x86: Drop -Wa,--divide
Fix up all the code that is using / to use >> for divisions instead.

Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10819
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-07 18:30:55 +02:00
Stefan Reinauer 4c8fa2aad2 Unconditionally compile romstage with -Wa,--divide
The option --divide is required by our assembler to ensure that
'/' is not parsed as a comment sign but as a division, because
some of the cache as ram code is using divisions.

The --divide parameter has been part of the GNU as since binutils 2.17.
Hence, compile romstage (which contains cache as ram init) with
-Wa,--divide unconditionally instead of probing for it and adding it to
all compiler invocations (because that is causing random trouble with
clang when compiling the SMM code and calling gcc with --divide instead of
-Wa,--divide)

Change-Id: Ideefb2a243dc1d657ba415a99c1f8ab1d93800e0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10817
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07 17:40:09 +02:00
Tom Warren faa76f5548 T210: UTMIP: Correct UTMIP PLL programming as per Mark Kuo
BUG=chrome-os-partner:39603
BRANCH=none
TEST=Built OK for Smaug.

Change-Id: Iba170d8ad6f1dff111421fd61f71da19de57efaa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1bf1c1442dacf45bac5d55b05ada99a2c96f2e45
Original-Change-Id: Iecf04691a637b56e2f2287ab7d4d0cdda0382421
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/282720
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-on: http://review.coreboot.org/10814
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-07 17:21:53 +02:00
Stefan Reinauer fd5398fcdd amd/lamar: drop unused value from mainboard_intr_data[]
This value is overwritten in the next line.

Change-Id: I622c35b8d78f6b01f2532dd8b40db15b2e888f58
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07 17:12:39 +02:00
Jonathan A. Kollasch a660bc1921 mainboard/msi/ms7135: remove bogus MADT IRQ override for timer
Stops Linux from complaining:

[0.097286] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
[0.100005] ..MP-BIOS bug: 8254 timer not connected to IO-APIC
[0.100005] ...trying to set up timer (IRQ0) through the 8259A ...
[0.100005] ..... (found apic 0 pin 0) ...
[0.143507] ....... works.

Change-Id: Ic09a6940f80e3da2c1f3c0ef04fb50a4096b7943
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10642
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07 16:02:17 +02:00
Ben Frisch 72af5d79f9 smbios: Calculate SMBIOS Max Struct size
The SMBIOS Specification 2.3 and up defines Maximum Structure Size
as the "Size of the largest SMBIOS structure, in bytes, and encompasses
the structure’s formatted area and text strings." The hardcoded size
is too small to accurately represent the maximum SMBIOS structure sizes.
While the field is not used by Linux it is used by some RTOS
implementations, eg. VxWorks.

TEST=Booted Linux and ran github.com/bfrisch/dmidecode which verified
the maximum structure size on Minnowboard Max.
Change-Id: I98087975c53a02857742dea283f4e303485b2ffe
Signed-off-by: Ben Frisch <bfrisch@gmail.com>
Reviewed-on: http://review.coreboot.org/10163
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07 08:23:33 +02:00
Alexander Couzens f6dde95e87 ec/lenovo/h8: silence sound on boot
Fix a bug when a sound was generated while going into suspend.
E.g. When a low battery sound is played while going into suspend
a sample is stuck in this register. The user will hear a sample forever.

Change-Id: I103a5f462c8044ef5875a9adf812234b5e6960ac
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/10297
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-07 02:40:50 +02:00
Patrick Georgi 49a8c8a3ad sandybridge: provide monotonic timer function
This fixes building the ELOG_GSMI feature by using the TSC as time source for
the flash drivers.

It's not the most precise clock, but should be good enough for the purpose.

Change-Id: I2d416c34268236228300a9e868628c35e22bf40c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10813
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-07 02:35:52 +02:00
Timothy Pearson 066980cd32 cpu/amd/model_10xxx: Determine single-link status of each CPU in _PSD generator
The prior ACPI _PSD generator committed in ef33db01 incorrectly assumed the active
link count of each processor was identical.  Detect the link count on each node
when generating the _PSD objects.

Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf9b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10158
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-07 01:42:51 +02:00
Timothy Pearson fb39f82116 cpu/amd/car: Move AP stacks below the BSP stack to free up space
Caching SPD data during startup requires additional CAR space.
There was a large chunk of free space between the AP stack top and
the BSP stack bottom; moving the AP stacks below the BSP stack
allows this space to be utilized.

TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores)
and 120k of CAR.

Change-Id: I370ff368affde7061d6547527bda058b9016e977
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10404
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-07 01:41:59 +02:00
Timothy Pearson a97e0075a2 cpu/amd/car: Increase Family 10h CAR size limit to 128k
This resolves issues with 4-node (32-core) systems not having
sufficient CAR memory available to boot.

TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores)
and 120k of CAR.

Change-Id: Ie884556edc5c85c2c908a8c6640eeec11594ba3a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10402
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-07 01:41:33 +02:00
Timothy Pearson b5e465522e cpu/amd: Detect any conflicts between sysinfo and the stack region
When increasing the number of supported CPUs on AMD Family 10h/15h
systems there is a relatively high chance of causing a collision
between the CAR global variable region and the AP stack space.
Such collision was noted when increasing the number of supported
CPUs to 32 on the ASUS KGPE-D16.

Detect collision at runtime and print a warning if collision is
present.

Change-Id: Ib5c32f868b1dfffb3b840bb1b1df5f55b5a25f8d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10401
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-07 01:40:43 +02:00
Timothy Pearson 46b2271ea4 northbridge/amd/amdfam10: Remove array to null comparison
The address of array 'sysinfo->DCTstatA' will always evaluate to 'true'.
Remove checking the base pointer of an array for validity.

Found-by: Coverity (CID 1293135: Incorrect expression)
Found-by: Clang (Wpointer-bool-conversion)

Change-Id: I99c9c9f1564dfb997c60b2a895d664e3b06c117b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9596
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-07 01:38:17 +02:00
Patrick Georgi 5a2bd0b693 Revert "sandy/ivybridge: use LAPIC timer in SMM"
This reverts commit a3aa8da2ac.

Chrome OS builds require the monotonic timer API in SMM for ELOG_GSMI,
but sandy/ivy doesn't provide it. The commit tried to work around that
by using generic LAPIC code instead, but this leads to multiple
definition errors in other configurations (and it may be unreliable once
the OS reconfigured the APIC timers anyhow).

This fixes the situation for the non-ELOG_GSMI case (which is more or
less everybody but Chrome OS). ELOG_GSMI requires a separate fix.

Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10811
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-06 22:13:07 +02:00
Lee Leahy acb9c0b661 Braswell: Update to end of June.
Remove some CamelCase in acpi.c
Add FSP PcdDvfsEnable configuration parameter.
Add lpc_init and lpc_set_low_power routines.
Remove Braswell reference to make code easier to port to another SOC.

BRANCH=none
BUG=None
TEST=Build and run on cyan

Change-Id: I5063215fc5d19b4a07f3161f76bf3d58e30f6f02
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10768
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 18:45:23 +02:00
Lee Leahy 2bc9cee0f7 Braswell: Update the ACPI tables
Build the GNVS pointer and add it to the DSDT.
Add the opregion for GOP support.
Build the SSDT entry and add it to the RSDP.
The arch/x86/boot/acpi.c module adds the HPET entry, remove the
acpi_create_intel_hpet routine.

BRANCH=none
BUG=None
TEST=Build and run on cyan

Change-Id: I8c7ae36b24da583928ad2532f611a855268b51f9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10748
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 18:44:38 +02:00
David Hendricks 1f440f60fb veyron*: Kill SKIP_DISPLAY_INIT_HACK
Now that we have functioning display code for all platforms,
we can just get rid of this ugly hack used on non-Chromebook
veyrons.

BUG=none
BRANCH=none
TEST=built for Brain, Rialto, Mickey, Romy

Change-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5
Original-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282049
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10785
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-06 09:42:53 +02:00
David Hendricks cd500134b1 veyron_rialto: Use VOP_MODE_NONE for display init.
This uses VOP_MODE_NONE for display init on veyron_rialto and
adds a mainboard_power_on_backlight() stub so that we can finally
get rid of SKIP_DISPLAY_INIT_HACK.

BUG=none
BRANCH=none
TEST=built for veyron_rialto

Change-Id: Ia6b420a962fe266e773c804b8e5c68da35848753
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a290c938c163759a3672c07d8ec7c0a38057b13d
Original-Change-Id: Iec2d7f03857198a4d6f7490db1e3e19c74f18c43
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282048
Reviewed-on: http://review.coreboot.org/10784
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:42:38 +02:00
Furquan Shaikh 5bcf8d637b t210: MTC cleanup
1. Correct MTC weak function definitions.
2. Correct MTC message in case no training data is present.

BUG=None
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on smaug.

Change-Id: Iba3c994982da947af3fbd2d7e9a06dff7947f2b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce9a4cd7d824acd0da5615b33319869f6cf1cd56
Original-Change-Id: I037439246709c8ec0ec7f12ea109cbe0ae1073ae
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/278027
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10780
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2015-07-06 09:41:23 +02:00
David Hendricks cc828514ce rk3288: Add VOP_MODE_NONE for headless devices
BUG=none
BRANCH=none
TEST=built w/ follow-up rialto patch

Change-Id: I166c75673c199e8c6860f601db6759cdc3cb9c96
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ba0e0b639f12654ec54216d4366c688baa5b3253
Original-Change-Id: Id21c87ace2f4d381a1e374e1d5fe15cf1cd96da0
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282047
Reviewed-on: http://review.coreboot.org/10779
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:41:10 +02:00
David Hendricks 51e73c3f6e veyron_brain: Add basic HDMI support
This adds a configure_hdmi() function that drives the HDMI
enable output high and configures the iomux. Calls to PMIC
functions to enable HDMI power are moved here as well.

BUG=none
BRANCH=none
TEST=with follow-up patches, we now get a dev screen on Brain.

Change-Id: Ifd2648376c789fb29c9e2e4ab6bdb10ca439e4a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91ec6a96edaf2042236aee0383e18715014f1013
Original-Change-Id: I0c6e9f8fc5e06f53a1a160d8ab2e32447168139e
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282046
Reviewed-on: http://review.coreboot.org/10778
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-06 09:40:49 +02:00
Julius Werner d8086876a7 lzma: Return correct amount of decompressed bytes
The LZMA functions are supposed to return the decompressed size, but
what they actually return is just an unaltered field from the LZMA
header that is *supposed* to contain the decompressed size. Apparently
some encoders just overshoot that for no good reason. This patch changes
the code such that the actual amount of decompressed bytes is returned.

BRANCH=smaug
BUG=None
TEST=Printed output bytes when decompressing kernels with LZMA in
depthcharge, noted that amounts now make sense.

Change-Id: Icdd8f782aa87841f770eff4c14a08973530c7446
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24b2fa8c9a342ca4288dad1430c8965395f00263
Original-Change-Id: Ib4cf8673846aedd34656e594ce7b8ea875b56099
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282742
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10777
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:40:37 +02:00
David Hendricks e6883a3d9b veyron_*: Set vop_mode in devicetree.cb files
This avoids any ambiguity or breakage in case the vop_modes get
shuffled around or changed in some future patch or copy+paste job.

Brain and Rialto need some more work done so their devicetree.cb
files will be updated in follow-up patches.

BUG=none
BRANCH=none
TEST=compiled only (for danger, jerry, mickey, romy, speedy)

Change-Id: I4fd549c82c8a5c31525c4e485fa8df73f33f2049
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd88973b53949058331613c7582650fbd4ea48db
Original-Change-Id: I47da45c5fd9648544392de8d76f86af812de9093
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282610
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10776
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:40:23 +02:00
David Hendricks af42f069ea rk3288: Auto-detect display.
We currently select either HDMI or EDP (default). This patch
allows us to use HDMI as a fallback for devices that may have
a display connected on either interface. It also renames the
enums to sound a little more sensible in other contexts (more
on that in the follow-up patches).

VOP_MODE_AUTO is added to the mode enum which will make it explicit
that a board can support either. In AUTO_MODE we will try EDP first
and then fallback to HDMI. Other modes can be set to force a certain
behavior such as HDMI-only on Mickey where it doesn't make sense to
try EDP.

A follow-up patch will add logic for when we explicitly don't want
to probe for any display (headless devices).

BUG=none
BRANCH=none
TEST=On veyron_danger, connected EDP and HDMI displays and saw dev
mode screen appear on EDP display. Unplugged EDP and then dev mode
screen showed up on HDMI.

Change-Id: I22b38031c4ab3d79fbb182f7a906da1197f35543
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3f57ed3758c4e516d9fd226ad9499b102b81b423
Original-Change-Id: I352dcde16f7f3ebbf5796852b685685e541eb794
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/281076
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10775
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:40:14 +02:00
huang lin c2b48e55f1 rockchip: rk3288: correct ddr 300MHz clock setting
CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz
setting can't meet this request, so modify it

BRANCH=None
BUG=None
TEST=Set ddr frequency to 300MHz and boot from mickey

Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5
Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/282445
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:39:38 +02:00
David Hendricks a1e5a7761a veyron_danger: EDP changes for v2
EDP-related hardware modifications for v2:
- BL_EN moved from GPIO7_A3 to GPIO7_A2
- EDP_HPD added to GPIO7_B3

BUG=none
BRANCH=none
TEST=built and booted Danger v2 with EDP panel attached, saw dev
mode screen come up

Change-Id: I47383610082b371a612aced656e56f1bd1cfa098
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b
Original-Reviewed-on: https://chromium-review.googlesource.com/280855
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:39:25 +02:00
Jonathan A. Kollasch 2c2e05ad79 nvidia/l1_2pvv: whitespace: remove spaces that are followed by tab
Change-Id: Ia84df2f4467e102fd5f675dba6432996584d78c1
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10796
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-07-05 04:32:23 +02:00
Martin Roth df02c338ef Kconfig: Fix references to obsolete symbols
These are all Kconfig symbols that have been removed or renamed.

USE_PRINTK_IN_CAR was removed in commit 8c4f31b3
Drop the USE_PRINTK_IN_CAR option. It's a bogus decision...

DYNAMIC_CBMEM was removed in commit e2b0affd
Remove Kconfig variable that has no effect

MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc
Remove Kconfig variable that has no effect

CACHE_ROM was removed in commit 4337020b
Remove CACHE_ROM.

SMM_MODULES was removed in commit 44cbe10f
smm: Merge configs SMM_MODULES and SMM_TSEG

INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218
soc/fsp_baytrail: Fix use of microcode-related Kconfig variables

CAR_MIGRATION was removed in commit cbf5bdfe
CBMEM: Always select CAR_MIGRATION

REQUIRES_BLOB was removed in commit 70c85eab
build system: Retire REQUIRES_BLOB

CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit
66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS

CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b
uart: Redefine Kconfig options

CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit
afa7b13b - uart: Redefine Kconfig options

Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10766
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-04 23:41:05 +02:00
Patrick Rudolph 8c2f39714f intel raminit: rename register
Found while doing code review.

Rename reg_4004_b30 to cmd_stretch.
Found in 4th-gen-core-family-desktop-vol-2-datasheet.pdf chapter 4.2.1.

Change-Id: Ib07059625ed458332708562e836803f2b587d5d8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10789
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-04 23:40:22 +02:00
Kimarie Hoot caa599507f hp/pavilion_m6_1035dx: Remove 'select USBDEBUG_IN_ROMSTAGE'
Since USBDEBUG is not selected by this platform, there is no
benefit to selecting USBDEBUG_IN_ROMSTAGE in the mainboard
Kconfig.  Further, using a 'select' for USBDEBUG_IN_ROMSTAGE
prevents the value from being modified by a user in menuconfig.

Change-Id: I67b71a724a8614882cff4bb43b042f0c092d11d2
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/10671
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-03 22:34:33 +02:00
Martin Roth 45895f1e7d Kconfig whitespace cleanup: Change leading spaces to tabs
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10764
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03 22:30:10 +02:00
Stefan Reinauer 2ba16dbd99 storm: Enable DRIVER_UART since we use CONSOLE_CBMEM_DUMP_TO_UART
This fixes the build with CONSOLE_CBMEM_DUMP_TO_UART.

Change-Id: Ibe79239c5799a5c4a08ed195fce4d0c63d629ca4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10769
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03 19:38:09 +02:00
Stefan Reinauer 417f16bc75 tegra124: verified boot fixups
This patch fixes up verified boot (vboot2) configuration of all
tegra 124 bases boards in the tree.

Change-Id: I81f2e83821cbfdbe2a55095543e7447efdde494e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10761
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-02 19:56:18 +02:00
Stefan Reinauer a3aa8da2ac sandy/ivybridge: use LAPIC timer in SMM
This fixes an issue with using the flash driver in SMM for writing
the event log through an SMM call.

Change-Id: If18c77634cca4563f770f09b0f0797ece24308ce
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10762
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-02 08:34:40 +02:00
Stefan Reinauer cdf8ee6071 purin: chromeos.c also needed in romstage
Otherwise the Chrome OS build won't succeed.

Change-Id: Idf93a09f53d08b6c201f1de140f0fff35f928dcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10760
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-07-02 03:01:24 +02:00
Stefan Reinauer cecabc19a5 ME/IFD binaries: Implement sane defaults for file paths
Change-Id: I81298aca07c18359e8e4bf5b2d8926d6b45a30c5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10763
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-02 03:01:00 +02:00
Martin Roth 57eff2a192 ifdfake: Add prompts and help for the regions in Kconfig
Update the ifdfake region questions in Kconfig with help descriptions
and prompts to allow values to be entered and not just use pre-defined
default values.

Change-Id: Ifdffadc3d74ec49492c2ded66623a1be6945425f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10649
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:26:45 +02:00
Martin Roth 775d50828e Intel Firmware Descriptor: Add Lock ME Kconfig question
Add the Kconfig question to allow the user to lock the ME section
using ifdtool.

Change-Id: I46018c3bc9df3e309aa3083d693cbebf00e18062
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:26:21 +02:00
Martin Roth c407cb97bc Move baytrail & fsp_baytrail to the common IFD interface.
- Add the common/firmware subdir to the baytrail & fsp_baytrail
makefiles and remove the code it replaces.
- Update baytrail & fsp_baytrail Kconfigs to use the common code.
- Update the IFD Kconfig help and prompts for the TXE vs ME.
- Whittle away at the CBFS_SIZE defaults.  All the fsp_baytrail
platforms have their own defaults.

Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10647
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:21:33 +02:00
Martin Roth c528c2e3e9 Intel Firmware Descriptor Kconfig: remove USES_INTEL_ME
When I added the common IFD Kconfig and Makefile, My thinking was that
I could use this symbol to differentiate between the ME and the TXE,
and to exclude the ME questions from platforms that use the IFD, but
don't use an ME, like Rangeley.  In practice this made things a lot
more complicated and isn't worth it.

Change-Id: I4428744e53c6bb7fc00a4fa4f0aa782c25fc9013
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10678
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:17:27 +02:00
Stefan Reinauer ca7794854c tegra132: adjust vboot2 memlayout to make coreboot compile
romstage didn't fit in it's region anymore.

Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10759
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-07-01 23:37:11 +02:00
Patrick Georgi 0232549621 google/veyron_minnie: Add new board
Copied from speedy, with changes to mainboard.c (and speedy -> minnie renames
across the directory)

Change-Id: Ib38f0b15da8306984869e7ee7b4ddf366b0df82c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10757
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-07-01 23:05:28 +02:00
Patrick Georgi ec88681ca3 nvidia/tegra210: Drop unused Kconfig symbol
The deleted symbols aren't used anywhere in the coreboot tree and come from
the downstream chromeos-2013.04 branch.

Change-Id: I0ebc2936dff400cf8fe68794c86ac583aba2a14b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01 22:03:39 +02:00
Patrick Georgi 6a02b3b3e4 linker scripts: Fix symbol handling for pre-RAM cbmem console
Some ld versions (eg. the one used in the chromium build system) mis-handled
the redefined symbol in romstage.ld, so use the feature that exists for
precisely that purpose.

Change-Id: I184310ab20a02f6b3d569798448eac78b13e88a3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10754
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01 22:03:21 +02:00
Patrick Georgi 20864c1d6d rockchip/rk3288: Initialize CPU in bootblock
Some basic MMU setup is required to allow unaligned memory accesses that
happen across our entire codebase.

Change-Id: If5a84e19a7a3e47d6009fd073b1323dfb25e6a06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10753
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-07-01 21:43:39 +02:00
Stefan Reinauer d0ed7eef74 tegra210: Include correct include files
Some include files were unnecessary, and program_loading.h
was missing.

Change-Id: Ief3d970af5fbbb6b79da06ba3ea1d8613bfc314f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10749
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-07-01 20:18:21 +02:00
Patrick Georgi d13fd1b013 nvidia/tegra210: reserve more room for the romstage in vboot builds
Change-Id: I11c2e270179c54af8687435ff662a509ac714505
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10733
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 22:13:04 +02:00
Patrick Georgi e3fe4e7572 google/foster: roll up fixes to compile with vboot
Change-Id: I796e0fa64f9a858a54b09a82fbec1f0576e7e124
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10732
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 22:06:45 +02:00
Patrick Georgi 84a124de6b google/smaug: roll up fixes to compile with vboot
Change-Id: I256410ff6c0107bbbaaf49b909d63ca61e88a22c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10731
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 22:06:42 +02:00
Patrick Georgi 4d6ad838e7 google/smaug: add new mainboard
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.

Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:47:22 +02:00
Patrick Georgi fd49d6faf9 google/foster: add new mainboard
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.

Change-Id: I8630e86a4b0e8756693f8989ce147d6d762cefe1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:47:12 +02:00
Patrick Georgi 40a3e321d4 nvidia/tegra210: add new SoC
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.

Change-Id: I81853434600390d643160fe57554495b2bfe60ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:43:01 +02:00
Patrick Georgi 7f641e68f2 google/peach_pit: disable Chrome OS support
The Exynos SoC code and vboot really don't get along and things are not even
in a good shape in Chrome OS' top of tree. Disable but don't rip out the
support functions, so it could be revived.

Change-Id: I982c5a3731b527fd1f1579e9de353819da656452
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10730
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:35:00 +02:00
Patrick Georgi 3756de0762 google/nyan: remove timestamp leftovers from upstreaming
Initializing timestamps and writing the "start romstage" timestamp already
happens earlier.
One question to sort out is what to do about the migration into cbmem, but at
least this compiles again.

Change-Id: Ie8a0b7998c6c9da71f036857987f3c781385034f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:34:39 +02:00
Patrick Georgi 78390f1303 drivers/i2c/tpm: move tpm driver around a bit more.
The many different places to put vboot support in can be confusing.
Instead of using libverstage (which isn't enough since those functions are
sometimes called outside that, too), mention all stages where it can resides
explicitly.

Change-Id: Idddb9f5e2ef7bcc273f429d9f432bd37b4573567
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10728
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:34:19 +02:00
Patrick Georgi 2f31ef1115 google/link: implement get_write_protect_state
Current vboot wants that function.

Change-Id: I9d3a592c448cf2af10f76cae4518341cbc0a6f41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:34:05 +02:00
Patrick Georgi 94b8ad4879 samsung/stumpy: implement get_write_protect_state
Current vboot wants that function.

Change-Id: Ie3b49aa716d9711223ec71a142878e847eedfe4e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:33:48 +02:00
Patrick Georgi 961e8a46af samsung/lumpy: implement get_write_protect_state
Current vboot wants that function.

Change-Id: I08590739112a7fcce7a983b6d77ff500692ef7d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10725
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:33:36 +02:00
Patrick Georgi 03decc0c5e intel/sandybridge: initialize variable
Otherwise cache_base may be uninitialized.

Change-Id: Ie91f9567cea24114723a5362f52052d6ec22a6b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10724
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:33:27 +02:00
Patrick Georgi ea31f63336 google/jecht: Fix compiling GPIO table code
A lot changed here between Chrome OS and upstream, and these changes are
needed to reflect that.

Change-Id: I7195861465388d0f6a7cb540ebf4e410e38c260a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10723
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:33:05 +02:00
Patrick Georgi b5e2090370 vboot: move vbnv_* sources around a bit more.
The many different places to put vboot verification in can be confusing.
Instead of using libverstage (which isn't enough since those functions are
sometimes called outside that, too), mention all stages where it can resides
explicitly.

Change-Id: I9360face822ada7018a1cfdfced8da29b347cbb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10722
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:32:57 +02:00
Patrick Georgi e1b832772d lib: add delay.c to bootblock if I2C_TPM driver is enabled
Change-Id: I752fcc3b8687e4f861c3977322ebb6439f14fac4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10708
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:19:50 +02:00
Patrick Georgi 091b4ae7de drivers/i2c/tpm: push tpm driver from verstage to libverstage
That way it's available wherever the verstage code ends up, bootblock,
verstage or romstage.

Change-Id: I0665e297f199acd60cff93e1b39812f183115d33
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10707
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:19:36 +02:00
Patrick Georgi 5f2055d0d9 chromeos: push vbnv_* accessors from verstage to libverstage
That way they're available wherever the verstage code ends up, bootblock,
verstage or romstage.

Change-Id: I6e59a40761f95a98d96a9b72e3bbcc59caae9b1a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:19:26 +02:00
Patrick Georgi f73f06cb73 google/cosmos: romstage needs the accessor functions for buttons
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.

Change-Id: Iecfd37e79883d826e15c474d77095fbbbb2b7cea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10705
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:18:46 +02:00
Patrick Georgi dea4bb676a google/storm: romstage needs the accessor functions for buttons
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.

Change-Id: I59a4f892ca84d475d8f46c8f8c1906dae10ad32d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:18:38 +02:00
Patrick Georgi 3cbbf19075 qualcomm/ipq806x: Fix uart in verstage
An old Kconfig symbol from Chrome OS survived into the Makefile (but is
nowhere declared or used). Use the same symbol as for uart.c in the other
stages.

Change-Id: I7a6f1b82254e888d6f2d65d6cff87c4d546ec097
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10703
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-30 08:18:22 +02:00
Patrick Georgi 954781f4f8 qualcomm/ipq806x: centralize vboot configuration
vboot configuration (separate stage or not, which stage loads romstage)
depends on SoC properties (eg. amount of SRAM), not on board specifics, so
move this part of the configuration to the SoC.

Change-Id: I70b4cd1794ddf2aba7cdae94859ea1d76ae019f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:18:12 +02:00
Patrick Georgi f0a97bf75e google/veyron: Fix building with CHROMEOS enabled
romstage requires some button accessor functions for the Chrome OS boot flow.

Change-Id: I3f90d66b103e0610931c183dd5f5679ca6f910f6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10697
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 08:17:52 +02:00
Patrick Georgi 2268b3b750 arch/arm64: Avoid race condition when building bl31
The arm-trusted-firmware build system may not create the final bl31.elf file
atomically, confusing our make to try to use it before it's ready.
Hence insert a (hopefully, but not guaranteed to be atomic) file move.

Change-Id: Iffc80467e0f4bbc96fc62414d4abfaa7b42634f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10700
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 08:11:39 +02:00
Julius Werner da0098a4d0 mainboard: Add Veyron_Shark
This patch adds the Veyron_Shark mainboard as a clean copy of Veyron_Speedy.

- board-ID differentiation removed, see mainboard.c
- speedy -> shark rename

BRANCH=None
BUG=None
TEST=Compiled.

Change-Id: I3b743a97f152f49647eee87be8f1497377ccacb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac2ca328adf7e0dd879f51bbeae3cc11bceebf86
Original-Change-Id: I8a7cc9acb199ecf23b388c66f6885931ea3ec219
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/276490
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/10699
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 08:11:26 +02:00
Duncan Laurie a51815119f hardwaremain: Move init_timer() call to before console init
The 8250 MMIO uart driver calls udelay, and if that is the first
call then it will also call printk in init_timer() which can result
in a deadlock trying to acquire the console lock.

There are a few options to prevent this:
1) remove the printk in init_timer which removes a useful debug message
2) change the udelay() to cpu_relax() in uart8250mem.c
3- move the init_timer() call in ramstage main() to be called earlier

Since hardwaremain.c:main() already has an explicit call to init_timer()
on x86 it is an easy change to move this to happen before the console
is initialized.

BUG=chrome-os-partner:40857
BRANCH=none
TEST=boot on glados with serial output through ramstage

Change-Id: I8a8d8cccdd0b53de9de44600076bfad75e4f5514
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 744610f72628a944582925933b286f65bde630d9
Original-Change-Id: Ic1fdafaea5541c6d7b1bb6f15399c759f484aa74
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/275157
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10698
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 08:11:16 +02:00
Patrick Georgi fbc45a60eb arch/arm64: Fix compilation without CONFIG_SMP
Compilers aren't happy with a declaration of boot_cpu() after defining
boot_cpu to 1.

Change-Id: I22d0db61646f3e226e5996fa94223ffbb6b760e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:11:03 +02:00
Stephen Barber e72487944f t210: Set UTMIP_PCOUNT_UPDN_DIV to 0
Improve USB device mode stability as per suggestion by Laurent.

BUG=chrome-os-partner:40929
BRANCH=smaug
TEST=flash firmware and check that USB device mode is still functional.

Change-Id: Id6dd7bb2e1632c512cfdf7d38a16de26a8f71471
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4298741ef4440c8bd8dac4a9f9eaa55ba560cbfb
Original-Change-Id: I07d6c46d215f2ccf2c76c580f59c4fa0d519eaa5
Original-Signed-off-by: Stephen Barber <smbarber@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/278030
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Tested-by: Benson Leung <bleung@chromium.org>
Reviewed-on: http://review.coreboot.org/10695
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:54 +02:00
Furquan Shaikh 67246f4738 arm64: Fix Kconfig issues for secure OS loading
BUG=chrome-os-partner:40713
BRANCH=None
TEST=Compiles successfully with and without SECURE_OS config selected

Change-Id: I93e9726712a1992f1788d60891d5f6917bba3767
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 535ac9ffd1199b047734da0a9ee257d468b3fbb1
Original-Change-Id: Ic70a0b57816a5f3af548edafd82ba3783825a174
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274416
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:46 +02:00
Furquan Shaikh a384c2899d arm64: Add support for loading secure os
Add support for loading secure os and pass its entrypoint as bl32 params
to bl31 stage.

BUG=chrome-os-partner:40713
BRANCH=None
TEST=Compiles successfully and loads secure os

Change-Id: I1409ccb7344c1d1b1ddc2b321fdae1beea2f823d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d3dc19025ff11c1e0590306230df7654ef9ad086
Original-Change-Id: Iafd540bf2906d10b5ee009e96179121fecbf5e11
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273719
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10693
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:28 +02:00
Patrick Georgi add740ac28 Add Kconfig flag to specify if there's a lid switch
Not all devices have a lid switch, so we need to state this
somehow. Since the alternative would be to extend get_lid_switch()'s
semantics to become a tri-state (open, closed, N/A), do this
through Kconfig.

BRANCH=none
BUG=chromium:446945
TEST=none

Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848
Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273850
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:19 +02:00
Patrick Georgi 08b8785aeb Expose get_lid_switch() in romstage
The function was used locally and in ramstage to set some
coreboot tables. It's also needed in romstage to deal with
"lid closed" behaviour.

BRANCH=none
BUG=chromium:446945
TEST=none

Change-Id: I8ad7061328c45803699321aa9f5edb0ed2288a8d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 78281a104fb9d79696a6ceb2a9a89a391146a424
Original-Change-Id: I56314b9dc9062dd61671982e7ec0ff15d7eb1bae
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273609
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:10:11 +02:00
Furquan Shaikh 066cc85e22 EC: Add new EC host event for FASTBOOT_MODE request
BUG=None
BRANCH=None
TEST=Compiles successfully

Change-Id: Id24b87e03097eb93c0b4316c853575629e5502aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf80de709d2bf310a3a37b9897063d2d833933b9
Original-Change-Id: Ia5d42efd81b59c1b99d3be5be6d0c770ad602429
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280879
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10688
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:41 +02:00
David Hendricks 14610ec20a veyron_danger: Update SDMMC power on/off code for v2
This re-factors SDMMC power on/off to make corrections and take
differences between board versions into account. To avoid similar-
but-different case switch statements in romstage.c and mainboard.c,
power on/off functions for SDMMC are split into their own .c file.

BUG=none
BRANCH=none
TEST=built and booted of micro-SD card on Danger v2

Change-Id: Ib3069c35ceff1ff98b49579a6298681c1390beee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eecfee4a5dd39073b5f966a25991a594b3c4b519
Original-Change-Id: Id86ae7f40687e843ffc4e7769309d4678ad54f49
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280853
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10685
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:13 +02:00
David Hendricks 4039822dc4 veyron_danger: Add basic HDMI support
This adds a configure_hdmi() function that drives the HDMI
enable output high and configures the iomux.

We'll add EDP/HDMI auto-detection in an upcoming patch.

BUG=none
BRANCH=none
TEST=set vop_mode to 1 in Danger's devicetree.cb and saw
dev mode screen output to HDMI display.

Change-Id: I2a208059fee74d436b5a5bedbc677bc59525f935
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 721f326319f727afcf73a0c21d20d26cb463ad71
Original-Change-Id: I139d39749963d4121aaeec0c3da37d825ffa94ac
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280849
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10684
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 08:09:02 +02:00
Stefan Reinauer 9bca4ba078 vboot2: Enable VBOOT_DYNAMIC_WORK_BUFFER on x86
Change-Id: Iaadbd52d948000d1ed46865b83bdb0f4926ca429
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10677
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-29 23:20:05 +02:00
Patrick Georgi aabfe05bff vboot2: consolidate vboot2 buffer initialization
Instead of calling the init function to clear out vboot2 data structures in
multiple places, move the function and call close to verstage_main().

Change-Id: If42e18a8e4581f22f7a7aced70ccbe3188bb0cd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10701
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-29 23:13:17 +02:00
Jonathan A. Kollasch 619781493a mainboard/msi/ms7135: DSDT: fix PCI and AGR interrupts
Tested with interrupting AGP card in AGR slot.
PCI slots tested with 3-function OHCI/EHCI USB 2.0 card,
covering the INTA-INTC lines in each.

Change-Id: I0f8aeba90890a76a7cf9cbee9be7bcf919d1e39a
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10644
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29 18:28:59 +02:00
Jonathan A. Kollasch 7a75aff3ff mainboard/msi/ms7135: only #include necessary headers in acpi_tables.c
Change-Id: I0837a2d1e0d8e233f6ef7d7212ce76f2223d19b9
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10641
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29 18:19:10 +02:00
Patrick Rudolph 4275ff86fa intel raminit: check correct registers in channel_test
Found while doing code review. No actual problem was observed.

Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H

Verify byte-lane error count registers 0 to 7 instead of verifying byte-lane
error count register 0 eight times in a row.

Change-Id: Ife6ac6558b2f65ad947870cde5f15d90560ce6d9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10664
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-28 22:42:11 +02:00
Patrick Rudolph 3247916d11 intel raminit: properly handle DDR3 DIMMs with address mirroring
Issue observed:
DDR3 DIMM with address mirroring enabled doesn't work when placed in
slot 1 and slot 0 is empty. It does work when placed in slot 0 and
slot 1 is empty.

Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
* Kingston KVR1066D3N7/4G (address mirroring enabled DIMM)

Problem description:
The address mirror enable bit is slot-swapped in the DIMM mapping code,
but none of the remaining code is aware of DIMM mapping. Removing the
code, that is swapping the mirror enable bit, results in the correct
behaviour. The DIMM is now working in every slot.

Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10652
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-28 22:40:41 +02:00
Timothy Pearson 039edebc08 mainboard/asus/kfsn4-dre: Enable VGA support
The ASUS KFSN4-DRE has full native VGA support, enable support for the
VGA device by default in the Kconfig file.

Change-Id: I09fc8845a30f26ca49f3547812f9784621ff4b5e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10673
Tested-by: build bot (Jenkins)
Reviewed-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-06-27 05:59:16 +02:00
Martin Roth b6c2f8919e lenovo/g505s: Add System Board ID to fix ACPI warning
Add the System Board Hardware ID to fix the warning:

dsdt.aml     88:  Device (MB) {
Warning  3141 -           ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)

Change-Id: Ie97b1e6792c8d4c8db2500cef6a79881b7ff94c8
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10669
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-27 02:48:42 +02:00
Martin Roth 9a4cbc9d15 google/parrot: Add System Board ID to fix ACPI warning
Add the System Board Hardware ID to fix the warning:

dsdt.aml     88:  Device (MB) {
Warning  3141 -           ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)

Change-Id: I063580142ae8053fdc05e165c01e86b8b7cd5ca6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10668
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-27 02:48:11 +02:00
Martin Roth 0458370bf7 Kconfig: Remove unnecessary and incorrect MRC_CACHE symbols
Because of a misunderstanding of how Kconfig files are parsed, the
OVERRIDE_MRC_CACHE_LOC symbol was added to make sure that the value
was correctly set.  This is not needed unless for some reason the
Kconfig parser is suddenly rewritten to parse everything differently.

At some point, the value in the FSP's Kconfig file was updated to
OVERRIDE_CACHE_CACHE_LOC, while the entries in the mainboard
Kconfig files were not updated.  This resulted in the default values
not getting set correctly by default on the FSP Bay Trail boards.

This removes the whole bunch of incorrect and unnecessary symbols and
just sets the default for the MRC cache location directly.

Change-Id: I1cec758576866b7e0677272b8309bfde8d4a1ee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10611
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-27 02:47:39 +02:00
Stefan Reinauer 302a2ec7d1 amd/inagua: broadcom driver 64bit fix
Change-Id: I357f11fa74bac5f9e1ecfc91a91f06127334752d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10596
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-27 01:01:26 +02:00
Patrick Georgi bfa51979dc rockchip/rk3288: complete vboot configuration and move to SoC
Where vboot verification can start, and how the code flow looks like is more a
property of the SoC (and its properties, like amount of SRAM) rather than the
board.

Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10662
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26 23:30:39 +02:00
Patrick Georgi 463d665cb1 google/chromeos: always enable VBOOT_VERIFY_FIRMWARE with CHROMEOS
Change-Id: Icc3cf64f259d4ebd7900ad91163276774e5422ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10661
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26 23:30:13 +02:00
Patrick Georgi 0d5f27b8bb vboot: Init vb2 work memory area before calling verstage
Otherwise it'll determine some offsets from uninitialized data and hilarity
ensues.

Change-Id: I6a671987857cfd3f3cd6078aebd13dd09fc79020
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10660
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26 23:30:01 +02:00
Patrick Georgi 1dc22f5cbc google/veyron_speedy: Add chromeos.c to romstage
vboot requires it.

Change-Id: Iae2310c9b9c311c3f64b8417295685261ba404b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26 23:29:51 +02:00
Stefan Reinauer 987493300d x86: Move architecture selection from linker script to Makefile.inc
Change-Id: I5efd3cb3e6970b5740f740507244a1ab823e0bb6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10590
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-26 22:44:10 +02:00
Stefan Reinauer eec2db4da7 prog_loader: Play nice with gc-sections
With an x86_64-elf toolchain, this code that is unused
outside of ramstage, is causing undefined references.

Help the compiler along a little bit by conditionally compiling
the code in ramstage only.

Change-Id: I75518149b53c24eda4b985b0fef856447e196dec
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-26 22:43:46 +02:00
Lee Leahy 3e5bc1feab soc/intel/common: Restrict common romstage/ramstage code to FSP
Restrict the use of the common romstage/ramstage code to FSP 1.1

BRANCH=none
BUG=None
TEST=Build and run on cyan/sklrvp

Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10653
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-26 00:01:57 +02:00
Lee Leahy fbe276b96f Braswell: Remove copyright address
Remove the copyright address from all of the files.

BRANCH=none
BUG=None
TEST=None

Change-Id: I7190e34e165e5652d33902440fa08253b77f4af2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10337
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25 21:51:17 +02:00
Lee Leahy 32471729d9 Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.

BRANCH=none
BUG=None
TEST=Build for a Braswell platform

Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25 21:50:48 +02:00
Martin Roth 5fe62efb77 soc/intel/common/Kconfig: Fix warning & whitespace
Because of a missing close quote, we have the warning:
src/soc/intel/common/Kconfig:52:warning:multi-line strings not supported

This was added in commit 0946ec37 -Intel Common SOC:Add romstage support

The whitespace issue - using spaces instead of a leading tab was added
in the same commit.

Change-Id: I429c66afb5a7e10ca0e0ef619ac46722c63fb376
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10654
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-25 20:25:30 +02:00
zbao 3ad1f1ca5f amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0
Besides the first five DWORDs, the offsets 0x40 & 0x41
are used to save SPI settings. They should only be 0xFF
for being written.

Other parts in ROMSIG are also changed to 0xFF for potential
requirement.

Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/10651
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-25 04:06:59 +02:00
Martin Roth 128043edee Intel FSP 1.1: Move Kconfig comment inside 'if' block
- Move the 'Intel FSP' Kconfig comment inside the 'if' block so that it
doesn't show up on platforms that aren't using it.
- Update the comment to reflect that this is version 1.1 of the FSP
interface.

Change-Id: I7182c5b07332c4f95620f7374526ab1de0484d01
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10650
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-25 00:02:37 +02:00
Lee Leahy 40c0543108 Intel/common: Remove copyright address
Remove the copyright address from the remaining files.

BRANCH=none
BUG=None
TEST=None

Change-Id: I026a0ff2bcb6c9580b45700edab446b787223007
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10336
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-24 17:05:35 +02:00
Lee Leahy 0946ec37aa Intel Common SOC: Add romstage support
Provide a common romstage implementation for the Intel SOCs.

BRANCH=none
BUG=None
TEST=Build for Braswell

Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-24 17:05:06 +02:00
Lee Leahy 4a8c19cc90 FSP 1.1: Bring source up-to-date
Use 3rdparty/blobs subdirectory for binary files
Display the MTRRs after TempRamExit and before the MTRR setup
Clear all of the variable MTRRs before the MTRR setup
Define the FSP attributes location and bits
Properly display the FSP_RESERVED_MEMORY_RESOURCE_HOB and the
FSP_BOOTLOADER_TOLUM_HOB.

BRANCH=none
BUG=None
TEST=Build and run on cyan

Change-Id: I788a5f1e7676b1a06c1bcd66ddbd0a2249cad47c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10589
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24 17:03:49 +02:00
Lee Leahy bfdf2489f0 cpu/x86: Add more MTRR symbols
BRANCH=none
BUG=None
TEST=Build and run on strago

Change-Id: Ia3740353eb16f2a2192cad8c45645f845bf39475
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10588
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24 17:03:29 +02:00
Lee Leahy edf0d58fff Intel vendorcode: Add FSP_SMBIOS_MEMORY_INFO_GUID
Add new GUID for FSP.

BRANCH=none
BUG=None
TEST=Build and run on strago

Change-Id: I539a59b513f67535436f581e0a79ab53f05682ca
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10587
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24 17:02:58 +02:00
Tobias Diedrich 1f7f4d49a1 pcengines/apu1: Remove unused ide.asl
The APU1 board has no IDE port, remove ide.asl.

Change-Id: I76b926969748de79ac1281ed50b37e9ade1a6771
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10622
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-24 07:20:16 +02:00
Patrick Georgi ba71ca3315 Remove address from GPLv2 headers
Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.

Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10640
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-24 07:09:24 +02:00
Martin Roth c4dd3e0212 Kconfig: Get rid of obsolete symbols
CAR_MIGRATION was removed in commit:
cbf5bdfe - CBMEM: Always select CAR_MIGRATION

ALT_CBFS_LOAD_PAYLOAD was removed in commit:
cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD

MARK_GRAPHICS_MEM_WRCOMB was removed in commit:
30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB.

EXTERNAL_MRC_BLOB was removed in commit:
0aede118 - Drop unused EXTERNAL_MRC_BLOB

CACHE_ROM is only in Google's codebase.
LID_SWITCH is only in Google's codebase.
DEFAULT_POST_DEVICE_LPC is only in Sage's codebase.
ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used.

HUDSON_NOT_LEGACY_FREE never existed as far as I can tell.
MAINBOARD_DO_EDID never existed as far as I can tell.

Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10616
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-24 06:03:42 +02:00
Kyösti Mälkki a48232268d sandy/ivy: Include IRQ routes from platform
The default route does work for all Chromebooks and is replaced
with platform-specific one in follow-up.

Change-Id: Ia1839ed38dacf44a89dc757394d054e17666f193
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10442
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-24 02:02:44 +02:00
Jonathan A. Kollasch 41e8d27878 msi/ms7135: move power_on_after_fail out of RTC century byte
Change-Id: I0796b6e7adad0151c5aa6271d62a2cf4abeedb1e
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10643
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 22:59:18 +02:00
Tom Warren 355dc1e66a nvidia/tegra: expose more registers
This is in preparation for t210

Change-Id: I3e640b1f7fc583518361527dec4c3c1072c80251
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e762d4bde1a18691257453e4b87a0bb42a0a2d7c
Original-Change-Id: Ida096106bb0137c07ad62d2df06628e37f0d884c
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272754
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10632
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2015-06-23 22:58:32 +02:00
Furquan Shaikh 018216d120 tegra: Move pinmux enum constants from tegra/pinmux.h to soc-specific pinmux.h
Since pinmux register format has changed completely for t210, move the
constants to pinmux.h in soc-specific folders.

BUG=chrome-os-partner:37546
BRANCH=None
TEST=Compiles successfully for ryu and foster.

Change-Id: Ic1680ac50fc2619657d0c610a5dfc3fb51df7286
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7844c941a6187f884b31a8f7cc52e64268d2c732
Original-Change-Id: Icd3b2a72f3698e0772e888d9209e1fcd5d10e77d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/260900
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10631
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2015-06-23 22:58:26 +02:00
Martin Roth 59aa2b191b southbridge/intel: Create common IFD Kconfig and Makefile
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC.
This is the start of creating a common interface for all of them.

This also allows us to reduce the chipset dependencies for CBFS_SIZE.

Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10613
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23 22:48:45 +02:00
Stefan Reinauer 6ab0fd0a94 vendorcode: Use cross archiver for libagesa.a on AMD f14
Change-Id: I61a9f65a1ac4c95096d0ff071a95984cf219caa8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10593
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-06-23 22:27:52 +02:00
Stefan Reinauer 23ec0a570e lippert/frontrunner-af: 64bit fixes
Change-Id: Ia764798c8b58497e2b453bd000dd06816c28f98f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10600
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 22:23:27 +02:00
Stefan Reinauer 03c6ab5ea6 lippert/toucan-af: 64bit fixes
Change-Id: I9e7f78587b9d6e87cf77757654da9145d4187625
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10599
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 22:08:41 +02:00
Patrick Georgi c32a52c200 acpi: bring back ability to link DSDT into ramstage
Bring back the ability to link in the DSDT. This is to help Chrome OS to
switch over to a new upstream quickly (because some of the custom built
mechanisms are a pain with tons of files).

This is supposed to be temporary (famous last words), but I'd rather fix the
lack of CBFS awareness in CrOS bit for good in the time I usually spend on
keeping upstream and CrOS branches close.

Change-Id: I7fa5540bbf5c568c4adca56a09c83b6c7e358ad5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-23 21:19:02 +02:00
Stefan Reinauer edae744467 drop unneeded IRQ_SLOT_COUNTs
This is only needed on boards that still provide old style PIRQ
tables.

Change-Id: Ie299de2937e5b91b7b3e1d1110e40be23c6d9f52
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10508
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 19:57:52 +02:00
Stefan Reinauer e6946c626a pcengines/apu1: 64bit fixes
Change-Id: Iacad070f43534a8b27a2473a6a2854bc2f6e607a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10598
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 19:56:48 +02:00
WANG Siyuan db08765962 AMD Kern: Fix path of PspSecureOs BLOB
AMD Kern uses PspSecureOs_prod_CZ.csbin rather than PspSecureOs_prod_CZ.sbin.
PspSecureOs_prod_CZ.csbin is the firmware in CarrizoPI v1.0.0.7.

Change-Id: Idf54ee808dd6965aec9b979be00b7f890a88b06d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10639
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 18:30:16 +02:00
Martin Roth 026e4dc3ff Kconfig: Move CBFS_SIZE into Mainboard menu
The CBFS size is really mainboard specific, since it really depends on
size of the chip on the mainboard, so it makes sense to have it in
the mainboard menu along with the ROM-chip size.

- Move the CBFS_SIZE definition up in src/kconfig
- Move the Mainboard Menu markers out of src/mainboard/kconfig into
src/Kconfig so CBFS_SIZE can live in the mainboard menu.
- Add a long list setting default values to do what the chipset
directories were previously defaulting the values to.  This will
be trimmed down in a following patch that creates a common set of
IFD routines.  (Who knew that kconfig supported line wrapping?)
- Update the help text.

Change-Id: I2b9eb5a6f7d543f57d9f3b9d0aa44a5462e8b718
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10610
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23 09:42:44 +02:00
Martin Roth 920f2e63e5 SeaBIOS: Clean up build command line.
- Move IASL up with the other tools.
- Remove OUT= which is no longer used in the
payloads/external/SeaBIOS Makefile.

Change-Id: I211ddcf3496b533151936fa5cbfa7a92986ec28f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10606
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23 08:26:37 +02:00
Patrick Georgi e6e94934e8 intel/broadwell: Fix refcode handling
Allow adding and executing a refcode binary.

Change-Id: I00e91a088a5695b42528e246d0ed642d988603e3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/10638
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23 08:23:02 +02:00
Patrick Georgi f1db074bc4 broadwell: fix typo
It's guarded by a non-standard configuration option, so didn't trigger.

Change-Id: Ib7a9a45befcb7857edde37e20de7d65a60970882
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10623
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23 08:22:54 +02:00
huang lin ad8382a3ee veyron_mickey: Apply differences between Brain and Mickey
Mickey:
- Does not have power key
- Does not have an audio codec(all audio goes thru HDMI)
- VCC18_LCD moved to VLDO8 and needs to be turned on (was
  connected to VSWOUT2 earlier)

BUG=none
BRANCH=none
TEST=Boot from mickey board, and hdmi work normal

Change-Id: I88cdc41ce8bb96a6b17aeb7f24b1c5619471b24e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c966edfa29df1049c469442dc3ad8bf8b4197b1
Original-Change-Id: I3d98203185f52ed751a5d3045a0ee8f9b4dfbc71
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274876
Reviewed-on: http://review.coreboot.org/10630
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 08:21:23 +02:00
David Hendricks c3f18da5ae veyron_danger: Fix #include guard
Cosmetic change only.

BUG=none
BRANCH=none
TEST=it compiles

Change-Id: Ibe86f624606e365457e03c50c005400d4b335536
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7dfc7002fbf5c100ae65458b33f5aa007dc8d60b
Original-Change-Id: Ibc03b028a7918d90cfab9614e800f6df463d86db
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280851
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10628
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-06-23 08:21:11 +02:00
Stephen Barber 31f8a2fe74 chromeos: vpd: properly null terminate values
VPD strings are not null terminated, so we can't use strcpy
on them in cros_vpd_gets.

BUG=none
BRANCH=none
TEST=add serial_number followed by cam_calib_data to VPD on smaug;
make sure that smaug boots and serial number matches exactly (no garbage)

Change-Id: Id72885517b3d0b1934ba329c1ef0d89a67bd2bb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 56bbe6688b11043360a046a250d1ea93db4d9f0e
Original-Change-Id: I811dfc2f0830a91410eb69961a6565080ff78267
Original-Signed-off-by: Stephen Barber <smbarber@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280836
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: http://review.coreboot.org/10627
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-23 08:20:59 +02:00
Yakir Yang 68f42be887 rockchip/rk3288: add support for hdmi display
this is an brief hdmi driver which config with simple
display parameter, const encoder input & output color
format and 8bit color depth, and only 48KHz audio support.

what's more to prevent TV have not show an right things
before coreboot switch to kernel space, we have to add
an terrible 2s delay to driver (2s come from test many
times), cause we have to wait TV to respond (we got no
flag to check whether it is ready).

BUG=chrome-os-partner:40337
TEST=Booted Veyron Jerry and display normal
BRANCH=None

Change-Id: Icd33467e95de6219e1b614616f0112afc52097b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e5b699aff75a579116aae63d858c834b2f648e8
Original-Change-Id: Iedc87c011c5b62ce5f16a296dd9c3e0c2eaba59b
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272565
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23 08:20:33 +02:00
Furquan Shaikh 464f5ca6d6 Revert "arm64: remove assembly code string functions"
This reverts commit 00263d0d8e
to reintroduce optimized string handling functions.

BUG=chrome-os-partner:41185
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on Smaug

Change-Id: I47f8d8afa5c9ff3fca67d4d0f393336fef03402b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eeb38afea828a2727d815e4fb5762cfdd09a2b3a
Original-Change-Id: Id053cbcea8b5e7ae29bdd6bb8b6f5e5011c42b00
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/275865
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10564
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 08:20:11 +02:00
Patrick Rudolph 78c6e3ec42 ddr3: add missing newline
Add missing newline to SPD CRC verification error message.
Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H.

Change-Id: Id1a0a2329507975c3f66ab884f6e26d99003318e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10636
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-23 01:50:33 +02:00
Patrick Rudolph 8c639359ea ddr3: Fix SPD CRC calculation
Use the correct SPD size for crc calculation. sizeof(*spd) returns 4
while sizeof(spd_raw_data) returns the expected value of 256.
Fixes erroneous printing of "ERROR: SPD CRC failed!!!" in raminit log.
Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H.

Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10629
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23 01:50:16 +02:00
WANG Siyuan 6762a8b85e AMD PI agesawrapper: add PSPP (PCIe Speed Power Policy) interface
PSPP policy is defined in 3rdparty/blobs/pi/amd/*/AGESA.h
/// PCIe PSPP Power policy
typedef enum  {
  PsppDisabled,                                           ///< PSPP disabled
  PsppPerformance = 1,                                    ///< Performance
  PsppBalanceHigh,                                        ///< Balance-High
  PsppBalanceLow,                                         ///< Balance-Low
  PsppPowerSaving,                                        ///< Power Saving
  MaxPspp                                                 ///< Max Pspp for boundary check
} PCIE_PSPP_POLICY;

Change-Id: I7fe735cddea94a83e38d856a3de1f27735467a28
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10461
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-23 01:10:52 +02:00
WANG Siyuan 2dcd0fc494 Move same Kconfigs to northbridge/amd/pi/Kconfig
Bettong, Lamar and Olivehill Plus have many same Kconfigs.
Move them to northbridge/amd/pi/Kconfig.

Change-Id: I758d5a09f27eee7a7bd60268a2aaed6f16fd0294
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10421
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23 01:10:44 +02:00
WANG Siyuan 01e3e0638d AMD Bettong: Add a new AMD FP4 socket mainboard
Add a new mainboard based on AMD's Family 15h Model 60h processor.
TEST: Bettong can boot Ubuntu 14.10, Windows 7 and Windows 8.

Change-Id: Id807369ff0f04ba303383c65ddd1bd512f184e6a
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10420
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23 01:10:35 +02:00
WANG Siyuan 0563941654 AMD Merlin Falcon: Add northbridge files for new AMD processor
Tested on Bettong. Windows 7, Windows 8.1 and Ubuntu 14.04 can boot.

Change-Id: Ifcbfa0eab74875638a40e74ba2a3bb7c4fb02761
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10419
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22 22:27:31 +02:00
WANG Siyuan d3deecdd9c AMD OemS3Save: refactor for Merlin Falcon
Merlin Falcon(Carrizo) replaces struct AMD_S3SAVE_PARAMS
with struct AMD_RTB_PARAMS and replaces AMD_S3_PARAMS with
S3_DATA_BLOCK.

Change-Id: If074a8de95d82130d29b2e3cfbd7e35cdb9b929d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10526
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22 22:27:14 +02:00
Martin Roth 7403e059ec Remove incorrect Kconfig expressions
The symbols used in these expressions were not correct and would never
evaluate as true.

Change-Id: Ia20177f41505473b14bc7b8e4b6fb16de36cc295
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10437
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-22 21:22:47 +02:00
Francis Rowe 86da2c70e2 lenovo/x60: Enable VESA framebuffer mode (native graphics)
At present, no option exists for "Keep VESA framebuffer", which
means that text-mode will be used. Add the appropriate Kconfig
option.

Change-Id: Iaed07eba6d9288c857f7e7a0b0be1107071e49e5
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/10553
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-06-22 19:23:22 +02:00
Francis Rowe 27ce9b1f27 lenovo/x60: Enable brightness controls (native graphics)
On i945 legacy brightness control is enabled by a single
bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one
reverses polarity). Set the bit to enable brightness
controls.

Change-Id: Id855c4e91fe71fb489739e62fbe99ca22841acd2
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/7048
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-22 19:23:11 +02:00
Stefan Reinauer 36b78852e2 superio: use common x86 code on x86-64
Change-Id: I2ddb5a8b183b21cbd3c3b22c537b815e86bd4738
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10592
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22 07:36:09 +02:00
Stefan Reinauer 1e2500e948 device: DDR3 generic code 64bit fix
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: I5ff309948c36289eedeb8a18030cdd2b4c337690
Reviewed-on: http://review.coreboot.org/10595
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22 07:35:42 +02:00
Stefan Reinauer 83fa169101 oprom: Fix for 64bit
Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10591
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22 07:35:21 +02:00
Stefan Reinauer 0e7b7bb6b3 device: Use x86 specific code on x86-64
Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10584
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22 07:34:41 +02:00
Stefan Reinauer b0bb8a1bb4 x86: make PCI MMIO CFG functions 64bit proof
Change-Id: Ife94f5324971f4fa03e9139f458b985f6fed9d87
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10577
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22 07:34:28 +02:00
Martin Roth a412d399e9 Remove obsolete EARLY_CONSOLE usage
The EARLY_CONSOLE Kconfig symbol was removed in
commit 48713a1b - console: Drop EARLY_CONSOLE option

The arm64 and mips directories don't even have early_console.c
to include.

Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10615
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-21 21:11:04 +02:00
Martin Roth 64ae446dbc superio/fintek/Kconfig: add newline at end of file.
Kconfig sometimes fails to parse the last line of a file if there's
no newline at the end.  Add one to be safe.

Change-Id: Ia9973a89b12596e1f2a2741ad2e255e886495331
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10614
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-21 21:10:28 +02:00
Martin Roth e1523ecaa1 Reorder arch & vendorcode in Kconfig
Because Kconfig uses the first valid default that it comes across, the
'source' commands to load sub-Kconfigs should be ordered from the
most specific (mainboards) to less specific (chipsets) to least specific
(architectures).  This allows the mainboards to override chipsets and
architecture Kconfig files.

Because the architecture files were getting loaded ahead of the chipset
and cpu Kconfigs, the preferred defaults values for things such as
NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set.

Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10609
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-06-21 08:24:55 +02:00
Martin Roth eb22da0e4d Remove old HAVE_UART_MEMORY_MAPPED select statements
The HAVE_UART_MEMORY_MAPPED symbol is no longer present, so these
don't actually select anything.

Change-Id: I6d0eb610e48a4506ac7449ac677ee67981d0ff0d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10608
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-21 00:20:17 +02:00
Stefan Reinauer e021dea777 cpu: x86 port to 64bit
Change-Id: Ib1c6732d3a338f6d898fadc19e5af59032343451
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10580
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20 18:16:54 +02:00
Stefan Reinauer defee17c67 x86: Make ACPI 64bit clean
Change-Id: I29eaba74185711df055cf56c23ef2bdae0c7b43e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10578
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20 18:16:31 +02:00
Stefan Reinauer bef400b96c x86: Make reading / writing of CRx registers 64bit proof
Change-Id: I782007fe9754ec3ae0b5dc31e7865f7e46cfbc74
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20 18:15:33 +02:00
Stefan Reinauer 7c35af2bc3 x86: make memcpy 64bit safe
This does not optimize memcpy for 64bit, it merely makes it compile.

Change-Id: I69ad6bd0c3d5f617d9222643abf7a2ba7c2a0359
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10575
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20 18:15:01 +02:00
Jonathan A. Kollasch d9628ece50 winent/mb6047: initialize hardware monitor CPUTIN configuration
Change-Id: Ic36727104e5c2f620f9b2b7b340de8548b467397
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10547
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17 16:01:48 +02:00
Fabian Kunkel 7558dbac31 mainboard/bap: Add support for BAP ODE E20XX
Adding new board based on AMD Kabini.
Most of the code is copied from gizmosphere/gizmo2
Board is developed by BAP - Bruhnspace Advanced Projects:
http://www.unibap.com/ (Site is under construction)
Special on this board is:
-Soldered down memory
-SuperIO Fintek F81866D
Known bugs:
-S3 doesnt work
-Serial ports only works for the first boot. Needs power cut.
Tested with:
-SeaBios as Payload
-Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1
-Windows 8 64Bit

Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10288
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17 12:01:04 +02:00
Tobias Diedrich 2a38551bb7 pcengines/apu1: Add ACPI led, button and GPIO devices.
Provide ACPI devices with devicetree-compatible annotations for the
three leds and the button of the APU1, as well as the GPIO driver.

This will cause the Linux kernel to automatically load the following
modules:
  leds_gpio (CONFIG_LEDS_GPIO)
  gpio_keys_polled (CONFIG_KEYBOARD_GPIO_POLLED)
  gpio_sb8xx (CONFIG_GPIO_SB8XX)

See
http://events.linuxfoundation.org/sites/events/files/slides/ACPI_vs_DT.pdf
and https://lwn.net/Articles/612062/ for some more information on how
the PRP0001 HID works.

To make this usable a Linux GPIO driver for the AMD chipset is also
required, which I am currently working on, but have not submitted
upstream yet.

Leds have been named after the convention in
Documentation/leds/leds-class.txt:
LED Device Naming
=================
Is currently of the form:
"devicename:colour:function"

For comparison, on an OpenWRT device:
GPIOs 0-21, ath79:
 gpio-1   (tp-link:green:usb   ) out hi
 gpio-2   (tp-link:green:system) out lo
 gpio-3   (reset               ) in  hi
 gpio-5   (tp-link:green:qss   ) out lo
 gpio-7   (qss                 ) in  hi
 gpio-9   (tp-link:green:wlan  ) out lo
 gpio-18  (rtl8366rb           ) in  hi
 gpio-19  (rtl8366rb           ) in  hi

On the apu1:
GPIOs 288-511, platform/PRP0001:00, AMD SB8XX/SB9XX/A5X/A8X GPIO driver:
 gpio-475 (switch1             ) in  hi
 gpio-477 (apu1:green:led1     ) out hi
 gpio-478 (apu1:green:led2     ) out hi
 gpio-479 (apu1:green:led3     ) out hi

Change-Id: I956ee92d9d98ef27a83ccb30d314543bd8634f2c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10540
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17 12:00:20 +02:00
Furquan Shaikh 69139e0e2a coreboot_tables: Add CBMEM ID and tag for MTC
BUG=chrome-os-partner:41125
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt

Change-Id: Ia95b2a21863df5c3d6c08e9a134618db03a58775
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8462a33c62ab34d0f5049fc3a7c5c2ee8e5e2e4c
Original-Change-Id: Ie48a9a776b1c3ad30acf924c3d073acc8f2a8eda
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276779
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10562
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17 11:56:12 +02:00