Commit Graph

28884 Commits

Author SHA1 Message Date
Subrata Banik 7bc9036d16 arch/cpu: Rename mp_get_apic_id() and add_cpu_map_entry() function
This patch renames mp_get_apic_id() to cpu_get_apic_id() and
add_cpu_map_entry() to cpu_add_map_entry() in order access it
outside CONFIG_PARALLEL_MP kconfig scope.

Also make below changes
- Make cpu_add_map_entry() function available externally to call
it from mp_init.c and lapic_cpu_init.c.

BRANCH=none
BUG=b:79562868

Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-12 03:08:10 +00:00
John Zhao 1159a163cd soc/intel/cnl: Enable VT-d
Enable VT-d through fsp upd VtdDisable. Update remapping structure
types in numerical order as all remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.

BUG=b:130351429
TEST=Booted to kernel and verified the DMAR table contents.

Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2019-05-11 11:16:48 +00:00
Ronald G. Minnich 4249348735 Define ENV_PAYLOAD_LOADER
We've been assuming that ENV_RAMSTAGE is always the payload loader.
In order to test out different models, we need a way to mark the
"stage we are in" as the payload loader.

Define a new rule, ENV_PAYLOAD_LOADER. For now, it is set
to ENV_RAMSTAGE. It is not used yet pending approval of this
approach.

Change-Id: I7d4aa71bad92987374d57ff350b9b0178ee7c12b
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-11 03:24:33 +00:00
Julius Werner 998dc17f52 vboot: Turn vboot_logic_executed() into a static inline
This patch moves vboot_logic_executed() (and its dependencies) into a
header and turns it into a static inline function. The function is used
to guard larger amounts of code in several places, so this should allow
us to save some more space through compile-time elimination (and also
makes it easier to avoid undefined reference issues in some cases).

Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-10 21:43:15 +00:00
Julius Werner a73e5a75b1 assert.h: Undefine ASSERT macro in case vendorcode headers set it
Some edk2 vendorcode headers define an ASSERT macro. They're guarded
with an #ifndef ASSERT, but if coreboot's assert.h gets included after
that header, we still have a problem. Add code to assert.h to undefine
any rogue definitions that may have already been set by vendorcode
headers.

This is ugly and should only be a stopgap... it would be nice if someone
maintaining those vendorcode parts could eventually replace it with a
better solution. One option would be to use a "guard header" for every
vendorcode header we want to pull into normal coreboot code which would
chain-include the vendorcode header and then undefine anything that
clashes with coreboot again.

Change-Id: Ibf8dc8b2365821e401ce69705df20aa7540aefb2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-10 21:41:25 +00:00
Julius Werner ef7d89cabe vboot: Make vboot_logic_executed() a bit more precise
This patch adds another check to vboot_logic_executed() to make sure we
only do a runtime check for verstage_should_load() if
CONFIG_VBOOT_RETURN_FROM_VERSTAGE is enabled. That's the only case where
the stage that's loading the verstage can execute after verification has
run (because the verstage will return to it when it's done). In the
other case, the stage that loads verstage really just loads it and will
never do anything again after hand-off, so it's guaranteed to always
execute before verification.

This change may allow extra dead-code elimination in some cases.

Change-Id: I7019b6f7b0acfbf0a8173914b53364751b08f2cf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-05-10 21:41:14 +00:00
Marshall Dawson 939bfccb3d soc/amd/stoneyridge: Add IO access functions for PMx
Replace locations in the source that explicitely use the CD6/CD7
index/data pair with utility function calls.

Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-10 17:35:18 +00:00
Lijian Zhao f36fcdf2ab mb/google/sarien: Fix s5 touchscreen power leakage
Leakage power is observed from TOUCH_SCREEN_PD# (GPP_E7 which is connected
 to RESET pin of Wacom controller) during S5.
To avoid leakage power, GPP_E7 needs to be turned off before S5 entry.

BUG=b:129899315
TEST=Measure leakage power in S5 from both Arcada and Sarien

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-10 17:00:59 +00:00
Elyes HAOUAS 9646cfe989 sb/bd82x6x: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not
apply to this PCI bridge because it is only defined for
"Header type 0 (normal devices)" (line 82).
Some lines obove that code line, the "write" on BCTRL is already done.

Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32700
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10 15:15:28 +00:00
Elyes HAOUAS c9f6bd9085 sb/i82801gx: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not
apply to this PCI bridge because it is only defined for
"Header type 0 (normal devices)" (line 82).

BCTRL registry for D30:F0 is defined at offset 0x3e for i82801gx
(see ICH7 Family Datasheet page 355).
The write on that register is already done some lines above.
So remove wrong register name and the wrong code line.

Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-10 15:15:14 +00:00
Arthur Heymans 9d9ce62ae9 mb/google/nami: Add VBT blobs and include them in cbfs
Add vbt files for nami variants and select Kconfig option
to utilize them. The default vbt is automatically added
by the Kconfig selection and so does not need to be
specified in the makefile with the others.

Test: boot vayne and akali nami variants, verify
display functional and correct vbt loaded.

Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-10 15:14:32 +00:00
Bonnie Lin 1360b9a73f mb/google/sarien/variants/arcada: Set tcc offset value
Set tcc offset value to 1 degree celsius for Arcada system.

BRANCH=None
BUG=b:122636962
TEST=Built and tested on Arcada system

Signed-off-by: Bonnie Lin <bonnie_ty_lin@wistron.corp-partner.google.com>
Change-Id: I3ca4be2f7b92e29fb133ecc32023526b177d2ac2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-05-10 15:14:19 +00:00
Dtrain Hsu bddfa59f1d mb/google/hatch: Fine tune Goodix touch screen timing
According to Goodix GT7375P datasheet, reduce Goodix touch screen timing.

BUG=b:129727745
BRANCH=None
TEST=local build and tested with Goodix touch screen worked under
coldboot (10 times), warmboot (10 times), S3 (10 times).

Change-Id: I4bf081bab5e89d3ce336c6432da5ba71279fa98d
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-05-10 15:14:08 +00:00
Furquan Shaikh 2de7af0c39 mb/google/hatch: Fix GBB_HWID for kohaku
This change fixes the typo in CB:32161 (mb/google/hatch: Add Kohaku
board) that defaults GBB_HWID incorrectly for kohaku using
BOARD_GOOGLE_HATCH_WHL.

Change-Id: I387879619ac4f79fad422e5f1f047dfe3c7b5b22
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32690
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10 15:13:46 +00:00
Elyes HAOUAS 32b9a99e16 nb/intel/i945: Use macro instead of magic number
Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31027
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10 15:13:33 +00:00
Kevin Chiu 8ed01a0e31 mainboard/google/kahlee: Fix Micron MT40A512M16TB-062E:J SPD CRC error
Correct Micron MT40A512M16TB-062E:J SPD CRC to 0x5330 to fix post hang
in AGESA TestPoint:05 TpProcMemSPDChecking.

BUG=b:127394249
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>

Change-Id: I8fa49e6e938b3195945b3199438cc53f3e9c92e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-10 15:13:20 +00:00
Michał Żygowski 1119428693 soc/intel/braswell/smbus: Enable early SMBus in romstage
Enable early SMBus support compatible with SPD library using Intel SB
common SMBus API.

TEST=boot Protectli FW2B with new FSP, MemoryInit should pass without
errors

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-10 15:13:07 +00:00
Elyes HAOUAS 4feaf6b7b8 sb/i82801gx: Remove duplicated 'define PMBASE'
Change-Id: If08bea821043bc8e661bf5327f4fe2cef3a65be8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-10 15:12:29 +00:00
Lijian Zhao d5d89c8a55 soc/intel/cannonlake: Fix pcie clock number
Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have
total 16 pcie clocks. It is different with pcie root port numbers.

BUG=CID 1381814
TEST=Build and boot up fine on sarien platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-05-09 18:05:00 +00:00
Duncan Laurie 643daed6b5 vendorcode/google/chromeos: Use explicit zero check in ACPI code
The ASL 2.0 syntax for "!X" resolves to "LNot(X)" which will evaluate
the object as an integer and turn into a boolean.  This may not do the
right thing if the object is actually a string and it can lead to
unexpected behavior.

Instead be specific about the object type and check for zero or an
empty string depending on what is being returned.

This fixes an issue where some VPD keys were causing the search to
stop and miss subsequent entries.

Change-Id: I1688842964f9c2f81ca31073da9c2d71a8c81767
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-09 15:34:53 +00:00
Ronald G. Minnich 24047fefda Change the guard for bootblock_systemagent_early_init to ENV_BOOTBLOCK
The definition of bootblock_systemagent_early_init was guarded by
!ENV_RAMSTAGE. But it's only called in the bootblock. So guard it
with ENV_BOOTBLOCK instead.

Change-Id: I143cf72e4a63b176e4772575e7a60a2a611e4ad9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-05-09 14:59:39 +00:00
Joel Kitching 2eb89c8b14 vboot: include vb2_sha.h when required
Should include vb2_sha.h header when SHA library functions or
constants are required.  This replaces NEED_VB2_SHA_LIBRARY.

BUG=b:124141368, chromium:956474
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1583820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-09 06:32:44 +00:00
Joel Kitching 5923d67cfd vboot: communicate display requirements with vb2api_fw_phase1
Input: tell vb2api_fw_phase1 if display unconditionally available
Output: vb2api_fw_phase1 may request coreboot to initialize
        display, if needed based on some internal request

Move setting the VBOOT_FLAG_DISPLAY_REQUESTED flag into
verstage_main.

BUG=b:124141368, b:124192753, chromium:948529
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I81c82c46303564b63b8a32e7f80beb9d891a4628
Cq-Depend: chromium:1564232
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-09 06:32:26 +00:00
Joel Kitching 9e8cf3cc86 vboot: remove use of VbInitParams
The VbInitParams struct will be deprecated.  Remove its
use in preparation.

Additionally, remove use of the flag
VB_INIT_OUT_ENABLE_USB_STORAGE, which is no longer used
downstream since vboot_reference CL:347257.

BUG=b:124141368, chromium:960226
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ibe02cb6ba639de0d7cbdf79fc4dbf49044c92278
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1583943
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32664
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-09 06:31:57 +00:00
Lijian Zhao 0a433db22c mb/google/sarien: Move EC PTS/WAK function to mainboard
Move optional EC PTS and WAK function into mainboard level.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie91a8168ae234f4fb4843c8587c77ae2f74aeb81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-09 00:25:44 +00:00
Lijian Zhao c7817bc128 soc/intel/common/acpi: Remove EC PTS/WAK dynamic loading
Use CondRefOf to replace config optios for PTS/WAK acpi method dynamic
loading. Then we can move EC PTS and WAK method to be under mainboard.

BUG=N/A
TEST=Build sarien source code, check build/dsdt.dsl have EC.PTS method
included, build whlrvp soure, check build/dsdt.dsl don't have EC.PTS
method. Both able to build pass.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I9f4bd7240832caf070e65039e4ba2d8656371da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32371
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-09 00:25:35 +00:00
Mike Hsieh b3ddb29c36 mb/google/sarien/variants/arcada: Update thermal configuration for DPTF
Update dptf for arcada DVT1.

BUG=b:123924662
TEST=Built and tested on arcada system

Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com>
Change-Id: Ia8024a69547a569d288e02931190a98676eeaab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-08 19:35:19 +00:00
Patrick Rudolph 49df54a1dc mb/lenovo/t520: Fix devicetree
Disable unused PCI devices.
Reduces idle power by around 0.5Watt.

Tested on Lenovo T520.

Change-Id: I6990dc5810084261b75d2a327b6a103be44fd4cc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-08 14:56:12 +00:00
Marshall Dawson 976e3e9ae6 soc/amd/stoneyridge: Add iomux read/write functions
Add functions to read and write the region in the AcpiMmio block.
Convert gpio.c to use them instead of creating pointers.

Change-Id: I2a0f44b6ec7261648cf0357b44a6c18dd40d1504
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08 13:50:04 +00:00
Marshall Dawson b4b9efcfdd soc/amd/stoneyridge: Finish read/write misc registers
Add 16 and 32-bit versions of read / write_misc functions.  Find one
access of the MISC block still using read8() and write8(), and convert
it.

Change-Id: I296c521ea7f43210db406013bbe79362545ce6f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08 13:49:45 +00:00
Marshall Dawson b435d4405d soc/amd/stoneyridge: Add aoac_ read/write functions
Add 8-bit functions to access the AOAC registers and use them in
southbridge.c.  At this time, there is no reason to pursue WORD or
DWORD access and it's not known if those transaction sizes are
supported.

Change-Id: I3a8f493625f941fb855c0b8a0eff511a9a5ddfe8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08 13:49:29 +00:00
Marshall Dawson 753c225c2c soc/amd/stoneyridge: Rewrite smbus_read/write, add asf
Convert smbus_read8() and smbus_write8() functions to use the same
arguments as the other AcpiMmio blocks, and add 16 and 32 bit versions.
Add matching functions for the ASF controller.

Change-Id: I3b0ecf21f20472245da98ab5e711a54e99dca93a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08 13:49:09 +00:00
Marshall Dawson 6ac87c4986 soc/amd/stoneyridge: Rearrange sb_util.c
In preparation to move code to a common directory, rearrange some of
the functions in sb_util.c.  Add various comments.  This change should
have no functional differences.

Change-Id: I1ad55a4a14a27e45459dcaf2fcc7449e29da6d4b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-05-08 13:48:46 +00:00
Marshall Dawson 5de4771360 soc/amd/stoneyridge: Rename AcpiMmio blocks
A subsequent patch will move the AcpiMmio support into amd/common.
Take this opportunity to rename the blocks in the 0xfed8xxxx region
with more consistency.

Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08 13:48:31 +00:00
Patrick Rudolph fe80bf2fd1 Documentation: Convert vboot to markdown
Convert the HTML document to markdown and place it under security section.

Change-Id: I212c6d0c977fd6772371ff6676478d48cc215d6e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32610
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-08 10:33:44 +00:00
Patrick Rudolph 62bc1cb88b mb/lenovo/*: Add support for VBOOT on 8MiB devices
Enable VBOOT support on all devices that have a 8 MiB flash, using a
single RW_MAIN_A partition, allowing the use of tianocore payload in
both RW_MAIN_A and WP_RO.

* Add VBNV section to cmos.layout
* Add FMAP for VBOOT and regular boot
* Select Kconfigs for VBOOT
* Enable VBOOT_SLOTS_RW_A by default

Also build test VBOOT on Lenovo T420.

Tested on Lenovo T520 using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6.

Change-Id: Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-08 10:31:23 +00:00
Patrick Rudolph 2521211753 ec/lenovo/h8: Add VBOOT board support
Use Fn-Key as recovery mode switch.

Tested using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6.

Change-Id: I2c682431b3f09839db265259205104bd9ef4abfc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-08 10:27:36 +00:00
Patrick Rudolph 2dc00fab7c ec/lenovo/h8: Add function to query sense state
* Add function to wait for sense registers to become valid.
* Add function to retrieve Fn-Key state.

Tested on Lenovo T500:
* It takes about 700msec for the registers to become valid.

Tested on Lenovo T520:
* It takes less than 150msec for the registers to become valid.

Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-08 10:26:35 +00:00
Elyes HAOUAS 1d3b3c3c09 {src,util}: Remove duplicated includes
Change-Id: Id09cec6b2aae58b131b208e96fec539d068ff68a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-07 16:15:56 +00:00
Patrick Rudolph 052163236c mb/lenovo: Add SMBIOS type 9 for ExpressCard
Mark all known PCIe root ports as ExpressCard slot.

Tested on Lenovo T520.

Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32309
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07 16:06:55 +00:00
Lijian Zhao d694f6e21b mb/google/sarien: Add SMBIOS type 9 fields
Fill SMBIOS type 9 fields for both sarien and arcada platform.

BUG=b:129485789
TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-07 16:06:39 +00:00
Patrick Rudolph f5b9369720 smbios: Walk over PCI devicetree to fill type 9
Use the devicetree values for type 9 slots.

Tested on Lenovo T520.

Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-07 16:05:53 +00:00
Patrick Rudolph bd7739f3aa device: ignore NONE devices behind bridge
Ignore NONE devices in dev_is_active_bridge that are commonly used to
indicate hotplug capable ports.

Tested on Lenovo T520:
The empty ExpressCard Slot is no longer marked as active bridge.

Change-Id: I23347270aaab17647023969091ce4bcdd41dd57a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-07 16:05:27 +00:00
Patrick Rudolph ac24d3c311 sconfig: Add SMBIOS type 9 entries
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.

smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)

Example:

    device pci 1c.1 on
        smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
    end # PCIe Port #2 Integrated Wireless LAN

Tested on Lenovo T520.

Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-07 16:04:56 +00:00
Dan Elkouby 1a93058448 sb/intel/bd82x6x: Fix flashconsole after lockdown
SMM final locks the SPI BAR, which causes flashconsole to hang.
Re-init it like SMM does with CONFIG_SPI_FLASH_SMM.

Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 16:04:07 +00:00
Maxim Polyakov 3ba380797b soc/intel/skylake: remove PrimaryDisplay check
Checking the PrimaryDisplay parameter (added by patch with Change
Id Ie3f9362676105e41c69139a094dbb9e8b865689f) isn`t required. The
display connected to PEG works  even if IGD is primary for output
image and at the same time this device is disabled

Tested on Asrock H110M-DVS with NVIDIA GTX 1060 GPU
Payload: tianocore edk2-stable201811-216-g51be9d0

Change-Id: I5615597881a151bb004676d914fbf40874ac1f68
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32615
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07 16:03:01 +00:00
Maxim Polyakov d7d0b04d3a soc/skl/memmap: calculate mem size even if IGD undefined in devtree
The DRAM base memory should be calculated even if IGD isn`t defined
in the board device tree

Tested on Asrock H110M-DVS

Change-Id: I3da51473e6c06da803bd969a4a6dff792c18f962
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-07 16:02:32 +00:00
Elyes HAOUAS 551a75923e sb/{ICH7,NM10,PCH}: Use common watchdog_off function
Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
2019-05-07 16:01:35 +00:00
Jiaxin Yu 30bc9f415d google/kukui: Support sound in boot process
Configure and enable GPIO for speaker amp max98357a.

BUG=b:117254418
TEST=Build pass and verified on kukui p1 board
BRANCH=None

Change-Id: I97655702dff402245326d2eff71fae0e336df9f5
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-07 16:00:31 +00:00
Nico Huber 3c0d23b6ab intel/fsp1_1: Drop remnants of `pei_data`
`pei_data` was a struct with blob parameters from pre-FSP times.
Somehow, it sneaked into upstream FSP1.1 support (probably because
early board ports were written for a different blob). When added
upstream, its usage was already perverted. It was declared at SoC
level but mostly used to pass mainboard data from mainboard code
to itself and FSP data from FSP code to itself. Now that no board/
SoC code uses it anymore, we can finally drop it.

Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:59:10 +00:00