This patch adds a pin configuration macro that supports both switching a
pin to its native function and configuring it as a SCI source. This is a
preparation to remove the GPIO2 soc_gpio_hook.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If0da5c010f35fd902f6b8857368daec93c12394a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50373
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Caroline has a Wacom W9013 digitizer on I2C2, which was
incorrectly disabled in commit d957d12e6
[mb/google/glados: clean up variant devicetrees]
as part of preparation for converting to overridetree format.
Test: build/boot, verify digitizer now available under Linux
Change-Id: I234bc0126b5d13c22a663d6544382890b312ce63
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Add correct board Id for ADL-M LP5 configuration
2. Add spd hex files for LP5 Micron part
3. Update memory.c file with correct Dq-dqs and byte mapping for LP5
BUG=None
BRANCH=None
TEST=Build is successful for ADL-M RVP
Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
List of changes:
1. Add separate file for ADL-M GPIOs
2. Configure GPIOs as per the schematics of ADL-M RVP
TEST=Able to build ADL-M
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.
TEST=Verified build for Shadowmountain
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2ebf4da1b8c1df2e9c43b6e3bb688a9f8db652d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51496
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.
TEST= Built and booted on ADL-P LP4 RVP
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some tested modules require regions to be defined but do not necessarily
access them. TEST_REGION_UNALLOCATED() combined with DECLARE_REGION()
are sufficient for most cases that require symbols only.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I51c5f6ce56575021c6e4277a9ed17263cd2e3bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51769
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support zinitix touchpad for sasuke.
BRANCH=dedede
BUG=None
TEST=built and checked touchpad worked on sasuke
Change-Id: I85794311c49e33c4683482e125bea5ca2dbacfa8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add an option to generate the Key Manifest from Kconfig options.
Change-Id: I3a448f37c81148625c7879dcb64da4d517567067
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50410
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This add an option to generate KM using the 9elements bg-prov tool
using a json config file.
The option to just include a provided KM binary is kept.
A template for the json config file can be obtained via
"bg-prov template".
Another option is to extract it from a working configuration:
"bg-prov read-config".
Change-Id: I18bbdd13047be634b8ee280a6b902096a65836e4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50409
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Private and/or public keys will be provided as user input via Kconfig.
As a private key also contains the public key, only ask what is required.
Change-Id: I86d129bb1d13d833a26281defad2a1cb5bf86595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
ANX7625 requires customized hs_da_trail time.
So override the data trail for ANX7625.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Jacuzzi
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I620035363507daaa19e3c272a44059c17be29af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
There's no need to use a fixed-width type here.
Change-Id: I727c64661990040db356c5508fecc0a65960c095
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51794
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The correct printf format specifier for an `unsigned int` is `%u`.
Change-Id: Iaf780eb366f8c3493b89beb9a5643fa285e7825d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51793
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We use `additional-dirs` for a single `mkdir -p` invocation for all
directiories. I don't see why these two, $(objcbfs) and $(objgenerated),
should be an exception.
Fixes clean builds for targets that don't include the phony `coreboot`
target, e.g. `make qemu`.
Change-Id: I85abaa74cddefd2bd669e2b5c8934352775070fe
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There's no need to write the GDCRTRAININGRESULT registers after raminit.
Change-Id: If604920fe7a3bee96f72f8aff5e96f0e25548f18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50534
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ANX7625 requires the line packets to end at the same time.
Otherwise, the display will be shifted.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Jacuzzi
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch allows overriding GPIO PM miscconfig register for each
GPIO community to avoid dynamic clock gating.
TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0]
are set to '0'.
Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Lists of changes:
1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS
2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to
soc/gpio.h. Refer to detailed description below to understand the
motivation behind this change.
An advanced GPIO PM capabilities has been introduced since CNP PCH,
refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions.
Now with TGP PCH, additional bits are defined in the MISCCFG register
for GPIO PM control. This results in different SoCs supporting
different number of bits. The bits defined in earlier platforms
(CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the
common GPIO code to keep the bit definitions in intelblock/gpio.h, but
the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so
that each SoC can provide this as per hardware support.
TEST=On ADL, TGL and JSL platform.
Without this CL :
GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)
With this CL :
GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)
Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
List of changes:
1. Update GPIO Group to GPE DWx assignment encoding as per MISCCFG
register per GPIO Community.
2. PMC_GPP_* macros are also updated as per GPIO_CFG register
in PMC space.
BUG=b:183464235
TEST=Able to fix the TPM IRQ issue on SM.
Change-Id: Id9f57b0b5726315f5ebba013f11d52ed3ee34484
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51789
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the PCH PCI device defines out of the SOC specific PCI defines
and into a common include. The PCH is common and doesn't need
duplicate definitions.
Change-Id: I1ca931e0f01e03c67f8f65ed7fd33c2c1d22183d
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch disables the unsued CPU PCIe RP for shadowmountain.
TEST= Boot shadowmountain and verify the device is disabled.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ide2badb06178fca8ff5cf51d8573a14635e190cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51772
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, we used to stitch extra VBT files to ADLRVP build using
Makefile. With enablement of emerge build, we should be able to
integrate more than 1 VBT binaries using ebuild.
This removing these lines to avoid compilation issues in emerge builds
BUG=None
BRANCH=None
TEST=Check if compilation passes on emerge build. Stitched additional
VBT files using emerge and checked that coreboot picks up correct VBT.
Change-Id: I69f1cc6c07415515ff85180fdd7cc5de11b4d805
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This patch adds a bit of a "preamble" to the coding style to provide
guideance on how it should be applied and how style questions that
aren't mentioned should be handled.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I88efd5f1006bd1fd82cea14ea65422d9958dc197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add function to allow overriding the RcompResistor and
RcompTarget UPDs from mainboard if required.
Mainboard users can pass required rcomp from memory.c file.
Refactor ddr_config structure to take out rcomp related variable
outside for all memory type to override if required.
BUG=b:182772421
TEST=Able to override the default RcompResistor and RcompTarget
values.
Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Alder Lake MRC is expecting a RcompResistor value of word width.
Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot
is passing an array of RcompResistor which is not completely in use.
Note: Rcomp resistor value represents rcomp resistor attached to
the DDR_COMP pins on the SoC.
2. Also, remove usage of '&' with memcpy the required value into
RcompTarget array.
3. Also, update RcompResistor value for ADLRVP.
BUG=b:183341229
TEST=Enable FSP debug log to verify the override value for
RcompResistor is reflecting correctly.
Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
MEC1701 can be accessed by IO port 2E/2F
Change-Id: I31f1b147476ec487e64f3c30b3cf514b45ced416
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Set default USB2 HS disconnect threshold to maximum to avoid false
disconnects that eventually lock up the xHCI controller
BUG=b:174538960
TEST=suspend_stress_test -c 50 on vilboz and morphius.
Sample set of USB2 HS devices connect and disconnect
successfully
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ic921d850a0bdd717a2a7e50e9e6f65e39e0607bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51265
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 4f87ae1d4a introduced a regression
in the I2C initialization resulting in soc_i2c_misc_init never getting
called, since the continue statement was indented like it belonged to
the if above, but due to the missing curly braces it was outside the if
block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Coverity CID 1451395, 1451387
Change-Id: Id1f17ad59cba44e96881f5511df303ae90841ab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51786
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous "PCIe port" numbering was incorrect and resulted in several
PCIe devices failing to enumerate. With lane reversal, these numbers are
all backwards. This explains the confusing mapping of Clock Source #1 to
Root Port #9 in https://review.coreboot.org/c/coreboot/+/50101. We were
confusing "Root Port" vs "PCIe Lane".
This change addresses the port vs. lane confusion in the device tree
configurations. It also adds more detailed documentation to a future
reader (i.e., me) to avoid this blunder.
BUG=b:181633452,b:181635072,b:177752570
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: I47edf0b0af1bdcf86b89f17ad2a1f128ef9e9f7a
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
After revisiting the genesis GPIO table and schematics for EVT closure,
I discovered several missing and/or incorrectly documented GPIO pin
mappings.
Now the GPIO pin names and functions should match what's written in the
latest schematics.
BUG=b:181633452,b:181635072,b:177752570
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: I73e6733bce761b00717091834c7a49e85154f80b
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51677
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both EHCI and xHCI USB controllers are inside the PCH (southbridge).
Now that mainboard USB configuration no longer depends on pei_data.h
definitions, the API declarations can be placed in southbridge code.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ia21991b225482b33c5bc0dc52884674d301b28ba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With this change, only raminit.c uses pei_data.h definitions. With MRC
cornered, making it optional is just a matter of writing a replacement.
USB config definitions will be moved to Lynx Point code in a follow-up.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/collis/memory/ src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt
DRAM Part Name ID to assign
MT53D512M64D4NW-046 WT:F 0 (0000)
H9HCNNNCRMBLPR-NEE 0 (0000)
MT53D1G64D4NW-046 WT:A 1 (0001)
H9HCNNNFBMBLPR-NEE 2 (0010)
BUG=b:182227204
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I773c65c0b6d5e868572530305ab8a61a0dd1532d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. H9HCNNNBKMMLXR-NEE
2. MT53E512M32D2NP-046 WT:F
3. K4U6E3S4AA-MGCR
BUG=b:183057749
BRANCH=dedede
TEST=Build the cret board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iacfdd9a27f126ba4b97d1a6493bcc09bb31454a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51619
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow schematic to modify USB port settings.
USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 0
USB2 [3]: LTE
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: Camera WFC
USB2 [7]: Integrated Bluetooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: LTE
BUG=b:182973703
BRANCH=dedede
TEST=Build the coreboot image.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I80447d6ac3422f858a9022f550b4f42353819405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add a helper bit mask to enable wake from either S0i3 or S3.
BUG=None
TEST=Build the Guyrbush mainboard.
Change-Id: I934abad78135260081a61aee4c496b362e483de1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The 'device pci 00.0 on end' entries are not necessary for socketed
devices unless a chip driver needs to be bound to a device, so remove
them from the devicetree. Also remove the `drivers/wifi/generic` chip
driver as it was not necessary either.
Change-Id: Id5f2e34d98b236f9cfac9f0afd8a8017e349603f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change allows guybrush EC communication while other patches
in the SOC code are worked on.
BUG=b:183149183
TEST=Boot guybrush with EC comunication
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I56fb64d4c065cf0665025346218cc66d77dacb52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51665
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Felix Held