To allow retraining memory without hotkey (for example in manufacturing
process), we want to enforce re-training when the recovery reason is set
to VB2_RECOVERY_TRAIN_AND_REBOOT (which can be done by running
"crossystem recovery_request=0xc4").
The special reason was created for X86 MRC cache, for ensuring RO
calibration data is filled (the underlying implementation was in vboot,
not coreboot); and on MT8183 we have only RW calibration, but it seems
totally fine to extend that for RW.
BRANCH=kukui
BUG=None
TEST=boots; crossystem recovery_reason=0xc4; reboot
Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Similar to MRC cache on x86 platforms, when a hotkey is pressed during
boot, the calibration data cache saved in the flash will be cleared,
consequently triggering DRAM retraining (full calibration) in the next
boot.
BRANCH=kukui
BUG=b:139099592
TEST=emerge-kukui coreboot
Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
SoC DRAM team suggested always running full calibration mode in recovery
mode because it is possible to get unstable memory even if the complex
memory test has been passed.
Since the recovery mode runs from RO and we only have training data
cache for RW, the trained calibration data can't be saved since RO and
RW may be running different firmware.
Also revised few message to make it more clear for what calibration mode
(fast, full, or partial) has been executed.
BRANCH=kukui
BUG=b:139099592
TEST=emerge-kukui coreboot
Change-Id: I29e0df71dc3357462e15ce8fc2ba02f21b54ed33
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
The DRAM calibration blob can be compressed using pre-RAM algorithm
(currently LZ4), which will save ~12ms in boot time.
On Kodama, boot time difference:
Before: 1,082,711
After: 1,070,309
BUG=b:139099592,b:117953502
TEST=build and boot, cbfstool coreboot.rom print -v (see dram compressed)
BRANCH=kukui
Change-Id: Ic3bd49d67ee6f80a0e4d8f6945744642611edf64
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
To make data flow more explicit, global variable 'impedance' is replaced
with a local variable, which is passed as a function argument.
BUG=none
BRANCH=kukui
TEST=Krane boots correctly
Change-Id: I0f6dacc33fda013a3476a10d9899821b7297e770
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
The patch adds config MT8183_DRAM_DVFS to enable DRAM calibration with
multiple frequencies to support DVFS switch.
BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I97c8e513dc3815a2d62b2904a246a1d8567704a4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch supports voltage adjustment for each DRAM frequency, which is
neccesary to support DVFS switch.
BUG=b:80501386,b:142358843
BRANCH=none
TEST=Boots correctly and stress test pass on Kukui.
Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
DRAM DVFS needs to be calibrated with different vddq voltages to get
correct parameters.
A new API is added to allow changing vddq voltage.
BUG=b:80501386
BRANCH=none
TEST=measure vddq voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35147
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DRAM DVFS needs to be calibrated with different vdram1 voltages to get
correct parameters.
A new API is added to allow changing vdram1 voltage.
BUG=b:80501386
BRANCH=none
TEST=measure vdram1 voltage with multimeter
Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33186
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most coreboot debug messages are sent to UART and cbmem console, and we
also want to collect DRAM calibration module output, especially for
cbmem console (so we can see the logs after kernel is up).
Instead of sharing whole cbmem/cbtable/cbmemconsole implementations, we
want to simplify that by a simple function pointer so output can be
preserved by do_putchar, which internally sends data to all registered
consoles (usually cbmem console and UART).
BUG=b:139099592
TEST=make; boots properly for full-k, with and without serial console.
BRANCH=kukui
Change-Id: I1cf16711caf3831e99e17b522b86694524425116
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36056
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The checksum is stored in the header of calibration data and saved to
SPI flash. After reading the data from flash, checksum is used to verify
the integrity of the calibration parameters.
BUG=b:139099592
BRANCH=kukui
TEST=Calibration data successfully loaded from flash
Change-Id: Ie4a0688ed6e560d4c0c6b316f44e52fd10d71a9d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
In broadcast mode we only need to set registers for channel 0
instead of all channels.
BUG=none
BRANCH=kukui
TEST=emerge-kukui coreboot
Change-Id: I22a4b69fd40d1978fa7b12e8edaba00ce5d7787d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Replace the magic clrsetbits_le32, read32, write32 by SET_BITFIELDS and
other bit field helpers.
Change-Id: I327297dd10718fbef7275fe95c95d00d3ab6ac84
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35471
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If DRAM calibration fails or mem test fails using the cached calibration
results stored in flash, rerun DRAM full calibration. If partial
calibration fails or the mem test following it fails, hang forever.
Partial calibration acts as a fallback approach in case of full
calibration failure. Therefore, if it fails, there would be no other
ways to initialize DRAM. Instead of falling into reboot loop and
draining out of battery, it is better to just hang so that the end user
may notice that and send to RMA.
BUG=b:80501386,b:139099592
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I8e1d4f5bc7b45f45a8bfef74e86ec0ff6a556af4
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35481
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since struct dramc_param has been defined, we can pass the struct
directly from mt_mem_init().
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: If7333fb579eff76dd9d1c2bf6fdfe7eccb22050f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35846
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load the calibration params from flash first and check the correctness
of the params. If the params have correct format, perform DRAM fast
calibration with these params to reduce bootup time. Otherwise, load the
DRAM blob and perform DRAM full calibration.
Bootup time of DRAM partial calibration:
- 1,349,385 usecs with low frequency
- 924,698 usecs with middle frequency
- 1,270,089 usecs with high frequency
3,544,172 usecs in total.
Bootup time of DRAM fast calibration:
- 216,663 usecs with low frequency
- 328,220 usecs with middle frequency
- 322,612 usecs with high frequency
867,495 usecs in total.
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Load calibration params from flash. If the format of the params is
correct, use these calibration params for fast calibration to reduce the
bootup time.
Bootup time of DRAM partial calibration:
- 1,349,385 usecs with low frequency
- 924,698 usecs with middle frequency
- 1,270,089 usecs with high frequency
3,544,172 usecs in total.
Bootup time of DRAM fast calibration:
- 216,663 usecs with low frequency
- 328,220 usecs with middle frequency
- 322,612 usecs with high frequency
867,495 usecs in total.
BUG=b:139099592
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dramc_param module simplifies the communication between coreboot and
MTK DRAM full calibration blob, and is shared by both implementations to
ensure the same format of parameters.
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Since we always write to &ch[chn].ao.dummy_rd after calling
dramc_engine2_end(), this write could be merged into dramc_engine2_end()
to simplify code.
BUG=none
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: Ibb4bd5ed016118811ad2097098417c19f00f4263
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35749
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Two fields of struct sdram_params are renamed for future CL of DRAM full
calibration. Field 'impedance' is also removed.
BUG=none
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be
calibrated with different vcore voltages to get correct parameters.
A new API is added to allow changing vcore voltage.
BUG=b:80501386
BRANCH=none
TEST=measure vcore voltage with multimeter
Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33391
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support mt8183 power saving during suspend to RAM, this patch loads
SPM firmware to support SPM suspend. SPM needs its own firmware to do
these power saving in the right timing under correct conditions. After
linux PM suspends, SPM is able to turn off power for the last CPU and do
more power saving for the SoC such as DRAM self-refresh mode and turning
off 26M crystal.
BUG=none
BRANCH=none
TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps)
while those with discrete DRAM can only run at 3200Mbps. This patch
enables 3600Mbps for eMCP DDR for better system performance.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test passes on Kukui
Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps,
2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386
BRANCH=none
TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch implements the dram init setting by replacing the hard-coded
init sequence with a series of functions to support calibration for more
frequencies. These functions are modified from MediaTek's internal DRAM
full calibration source code.
BUG=b:80501386
BRANCH=none
TEST=1. Kukui boots correctly
2. Stress test (/usr/sbin/memtester 500M) passes on Kukui
Change-Id: I756ad37e78cd1384ee0eb97e5e18c5461d73bc7b
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Set BL31 platform to mt8183 to link with ARM Trusted Firmware.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui with more patches in ATF.
Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbs)
while those with discrete DRAM can only run at 3200Mbps. A new option
MT8183_DRAM_EMCP is added to Kconfig for a mainboard to select,
depending on whether it supports eMCP or not.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9b73c8b512db5104896ea0d330d56e63eb50a44b
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Consider the association between modem[1] and DCXO, this patch is a fix for
eb5e47d("mediatek/mt8183: update dcxo output buffer setting") [2]
We should not disable XO_CEL and block the bblpm request when modem is still ON.
For power-saving, we still could disable unused XO_CEL and
mask request to disable unused power mode when modem is no longer be used.
[1] https://review.coreboot.org/c/coreboot/+/32666
[2] https://review.coreboot.org/c/coreboot/+/32323
BRANCH=none
TEST=Boots correctly on Krane.
Change-Id: I047ebed615e874977ca211aafd52b5551c71b764
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Enlarge PRERAM_CBFS_CACHE region from (16K - 4) to (48K - 4) bytes to
decompress and load more data from CBFS in romstage.
BUG=b:134351649
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34896
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since SRAM space is too small to fit all needed features, enable
VBOOT_RETURN_FROM_VERSTAGE and overlap decompressor, verstage and
romstage to gain more space.
BUG=b:134351649
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: Ibe336cf93b01fa2ea57b4c2e0a89685424878c91
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34871
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards (e.g., Kukui) need GPIO based CS for SPI0. This patch
changes the pinmux and binds the pins to the correponding SPIs.
When using GPIO based SPI CS, we need to manually make CS log/high
before/after SPI transactions.
BUG=b:132311067
BRANCH=none
TEST=Verified that b/132311067 is irreproducible
Change-Id: I61653fb19242b6ee6be9a45545a8b66e5c9c7cad
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The MT8183 display serial interface (DSI) is based on MIPI
Alliance Specification, supporting high-speed serial data
transfer between host processor and peripheral devices such
as display modules.
DSI supports both video mode and command mode data transfer
defined in MIPI spec, and it also provides bidirectional
transmission with low-power mode to receive messages from
the peripheral.
Reference: MT8183 Application Processor Functional Spec,
6.7 Display Serial Interface (DSI)
BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The MT8183 SOC has a DISP (display controller) that supports
overlay, read/write DMA, ... etc. The output of DISP goes to
display interface DSI, DPI or DBI directly.
Reference: MT8183 Application Processor Functional Spec,
6.1 Display Controller
BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch implements i2c driver for MT8183.
BUG=b:80501386
BRANCH=none
TEST=Boot correctly on kukui.
Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30976
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load SSPM firmware and boot up SSPM.
BUG=b:80501386
BRANCH=none
Test=We can see "SSPM is alive" in ATF stage if SSPM enabled and ipi success
Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31835
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SRCCLKENA holds 26M clock, which will fail suspend/resume,
and the SRCCLKENA is not used by mt8183,
so we can simply release it for suspend/resume to work.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui, suspend test pass.
Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082
Signed-off-by: Yanjie.jiang <yanjie.jiang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32666
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.
BUG=b:80501386
BRANCH=none
Test=Build pass
Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31516
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Calibrate RTC eosc clock which will be used when RTC goes into
low power state.
BUG=b:133872611
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ie8fd6f4cffdcf7cf410ce48343378a017923789c
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
DCXO consists of core that generates clock and output buffers that
provide clock to other peripheral components.
This patch mainly eliminates the extra power consumption of output buffers.
We only enable the buffer for SOC and disable unused buffers for power-saving.
Also disable useless buffer power mode to guarantee the lowest power state.
BRANCH=none
TEST=Boots correctly on Kukui.
Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32323
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When system shuts down, RTC enable eosc calibration feature to save
power. Then coreboot RTC driver needs to call rtc_enable_dcxo function
at every boot to switch RTC clock source to dcxo.
BUG=b:128467245
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
