Commit Graph

30591 Commits

Author SHA1 Message Date
Mathew King c7ddc999fc ifdtool: Add validate option to ifdtool
Add an option to ifdtool which validates that the flash regions defined
in the descriptor match the coresponding areas in the FMAP.

BUG=chromium:992215
TEST=Ran 'ifdtool -t' with a good bios image and verify no issues
     run 'ifdtool -t' with a bad bios image and verify expected issues

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 15:28:15 +00:00
Patrick Georgi 006eb9d8c8 libpayload: refactor fetching cbmem pointers
There's a recurring pattern of reading cbtable entries that point into
cbmem entries. Move that pattern into its own function.

Coccinelle patch used for this:
  @@
  identifier T, T2;
  expression TARGET;
  @@
  -struct cb_cbmem_tab *const T2 = (struct cb_cbmem_tab *)T;
  -TARGET = phys_to_virt(T2->cbmem_tab);
  +TARGET = get_cbmem_ptr(T);

Change-Id: I7bd4a7ad8baeeaebf0fa7d4b4de6dbc719bc781f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 15:27:30 +00:00
Petr Cvek c49869b424 sb/intel/i82801gx: Use symbolic name for register, code rework
An original code had a wrong register address 0x27 for AHCI BAR.
The value was aligned incidentally by the code specific of
the pci_read_config32 function to the correct address 0x24.

All 0x24 values in sata.c were changed to the symbolic name
PCI_BASE_ADDRESS_5 and the code was optimized.

An equivalent code was tested on a real hardware.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35737
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03 15:24:42 +00:00
Frans Hendriks be81685887 mb/facebook/fbg1701/devicetree.cb: Use 64MB framebuffer size
Connected 4K monitor is not configured at max resolution. The
framebuffer size is too small.

Increase the framebuffer size to 64MB. This is sufficient for max
configuration of 1 HDMI monitor combined with internal LCD panel.

BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701

Change-Id: I25d2cd696830fc5bda84ea2b87538f526373998e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-03 14:06:21 +00:00
Frans Hendriks f26a1985bf soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB
Add defines to have some more readable code for devcietree.cb.

BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701

Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-03 14:05:53 +00:00
Frans Hendriks 0b20b83b7d mb/facebook/fbg1701: Add mainboard_read_pcb_version()
PCB version is determined using inb() in actual code.

Create function mainboard_read_pcb_version to read pcb version.

BUG=N/A
TEST=Boot and verified on Facebook FBG-1701

Change-Id: I7c16627f468d84ca4ad2aab8bf9fb555f50dc23c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-03 14:04:35 +00:00
Patrick Georgi 22f009901d Update chromeec submodule to upstream master
Updating from commit id 860fe2962:
2018-12-29 05:45:29 -0800 - (mt_scp/ipi: Support host command.)

to commit id a1afae4e0:
2019-10-02 11:47:45 +0000 - (juniper: initial setup)

This brings in 1723 new commits.

Change-Id: Ieb4f00b21a4354bb634c3427c73260123b54ac2a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 04:43:36 +00:00
Patrick Georgi 4685e53fe6 Update opensbi submodule to upstream master
Updating from commit id ce228ee:
2019-07-02 11:11:08 +0530 - (include: Bump-up version to 0.4)

to commit id e561c63:
2019-10-02 17:03:58 +0530 - (lib: Fix coldboot race condition observed on emulators/simulators)

This brings in 44 new commits.

Change-Id: Ide6e3c2bb98e79750b40a9b8ca9f2f1d2c123628
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 04:43:28 +00:00
Patrick Georgi 193eefb2e8 Update vboot submodule to upstream master
Updating from commit id e6700f4c:
2019-08-13 04:36:52 +0000 - (vboot: update vboot2 functions to use new vb2_error_t)

to commit id b2c8984d:
2019-10-01 06:01:59 +0000 - (vboot: fix compile error with MOCK_TPM)

This brings in 71 new commits.

Change-Id: Id7cefa3ad5b30c955d18e469494fec32f6f58a48
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 04:43:17 +00:00
Kyösti Mälkki d46bc60413 intel/fsp_baytrail: Drop some PCI scratchpad register definitions
These were unused and somewhat cryptic, assumed purpose was to store
pre-CBMEM timestamps in various PCI config space locations.

Change-Id: I074294446501d49a9bd3c823a2a794c33f443168
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03 03:12:31 +00:00
Martin Roth ce005dac68 util/release: add gerrit stats script
This tool downloads, caches and analyzes commits pushed to gerrit
for a specified range of commits.  Currently it only works over SSH.

Data that is printed about the range of commits:
CSV Data about each individual commit:
- Commit ID
- Commit Date
- Author
- Commiter
- Submitter
- Lines added
- Lines removed
- Title
- Reviewers

It then prints the analysis it did on the data:
- Total Commits
- Total lines added
- Total lines removed
- Total difference
- Authors - Number of commits
- Total Authors
- Authors - Lines added
- Authors - Lines removed
- Reviewers - Number of patches reviewed
- Submitters - Number of patches submitted

The script relies on a number of perl modules
which must be installed separately.

Change-Id: I74896a97b5fe370c0b08562ac85d29435e438a31
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/14225
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 02:12:45 +00:00
Stefan Reinauer f5fa96f9c3 buildgcc: Run aclocal before configure
Ubuntu 19.04 will fail looking for aclocal-1.15 if the scripts
are not regenerated because 19.04 ships with 1.16.
There are not enough eyes to roll when working with GNU autotools.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4aa9f520499930ffc984ab0b0144c9c6b2e544a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03 02:06:35 +00:00
Martin Roth f47c32a12d util/crossgcc: Add patch for __alloca missing on ubuntu 18.04
Bring this over from the HEADS repo.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I36dc9860f4c4a2675fd3fa24fa3e534215ceb43e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 02:06:30 +00:00
Kyösti Mälkki da33b75e7d intel/quark: Drop xx_DEV_FUNC
Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.

Change-Id: Ice1062d10b793dcbeb5b2ce9e2788fd3b6b6250b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02 20:14:27 +00:00
Kyösti Mälkki 85b6c66c83 intel/skylake: Refactor IRQ assignments
When creating the IRQ routing, referenced device and
function number are always of the same PCI device.

Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35735
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 20:13:55 +00:00
Kyösti Mälkki 0b4298c242 intel/pci_devs: Regroup PCI xx_DEVID entries
Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02 20:13:24 +00:00
Furquan Shaikh 3d4923d85a libpayload: Add fmap_cache to sysinfo_t
Now that FMAP is cached in CBMEM and its pointer is added to coreboot
table for quick lookup, this change adds a new member "fmap_cache" to
sysinfo_t that can be used by payloads to get to FMAP cache.

BUG=b:141723751

Change-Id: If894c20c2de89a9d8564561bc7780c86f3f4135a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02 11:26:53 +00:00
Thejaswani Putta 86cb421df6 mb/google/drallion: Disable GBE in firmware for drallion variants
BUG: None
TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com>
Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:23:45 +00:00
Kyösti Mälkki 459f493486 intel/baytrail: Replace config_of(dev) with config_of_soc()
The function does not otherwise need dev.

Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:21:27 +00:00
Kyösti Mälkki d5f645c6cd soc/intel: Replace config_of_path() with config_of_soc()
The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.

Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.

Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02 11:21:10 +00:00
Himanshu Sahdev d3d38c95b7 coreinfo/coreinfo.c: Support both lower and upper case alphabets
Modify handle_category_key to handle both upper and lower case alphabets
in the coreinfo payload.

Change-Id: I3ccbf69e90ba7824ad6ec85d2ca59aa8f40b3006
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-02 11:20:06 +00:00
Eric Lai 0f47ff1be5 mb/google/drallion: Dynamicly disable memory channel
Disable memory channel by HW strap pin. Using for factory
debug.

BUG=b:139773082
BRANCH=N/A
TEST=Rework HW strap pin and check /proc/mem_info

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:19:23 +00:00
Yu-Ping Wu cf9588040d mediatek/mt8183: Rename fields of struct sdram_params
Two fields of struct sdram_params are renamed for future CL of DRAM full
calibration. Field 'impedance' is also removed.

BUG=none
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:17:25 +00:00
Arthur Heymans 4c80425f30 sb/intel/common/smihandler: Hook up smmstore
TESTED on Asus P5QC.

Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30012
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:15:30 +00:00
Michael Niewöhner 6238563b2b soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter
Make the the FSP Parameter PchHdaVcType a devicetree setting and make
use of it in the devicetrees of all boards that currently set it.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2019-10-02 11:15:00 +00:00
Richard Spiegel 5387144a93 Documentation/mainboard/amd: Add padmelon documentation and images
Create documentation on padmelon, including how to program the SPI. Also
include an index.md pointing to the documentation, as currently there's no
maiboard documentation folder for AMD.

BUG=none.
TEST=none.

Change-Id: I1a684c1acd3fb9441df71e2bc0fffa6131148b98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-01 15:15:30 +00:00
Richard Spiegel 6453c9062b Documentation/soc/amd: Add Family 15h
Create documentation for AMD Family 15h.

BUG=none.
TEST=none.

Change-Id: Iaab4edc431329a691283121494595f3797c566c6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-10-01 15:13:29 +00:00
Hsin-Hsiung Wang 9168ab0077 mediatek/mt8183: Allow modifying vcore voltage
Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be
calibrated with different vcore voltages to get correct parameters.
A new API is added to allow changing vcore voltage.

BUG=b:80501386
BRANCH=none
TEST=measure vcore voltage with multimeter

Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33391
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-01 15:11:29 +00:00
Patrick Rudolph 6e079dc120 cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.

Will be used in MP init to only write "Core" MSRs from one thread
on HyperThreading enabled platforms, to prevent race conditions and
resulting #GP if MSRs are written twice or are already locked.

Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-01 15:10:16 +00:00
Petr Cvek 5adbc767f6 mb/kontron/986lcd-m: Add gameport base allocation workaround
A missing definition of gameport base (PNP io 0x60) will cause
an automatic address assignment during PCI/PNP enumeration, which
won't obey limit 0x7ff. This will cause the enumeration to fail
as other devices already have the values enabled.

The symptoms are: not working USB, PS/2, garbled UART console,
not working PCIe GPUs and crashes. Probably because of wrongly
assigned IO ports.

Example of log (shortened):

Done reading resources.
Setting resources...
!! Resource didn't fit !!
   aligned base 1000 size 1000 limit 2e7
   1fff needs to be <= 2e7 (limit)
   PCI: 00:1c.0 1c *  [0x0 - 0xfff] io
!! Resource didn't fit !!
   aligned base 1000 size 1000 limit 2e7
   1fff needs to be <= 2e7 (limit)
   PCI: 00:1c.1 1c *  [0x1000 - 0x1fff] io
!! Resource didn't fit !!
   aligned base 1000 size 1000 limit 2e7
   1fff needs to be <= 2e7 (limit)
   PCI: 00:1c.2 1c *  [0x2000 - 0x2fff] io
!! Resource didn't fit !!
   aligned base 400 size 10 limit 2e7
   40f needs to be <= 2e7 (limit)
   PCI: 00:1f.2 20 *  [0x3080 - 0x308f] io
!! Resource didn't fit !!
...
ERROR: PCI: 00:02.0 14 io size: 0x0000000008 not assigned
...
ERROR: PCI: 00:1f.2 10 io size: 0x0000000008 not assigned
ERROR: PCI: 00:1f.2 14 io size: 0x0000000004 not assigned
ERROR: PCI: 00:1f.2 18 io size: 0x0000000008 not assigned
ERROR: PCI: 00:1f.2 1c io size: 0x0000000004 not assigned
ERROR: PCI: 00:1f.2 20 io size: 0x0000000010 not assigned
...
PCI: 00:1b.0 subsystem <- 8086/27d8
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 8086/27d0
PCI: 00:1c.0 cmd <- 107
PCI: 00:1c.1 brids70c01mcu0PeC: 0
dV0i8s0immicrocode: upd10a00000y0025 x666600CPU physiaB 0 0 e k
MTRR cheaeu60zeAttemfWaiting for 1st Sot AP: slot 1 apic_L0ecl0zsax a
aInitiNntt kac:oIG0 Ua dUrSGSGL Ct0C07fintel_vga_int15_h
VGA Option ROM wa7..Azalia0Azalia: codkAbCiPCI: 00:1c.0 init finished

We can see the ports probably started to collide after the activation
of 00:1c.0 device. A debug run with compiled SPEW shows the problem
with enumeration:

PCI: 00:1f.1 18 *  [0x50b8 - 0x50bf] io
PCI: 00:1f.2 10 *  [0x50c0 - 0x50c7] io
PCI: 00:1f.2 18 *  [0x50c8 - 0x50cf] io
PCI: 00:1f.1 14 *  [0x50d0 - 0x50d3] io
PCI: 00:1f.1 1c *  [0x50d4 - 0x50d7] io
PCI: 00:1f.2 14 *  [0x50d8 - 0x50db] io
PCI: 00:1f.2 1c *  [0x50dc - 0x50df] io
PNP: 002e.7 60 *  [0x50e0 - 0x50e0] io		<-- gameport base
DOMAIN: 0000 io: base: 50e1 size: 40e1 align: 12 gran: 0 limit: 7ff done

Notice a weird base for DOMAIN, along with the limit.

Adding a definition of gameport (0x220) as a workaround fixes
the problems.

The gameport should be still disabled thanks to disable bits
(W83627THF datasheet is little bit chaotic). I didn't find any info
if the gameport is available on some pads of the motherboard.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: Ie8e42552ac5e638e91e5c290655edcce1f64e408
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-01 15:07:13 +00:00
Kyösti Mälkki 2647b6f9ba intel/i945: Define peg_plugin for potential add-on PCIe card
Change-Id: I06f6a7ed7a1ce935d154b8c7b11dcb81608329b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-01 01:56:17 +00:00
Kyösti Mälkki 9137cbd5e4 intel/i945: Delay bridge VGA IO enable to ramstage
Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-01 01:55:01 +00:00
Kyösti Mälkki 444d2af9a9 intel/i945: Define p2peg for PCIe x16 slot
Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-01 01:54:23 +00:00
Kyösti Mälkki df128a55b1 intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL
This is a PCI standard register, no need to alias its
definitions under different names.

Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-01 01:54:08 +00:00
Kyösti Mälkki a84a7340b6 sb/intel/bd8x62x,i82801gx: Fix PCI bridge subsystem IDs
Implementation of ich_pci_dev_enable_resources() used to have
a custom implementation to program PCI subsystem IDs for the
(legacy) PCI bus bridge.

With the local implementation removed, we no longer need the
custom .enable_resources callback.

Change-Id: I6f73fd0e4d5a1829d1555455c9a143f1d18a6116
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Petr Cvek <petrcvekcz@gmail.com>
2019-09-30 20:08:04 +00:00
Kyösti Mälkki a0b366d550 device/pci_early: Drop some __SIMPLE_DEVICE__ use
The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.

We have some use for PCI bridge configurations and
resets in romstages, so expose them.

Change-Id: Ia97a4e1f1b4c80b3dae800d80615bdc118414ed3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30 20:06:06 +00:00
Arthur Heymans 50b4f78344 sb/intel/spi: Use different SPIOPS for most SST flashes
Many supported SST flashes use the AAI OP (0xad) to write.

TESTED on Thinkpad X60 with SST25VF016B, flashrom can use AAI_WRITE op
with locked down SPIOPS.

Change-Id: Ica72eda04a8d9f4e563987871b1640565c6e7e12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-30 12:02:35 +00:00
Arthur Heymans ebf201b8f5 sb/intel/bd82x6x: Use common final SPI OPs setup
This also reworks the interface to override OPs from the devicetree to
match the interface in sb/intel/common/spi.

Change-Id: I534e989279d771ec4c0249af325bc3b30a661145
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-30 12:02:15 +00:00
Aamir Bohra ff5eb86aeb mb/google/drallion: Clean up devicetree config
* Disable SATA controller and related configs.
* Disable PCIe root ports 10 and related configs.
  -> Board uses integrated CnVi for WLAN
* Disable PCIe root ports 12 and related configs.
  -> Board uses WWAN intarfaced over USB

Change-Id: If9d49cef290dcccb114afccc3ac34cd072802ea4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35723
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 12:01:08 +00:00
Aamir Bohra 0e1245e3d0 mb/google/drallion: Configure LPSS controller parameters
drallion uses below LPSS controllers:

I2C: 0/1/4
GSPI: None
UART: 0(Console)

BUG=b:141575294

Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2019-09-30 12:00:57 +00:00
Kyösti Mälkki 7b2da05310 arch/x86: Fix __ROMCC__ automatic prerequisities
While the list of prerequisities is not created with romcc,
we need to simulate it since different set of header files
will is used.

Change-Id: Ib799c872b5280e2035126f9660e04e51acc4b1a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35601
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 11:59:26 +00:00
Kyösti Mälkki d2186a3b3f soc/intel/fsp_broadwell_de: Enable SSE and SSE2
Apparently romcc-bootblock just barely built without
XMM registers.

Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-30 11:54:34 +00:00
Nico Huber b56fcfe9b5 drivers/i2c/lm96000: Add more settings for fan control
Allow to set a lower temperature limit, as the currently hard-coded
25C may be to low for a given temperature sensor. Also enable smoo-
thing, currently hard-coded to the maximum interval of 35s, and set
the hysteresis value.

Change-Id: I5fde1cf909e8fbbaf8a345790b00c58a73c19ef8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30 11:52:31 +00:00
Nico Huber 9a940bf295 drivers/i2c/lm96000: Fix integer sign issue
We accidentally converted an `int` return value to an `unsigned`,
making it impossible to check for errors with `< 0`. Fix that by
using an `int` variable.

Change-Id: I5433c27e334bc177913e138df83118b128c674b7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30 11:51:41 +00:00
Nico Huber 5fb34e87eb ec/kontron/kempld: Add fall-through comments where appropriate
Fixes related GCC warnings.

Change-Id: I803fc0e005390ebd8a5e3ac6886ee968c56c3a34
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30 11:51:11 +00:00
Nico Huber 5936ba43f3 drivers/i2c/at24rf08c: Add proper Kconfig option
The existing Kconfig code made SMBIOS_PROVIDED_BY_MOBO depend
on VENDOR_LENOVO. Thus, it couldn't be selected by boards from
other vendors. So we add another Kconfig that selects it
here.

NB. It's still unclear how the two drivers in this directory
are related (at24rf08c and lenovo_serial). From the code, it
doesn't look like the latter belongs here.

Change-Id: Iaa5c5a584f2a5e2426352ec6aa681f99a55efa49
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30 11:50:42 +00:00
Nico Huber 9734af6697 device/i2c_bus: Add i2c_dev_read_at16()
i2c_dev_read_at16() sends a 16-bit offset to the I2C chip (for larger
EEPROM parts), then reads bytes up to a given length into a buffer.

Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30 11:50:16 +00:00
Maxim Polyakov 9529530766 pci_ids: fix PCI ID for Intel Iris HALO GT4 iGPU
According to the documentation [1], SKL-H Halo GT4E (Iris Pro Graphics
P580) PCI ID should be 0x193B.

[1] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM)
    Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference
    Manual. Volume 4: Configurations. May 2016, Revision 1.0
    Doc Ref # IHD-OS-SKL-Vol 4-05.16

Change-Id: Id62fe3ec26779d51b748efd271db565ade1e3ee0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-30 11:49:07 +00:00
Maxim Polyakov dde937cce3 pci_ids: rename PCI_DEVICE_ID_INTEL_SKL_ID_H
The new macro name contains the number of cores:
PCI_DEVICE_ID_INTEL_SKL_ID_H_4 - 4 core
PCI_DEVICE_ID_INTEL_SKL_ID_H_2 - 2 core

Change-Id: I190181b213d55865aa577ae5baff179fef95afde
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35302
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 11:48:50 +00:00
Paul Fagerburg 4ab023329d util/mb/google/hatch: update CRC calculation for correctness
The CRC result is treated as a signed value, and so in certain
situations, the calculated value for the last four digits will not
be correct. Ensure that the CRC is treated as an unsigned 32-bit
value prior to converting the last 4 decimal digits to a string.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I92f9ce1ceb7450f90b89c94e0ace6f79a9419b42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35604
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 11:43:28 +00:00