Commit Graph

48036 Commits

Author SHA1 Message Date
Sean Rhodes d18fa49a0f mb/starlabs/lite/glkr: Simplify GPIO macro's
Use shorter macro's to conifgure GPIO's.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I926aac8679f847cd963be07786e9fe2e4c63bda6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-21 12:29:51 +00:00
Sean Rhodes 2c6c5f2f7a mb/starlabs/lite/glkr: Disconnect unused GPIO's
Disconnect GPIO's that are unused, or not connected.

Also update comments that are vague or have errors.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1b071ec1d194f76ee78066396bac8dfff5ec851b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64651
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-21 12:29:21 +00:00
Matt DeVillier f8c8a8dc55 soc/amd/common/i2c: Add i2c bus ops handler
Without this, calls to i2c_link() and runtime i2c detection fails on
AMD common platform boards.

Test: Runtime i2c detection of correct touchpad model succeeds on
google/zork.

Change-Id: I238b680b2afb4b9d3e5ac75fe9e630b2adc74860
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-21 12:28:45 +00:00
Matt DeVillier 323ca33b20 soc/amd/*: Move selection of DRIVERS_I2C_DESIGNWARE to common block
All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select
DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the
selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding
the Designware I2C bus ops handler in a subsequent commit.

Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-06-21 12:28:33 +00:00
Matt DeVillier e97eb8f94b device/i2c_bus: Add missing trailing newline to console output
Improves readability in console log.

Change-Id: Ied0cbb746ff3ca6250ed9322dfb2726da0949e16
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-21 12:28:21 +00:00
Matt DeVillier 06abb91b22 device/i2c_bus: Check for self loop in bus link
When trying to find the parent i2c bus of a given device, ensure that
the bus link doesn't point to itself, else we'll get stuck in an
infinite loop.

Change-Id: I56cb6b2a3e4f98d2ce3ef2d8298e74d52661331c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-06-21 12:28:07 +00:00
Subrata Banik f887879815 mb/google/brya: Add `ext_pm_support` for taeko eMMC SKU
This patch ensures google/taeko eMMC SKU has advanced PM support
enabled.

BUG=b:235915257
TEST=Able to boot to eMMC SKU to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6b14130e47c3e3ec9b066456f3195841c83623a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65243
Reviewed-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-21 11:41:33 +00:00
Subrata Banik 0a50ea0960 mb/google/brya: Add `ext_pm_support` for taniks eMMC SKU
This patch ensures google/taniks eMMC SKU has advanced PM support
enabled.

BUG=b:235915257
TEST=Able to boot to eMMC SKU to ChromeOS.

Change-Id: I20c98006b6a45e2c8286480c560c8dbc0752327c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65213
Reviewed-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-21 11:41:17 +00:00
Stanley Wu 8e3610486e mb/google/nissa: Create pujjo variant
Create the pujjo variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Follow other ADLN variant to generate by manual)

BUG=b:235182560
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJO

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I73ec985bc19320260d0c3132c1ca23a3648df9e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-21 11:41:00 +00:00
Matt DeVillier 77c86aafeb mb/purism/librem_cnl: convert to using overridetrees
Convert the librem_14 and librem_mini from using separate devicetrees
to using a baseboard devicetree and overridetrees. This reduces code
duplication, and facilitates adding any new variants with minimal
additional code.

Test: build/boot Librem 14 and Librem Mini v2 boards

Change-Id: Ide65ffc750495c9ba2074757ce467efa2f384c56
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 20:51:56 +00:00
Sean Rhodes 57779955c9 soc/intel/apollolake: Hook Up SataPortEnable to devicetree
Hook Up SataPortsEnable to the devicetree. As the default value is 0,
set both [0] and [1] in all mainboards so they aren't affected.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20 20:09:40 +00:00
Michał Żygowski 3f205a416e soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI names
ADL-S has more USB ports than mobile chipsets. Add missing ACPI
names.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63655
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20 14:07:07 +00:00
Nicholas Chin cc8be37a59 libpayload/Makefile.inc: Initialize vboot submodule
After commit 63e54275f6 (libpayload: Implement new CBFS access API),
libpayload includes headers from commonlib/bsd, which in turn include
vb2_sha.h from vboot after commit 0655f78041 (commonlib/bsd: Add new
CBFS core implementation). Usually submodules are initialized by the top
level Makefile.inc, but since this file is never read when building
libpayload based payloads outside the main coreboot build, the header
cannot be found unless the vboot submodule had previously been
initialized. This is especially evident when following Tutorial 1 in the
documentation, where the coreboot repo is cloned without recursing into
submodules and coreinfo is built separately from the coreboot build
using `make -C payloads/coreinfo`.

TEST=Deinitialize submodules and run `make -C payloads/coreinfo`.
Coreinfo should build without error.

Change-Id: I29b16525999921fbce51c2459d3d534b64e00b3c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65222
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20 13:54:31 +00:00
Arthur Heymans c056d18fbe soc/amd/stoneyridge: Align get_cpu_count to other targets
The CPUID function to get the number of cores on a package is common
across multiple generations of AMD cpus.

Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64869
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-20 12:19:06 +00:00
Arthur Heymans 615818f5a9 soc/amd/*: Make mtrr decision based on syscfg
The syscfg has to option to automatically mark the range between 4G and
TOM2, which contains DRAM, as WB. Making it generally not necessary to
allocate MTRRs for memory above 4G if no PCI BARs are placed up there.

Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-20 12:18:43 +00:00
Sean Rhodes 99d2d62fa1 mb/starlabs/labtop: Configure tcc_offset based on power_profile settings
Set tcc_offset value based on the power_profile value, ranging from 10
to 20 degrees.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I66fb266c1730833ff6e2dbf8ea39f23ee0878590
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:15:52 +00:00
Jesper Lin 49d0204c31 mb/google/brya/variants/nereid: enable CNVi bluetooth in overridetree
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nereid overridetree to enable port 10.

BUG=b:236162084
TEST=USE="project_nereid emerge-nissa coreboot" and verify it builds
without error.

Signed-off-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
Change-Id: Ic45301b863383e447b2dd3e06811b469cc247229
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65188
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20 12:13:02 +00:00
Elyes HAOUAS e7b96c32c1 drivers/usb/gadget.c: Use 'printk()' instead of 'dprintk()'
dprintk(BIOS_,...) was probably useed for debug print, so use
printk(BIOS_, ...) instead.

Change-Id: Ia4171c8b4b42f6b0c1c9c0438bab2eef73f8c416
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-06-20 12:12:30 +00:00
Sean Rhodes 3ae95b2630 mb/starlabs/lite/glk: Organise USB ports by hardware port
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.

This change also corrects the daughterboard USB 3.0 port number.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib6a934a1e5e65fe387c63b78cbe80e45e97e0a8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20 12:11:37 +00:00
Sean Rhodes b02c90d146 mb/starlabs/lite/glkr: Correct the daughterboard USB 3.0 port number
The daughterboard USB 3.0 was set to port 3, which is incorrect. This
patch corrects that to port 4.

This fixes an issue where USB 3.0 devices are not detected when plugged
in to this port.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50f86dee1b512d0dd20d07e3ee17ebfa5e537bc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:11:01 +00:00
Sean Rhodes 8a1eb1993d mb/starlabs/lite/glkr: Correct USB port numbers
The USB ports for the Motherboard USB 3.0 and Type-C were labelled
incorrectly. This change swaps the ports, so they are labelled correctly
and also corrects the over-current pins that they use.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I80484dc8bdd68dd72b3848720c790d59237a9f8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:10:42 +00:00
Sean Rhodes 8a4f076894 mb/starlabs/lite/glkr: Organise USB ports by hardware port
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2a7f50ca2b2001e83211e8eba56bfa929ecdfd74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:09:44 +00:00
Sean Rhodes fe97c77cab mb/starlabs/lite: Enable enhanced C-states
Tested on the StarLite Mk III & Mk IV with Zorin 16.2 Core. This
resulted in a reduction in power consumption of approximately 3%.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7b5f4e01bc786db02184b722c74fda7d0ca055be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:08:08 +00:00
Sean Rhodes 9d894b8563 soc/intel/apollolake: Hook up C1e to enhanced_cstates
Hook up C1e FSP S UPD which enables enhanced C-states, to
enhanced_cstates. This allows it to be enabled in the
devicetree with a value of "1" as the default is disabled.

C1e exists on both APL and GLK, and has been there since their
initial releases.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie803a75ac9fb64a6c21b31baeea7b736e4fbf5fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:07:52 +00:00
Sean Rhodes 9088b681f5 soc/intel/apollolake: Hook up UfsEnabled to devicetree
Hook up FSP S UfsEnabled UPD (1d.0) to devicetree.

UFS only exist on GLK, and has been there since its
initial releases.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:06:56 +00:00
Sean Rhodes ae64b6e5db mb/starlabs/lite: Configure MMIO window for EC
The Nuvoton EC requires a window to be opened for updates, so open
this window only if the Nuvoton EC is present.

Change-Id: Iaa45aa58749c4d0bfc77e60b52eab2bcb270f3ee
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:05:53 +00:00
Sean Rhodes 220a47d12c mb/starlabs/labtop/kbl: Organise USB ports by hardware port
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib5fec81a7a04f2f5ab13784435944601902904d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:05:07 +00:00
Sean Rhodes 840915bb8a mb/starlabs/labtop/cml: Organise USB ports by hardware port
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie9bc6b3e20dddeb14cea195ef9a719432f66c6e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:03:35 +00:00
Sean Rhodes e07ac22487 mb/starlabs/lite/glk: Configure LPC IO registers
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I47523fae8d1cb0fbb972a82c43a992c9fb606ed4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:03:05 +00:00
Sean Rhodes b7c1a3aee9 mb/starlabs/lite/glkr: Configure LPC IO registers
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2d949af0086c231e27ac889c0aabd0d3e00c94fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:02:53 +00:00
Sean Rhodes 7a82a805b8 soc/intel/apollolake: Allow configuring the LPC IO registers
Allow configuring the LPC IO registers in the devicetree with:
* gen1_dec
* gen2_dec
* gen3_dec
* gen4_dec

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2a7ab3faf927cda76640227feff4e19017442897
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:02:35 +00:00
Petr Cvek d6fb425ca6 intel/gma: Use bitwise or instead addition for valid bit
Page table entries bit 0 is used as "valid". Its value should be set
by a bitwise OR and not by an addition.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: I14467081c8279af4611007a25aefab606c61a058
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20 12:02:05 +00:00
Paul Menzel 3b0303dbe8 Doc/soc/intel/mp_init: Mark up Reference section title as title
It’s a section title, so mark it up as a title as it’s done similarily
in other documents.

Change-Id: If9d524afe6f80ae1b2704d11617786ee923814b2
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-20 12:01:41 +00:00
Nick Vaccaro 6ddcbb6f0b mb/google/brya/var/skolas4es: Add new memory parts
Add support for the MT53E2G32D4NQ-046 WT:C and MT53E512M32D1NP-046 WT:B
memory parts to skolas4es.

BUG=b:236284219
BRANCH=firmware-brya-14505.B
TEST=None

Change-Id: I5e3534985e12535ccc4285a0d829bca04781cf1b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65179
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-20 12:00:15 +00:00
Elyes HAOUAS f6c100fbac include/smbios.h: Update misc_slot_type and smbios_onboard_device_type
Update according to DSP0134: https://www.dmtf.org/standards/smbios

Change-Id: Iceccc672eaef0ad0bc0589797fa15d2a6a918918
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-06-20 10:50:41 +00:00
Angel Pons bb58c1e438 util/cbfstool: Set `USE_FLASHROM=0` to build vboot
cbfstool does not need to build vboot with flashrom support.

TEST=./util/abuild/abuild -a --timeless -y -c $(nproc) -Z -t hp/280_g2
     no longer fails due to missing libflashrom.h header.

Change-Id: I57edcb1b67baa4c458874b11e9ca0238b4419c46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-19 18:46:04 +00:00
Elyes Haouas 67f0945506 sb/intel/i82801ix/smihandler.c: Remove dead increment
The value stored to 'data' is never read. So remove dead increment and
commented out code.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ifef67fc6415af1260d1a1df54f53fbe67f8860bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-06-18 04:50:22 +00:00
Tony Huang 356f118379 mb/google/dedede/var/shotzo: Add EC defines for ACPI
Update Shotzo own ec.h with the battery, lid and ps2
defines stripped.

This is to ensure the correct ASL is generated so that we don't
advertise PS2 keyboard support and battery/lid interrupts which
don't exist.

In MAINBOARD_EC_SCI_EVENTS drop following events.
    EC_HOST_EVENT_LID_OPEN
    EC_HOST_EVENT_LID_CLOSED
    EC_HOST_EVENT_BATTERY_LOW
    EC_HOST_EVENT_BATTERY_CRITICAL
    EC_HOST_EVENT_BATTERY
    EC_HOST_EVENT_BATTERY_STATUS

set MAINBOARD_EC_SMI_EVENTS to 0 and drop
    EC_HOST_EVENT_LID_CLOSED smi event.

In MAINBOARD_EC_S5_WAKE_EVENTS drop below event.
    EC_HOST_EVENT_LID_OPEN

In MAINBOARD_EC_S3_WAKE_EVENTS drop following events.
  EC_HOST_EVENT_AC_CONNECTED
  EC_HOST_EVENT_AC_DISCONNECTED
  EC_HOST_EVENT_KEY_PRESSED
  EC_HOST_EVENT_KEY_PRESSED

BUG=b:235303242
BRANCH=dedede
TEST=Build

Change-Id: I5717e2e8ca7549d160fe46ccde31c6d7cf9649d7
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65167
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-18 04:37:50 +00:00
Cliff Huang edf71a08b4 soc/intel/alderlake: Skip PCIe source clock assignment if incorrect
When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.

Add check and skip for enabled root port that does not have clock
structure. In addition, a root port can not use a free running clock or
clock set to LAN.

Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-18 04:35:37 +00:00
Tim Wawrzynczak 74ed2a5d60 mb/google/brya/var/agah: Remove variant_finalize
The EEs and I misunderstood, and apparently the vfio-pci kernel driver
will turn off the dGPU when it sees it is unused, so coreboot should
leave the dGPU on so the kernel driver can save state before it shuts it
down.

TEST=Tested by ODM

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I30b5dead7a5302f3385ddcaecfbf134c3bb68779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65181
Reviewed-by: Robert Zieba <robertzieba@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-18 04:33:25 +00:00
Julius Werner 6e28808612 Update vboot submodule to upstream main
Updating from commit id 25b94935:
    vboot_ref/futility: Wrap flashrom_drv behind USE_FLASHROM

to commit id 61971455:
    vboot_ref/Makefile: Expose symbols irregardless of USE_FLASHROM

This brings in 90 new commits.

BUG=b:207808292,b:231152447
TEST=builds with vboot_ref uprev.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: Id542f555732b58e1205e757393f9d5fdbde2de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17 20:57:35 +00:00
Sridhar Siricilla 044817762b soc/intel/{alderlake, common}: Rename the pre_mem_ft structure
The patch renames identifiers (macros, function and structure names) in
the basecode/debug/debug_feature.c to generic names so that they can be
used to control the features which may have to be controlled either
during pre and post memory.

Currently, the naming of identifiers indicate that it meant to control
the features which can be controlled during only pre-memory phase.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17 19:47:11 +00:00
Frank Wu b404fa474f mb/google/brya/var/banshee: Update thermal settings PL1 and PL2
Update PL1 and PL2 based on the suggestion of the thermal team.
Then the settings are both updated in firmware log.

BUG=b:233703656, b:233703655
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ibb81a1a8519b88ed4774385d9ccf895d64bbdc21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-17 16:50:29 +00:00
Subrata Banik 56d3103f6e cpu/intel/microcode: Fix `device enumeration` boot regression
Prior commit hash 0310d34c2 (cpu/intel/microcode: Have provision to
re-load microcode patch) introduces an option to reload the microcode
based on SoC selecting RELOAD_MICROCODE_PATCH config.

This patch might potentially introduce a boot time regression (~30ms)
when RELOAD_MICROCODE_PATCH kconfig is enabled as all cores might end up
reloading the microcode without the proper need.

Note: RELOAD_MICROCODE_PATCH kconfig is not yet selected by any SoC
hence, it doesn't impact any coreboot project.

The idea is reloading microcode depends on specific use case
(for example: Skip FSP doing MP Init from Alder Lake onwards) hence,
a follow up patch will create a newer API to allow reloading of
microcode when RELOAD_MICROCODE_PATCH config is enabled.

BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie320153d25cefe153fc8a67db447384f1f20f31f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-17 16:07:35 +00:00
Arthur Heymans 8cd1dfa4ae soc/amd/smm_relocate.c: Improve TSEG programming
TSEG does not need to be aligned to 128KiB but to its size, as the MSR
works like an MTRR. 128KiB is a minimum TSEG size however.

TESTED on google/vilboz.

Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64865
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-17 15:27:21 +00:00
Jeff Daly 5b67ad0a5f soc/intel/denverton_ns: enable Denverton to use common msr defines
Use Intel common SoC msr.h for Denverton refactor

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ic5f99fbcd2f936d4e020bd9b74b65dcd6e462bdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61016
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-17 14:53:18 +00:00
Jeff Daly e5ac300602 soc/intel/denverton_ns: enable Denverton to use common SoC SPI code
Use Intel common SoC SPI code for Denverton refactor

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17 14:52:41 +00:00
Mark Hsieh 24f7554e07 mb/google/nissa: Create joxer variant
Create the joxer variant of the nissa reference board by copying
the template files to a new directory named for the variant.

BUG=b:236086879
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_JOXER

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4cb74f90c4ec33818b551d5f51759930e3222677
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2022-06-17 14:40:12 +00:00
Eric Lai 99edff944c soc/intel/denverton_ns: Define macro TOTAL_PADS
Define total GPIO pins as TOTAL_PADS.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I220b6f1a968667a68c30c7287ab5af1912959e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-17 14:39:07 +00:00
Eric Lai 471c239ffe soc/intel/xeon_sp: Define macro TOTAL_PADS
Define total GPIO pins as TOTAL_PADS.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic7c48415d1fa3067ac62520a542058e7cab45941
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-06-17 14:38:47 +00:00