No need to limit these declarations to FSP. Both
PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE
can be built on top of this.
Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Stoney Ridge is family 15h models 70h-7Fh, Merlin Falcon is family 15h models
60h-6Fh. Add changes based on config parameter SOC_AMD_MERLINFALCON to make
the code backward compatible with Merlin Falcon.
BUG=none.
TEST=Tested later with padmelon board.
Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33624
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DIMM_SPD_SIZE is no longer used and should have been removed in
78025f6 "soc/amd/picasso: Remove all AGESA references".
Change-Id: Iae15998835e4d8afdb44cca77d2c9009b7e3947a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Make the option match the change in I7c3b3ec.
"stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUME"
Change-Id: I7fa13428ec0119b61f429116a52986067e833bdf
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The decision to leave the alignment in stoneyridge was driven because
of a spec difference with picasso. AMD has checked the design
materials and has confirmed there was no change.
TEST=Build Grunt successfully
BUG=b:130343127
Change-Id: If3a1d5a41dc175c9733fd09ad28627962646daf9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add config parameter for Merlin Falcon (SOC_AMD_MERLINFALCON) and modify
the Makefile.inc based on this config parameter.
BUG=none.
TEST=Tested later with padmelon board.
Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is only a qualifier between TSEG and ASEG.
Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SMM_TSEG is a qualifier between TSEG and ASEG memory
region. ASEG is deprecated and not supported for
this platform in coreboot codebase.
The SMM lock should be set based on whether SMM is
installed or not, HAVE_SMI_HANDLER currently tells
that.
Change-Id: I9756f8a59ccfedd59d5b997b35313452dd0c4f46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34127
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove
all source, support functions, and comments related to AGESA.
Family 17h requires v9 which has no similarities to v5 for
integration into a host firmware. AGESA v9 support will be added
via subsequent patches into the appropriate locations.
Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Remove the mailbox call to notify the PSP that DRAM is ready. This
is not supported on Family 17h.
Remove the selectable SMU firmware. This is a feature of the PSP
bootloader and the standard bootloader doesn't contain the ability.
Clean up additional mentions of PSP within picasso.
Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The command line options for picasso will look different than
stoneyridge. Remove the fanned/fanless distinction to simplify
the makefile.
Picasso will use subprograms instead of fanned/fanless SKUs.
Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33753
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove
source that uses these. Remove USB devices from the AOAC registers.
Remove the D0/D3 support from ASL, including all supporting xHCI
firmware loading support. Remove xHCI firmware from amdfw.rom.
Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Remove all Picasso bootblock support. CAR is not a supportable
feature, and the first code executed at the reset vector will be
a hybrid romstage. Details for this implementation may be found
in Documentation/soc/amd/picasso/family17h.md.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Update paths. There are still a few paths in Kconfig relating to PSP
and the firmware directory table. Those will be updated in a follow-on
commit.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I18f3d80dbeabd754ebcee6593864fd613fc2ef7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32412
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the Makefile is updated, we can change the name back without
it affecting the Stoney build.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I18ee48865fb64265f38179560265827783d50820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Remove files that aren't needed for the picasso port.
Remove traces of AGESA v5 (includes binaryPI support files). Remove
SPD helper.
Picasso (and all AMD Family 17h processors) have a very different
boot flow from previous products. Memory is initialized by the PSP
before the x86 processor is released from reset. The SPD is read by
the PSP, so it's not needed in coreboot.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
So that everyone can see what's being updated from stoney, we're
starting with a direct copy of the stoney directory. There are
arguments both for and against doing it this way, but I believe
This the most transparent way. We've moved much of the duplicated
stoney code into the soc/amd/common directory and will continue
that work as it becomes obvious that we have unchanged code between
the SOCs.
Makefile.inc has been renamed as makefile.inc so that it won't
build in jenkins until the directory is updated.
Other than that change, this is an exact copy of the stoneyridge
SOC directory which will be updated in the follow-on commits in
the patch train.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a method for the soc/amd/<product> to indicate what AcpiMmio
ranges are supported. Induce a build error if soc or mainboard
code is added which attempts to use an unsupported block.
This patch attempts to dissuade accessing unsupported blocks without
requiring the complexity of structures or reinitializing at the
beginning of a new stage.
TEST=boot grunt, force build errors by removing blocks in iomap.h
BUG=b:131682806
Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Modify the 16 and 32 bit BIOS RAM access functions that had been
originally moved from stoneyridge. This was suggested in the
review of
69486cac7: Create AcpiMmio functionality from stoneyridge
Change-Id: I5b491da6f263cbab2b549301e16a7e19896f2428
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32932
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Document the AcpiMmio individual blocks better. This is in response
to a request in gerrit for
69486cac7: Create AcpiMmio functionality from stoneyridge
Correct comments that were inadvertently left in place from older
patches.
Change-Id: I4c16a866de5622e8cfbd3a08816b9d3182950d0e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32931
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change all arguments named "offset" to "reg" to match the others.
These should have gone into change
69486cac7: Create AcpiMmio functionality from stoneyridge
Change-Id: Ifdd00d0a5d1e03bfa68a13eeece2d2cfd56aa39d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32930
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reorder the biosram prototypes to match the rest of the file. Remove
prototypes for asf 32-bit functions that have not been implemented.
Change-Id: Ic2663158d8a71952c26eb37f34342a6ea5e58a42
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32929
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Relocate the alink access functions out of stoneyridge where they
were dead code. This source maintains the ability to access all
register spaces, however more modern APUs define only ABCFG in
the BKDGs.
BUG=b:131682806
Change-Id: I5c558ccc64bd04a66399c678d43beb0a97e72f63
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32663
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the address and replace the hardcoded value in the ASL code.
Change-Id: If0b99de78d8c5948e2e5f2aa50dfc2efc1bd1ba1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32662
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Separate chipset-specific source from sata_init(), and modify it
to better match coreboot conventions. A subsequent patch will
move the generic portion to soc/amd/common.
The support for enabling port multipliers appears to have been
first added for Kabini. Although missing from the documentation,
the ability to affect the HBA Capabilities Register seems to remain
for Stoney Ridge.
Change-Id: I5dd9f613d36badc3e4d185a22b4475cb82ce187e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32660
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Obsolete pm_acpi_pm_cnt_blk(), and remove it and pm_acpi_pm_evt_blk().
Relocate the remaining functions to get/save UMA information to
southbridge.c.
Change-Id: I90c4394e3cf26f4ad60a078948a84303bda693d0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32659
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the function into common code. Convert it to use the memory-
mapped access type. Convert vboot_platform_is_resuming() to call it
instead of duplicating the source.
BUG=b:131682806
Change-Id: I245bebb8dc2d331cdd56acfb245a004536b792ab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AcpiMmio block allowing direct access to the ACPI registers
has remained consistent across AMD models. Move the support from
soc//stoneyridge to soc//common.
BUG=b:131682806
Change-Id: I0e017a71f8efb4b614986cb327de398644599853
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The halt.c file relies on the ACPI register block in the AcpiMmio
range. This register block is consistent across AMD device
generations, so to prepare for moving additional stoneyridge support
to this directory by changing the file name and add a Kconfig symbol
to control the build.
BUG=b:131682806
Change-Id: I2f7442dd78bced7f69b0416a8cd751291f82151f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD devices traditionally have the LPC-ISA bus at 14.3 and the
definition has been very consistent. Relocate the feature from
stoneyridge into common/block.
BUG=b:131682806
Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A subsequent patch will move the soc//stoneyridge LPC functionality to
a common directory. Prepare by reworking the SPI BAR configuration
function in southbridge.h. The SPI BAR is not a typical PCI BAR, and
is at D14F3xA0.
Change-Id: I73ddb4afaf9e67ca0522ecb6085b23c92fedc461
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32652
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The banked GPIO functionality in the AcpiMmio block has been consistent
since the Mullins product. Move the basic support into a common
directory.
Each product's pin availability, MUXes, and other details must remain
specific to the product.
The relocated source also drops the weak configure_gevent_smi() that
reports SMI is not available. The stoneyridge port relies on SMI
to do its initialization, similar to modern soc/intel devices. This
is the plan for future soc/amd ports, so make a missing function a
build error instead of a runtime warning.
BUG=b:131682806
Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
