Commit Graph

20446 Commits

Author SHA1 Message Date
Patrick Georgi dce629b2f8 util/cbfstool: avoid memleaks and off-by-ones
Change-Id: Iac136a5dfe76f21aa7c0d5ee4e974e50b955403b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: scan-build 3.8
Reviewed-on: https://review.coreboot.org/18134
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-20 20:05:09 +01:00
Arthur Heymans 1dfc0a64d4 mb/apple/macbook11,macbook21,imac52: Remove per board directories
This is achieved by setting up Kconfig and Kconfig.name very similar
to how variants are used.

Change-Id: I22089ff29e3879d7956527a092a0ac6425b05cb3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17894
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-20 17:07:13 +01:00
Lee Leahy 0b5678f21f arch/x86: Fix most of remaining issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
ERROR: Macros with complex values should be enclosed in parentheses
ERROR: switch and case should be at the same indent
WARNING: char * array declaration might be better as static const
WARNING: else is not generally useful after a break or return
WARNING: storage class should be at the beginning of the declaration
WARNING: void function return statements are not generally useful
WARNING: break is not useful after a goto or return
WARNING: Single statement macros should not use a do {} while (0) loop
WARNING: sizeof *t should be sizeof(*t)
WARNING: Comparisons should place the constant on the right side of the test

TEST=Build and run on Galileo Gen2

Change-Id: I39d49790c5eaeedec5051e1fab0b1279275f6e7f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-20 16:36:24 +01:00
Wisley Chen 41dded3548 mainboard/google/snappy: Update _hid name for weida touchscreen
Change hid name to "WDHT0002" for Weida WDT8752 which is supported by
standard hid i2c Linux driver.

BUG=b:35586513
BRANCH=reef
TEST=build, boot on snappy, and verified acpi node "WDHT0002" created.

Change-Id: Ie0cc980aa427b6db1eb14eb7868718619bb1310f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18874
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-20 04:04:09 +01:00
Sumeet Pawnikar f8c891a15a mb/google/reef: Remove CPU throttling effect of the charger sensor
It's not relevant to throttle CPU based on the charger sensor.
So, remove this CPU throttling effect.

BUG=b:35908799
BRANCH=master
TEST=Built and booted on Electro DUT

Change-Id: I267b6e07fa9def2c91ff9f6035f2d9437faf1965
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/18852
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-03-19 23:53:12 +01:00
Bora Guvendik 9b76f0b27b cpu/x86: add a barrier with timeout
In case something goes wrong on one of the
cpus, add the ability to use a barrier with
timeout so that other cpus don't wait forever.
Remove static from barrier wait and release.

BUG=chrome-os-partner:59875
BRANCH=reef
TEST=None

Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/18107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-19 21:40:08 +01:00
Kyösti Mälkki 4796c32ad6 ramstage: Align stack to 16 bytes
Some SSE instructions could take 128bit memory operands from
stack.

AGESA vendorcode was always built with SSE enabled, but until
now stack alignment was not known to cause major issues. Seems
like GCC-6.3 more likely emits instructions that depend on the
16 byte alignment of stack.

Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18823
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-19 21:38:53 +01:00
Nicola Corna 85e81dfa6d tint: Add USB support
Enable the USB during the initialization of tint. Without it USB
keyboards don't work, which makes this payload pointless on
systems where a PS/2 keyboard port isn't available.

Based on I98f0ccdb19d6b195572941cf87ce3221f57db7c5 (tint and
nvramcui: enable USB, update tint to 0.04+nmu1 with changes) [1]

[1] https://review.coreboot.org/17507/

Change-Id: Iaa8dfac0301ef19a2d76a0975d025b00e7f3807b
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18766
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-19 21:38:22 +01:00
Nicola Corna 16719ad143 sb/intel/common/firmware: Add Intel ME/TXE firmware check
Ensure that the provided ME/TXE firmware is valid, using the
check capabilities of me_cleaner.

me_cleaner checks that the fundamental partition is available and
it has a correct signature. The checks performed by me_cleaner
aren't exhaustive, but they should find at least whether the user
has provided an empty or corrupted firmware.

me_cleaner has been tested on all the ME (6-11.6) and TXE (1-3)
firmwares available here [1], and it hasn't reported any false
positive.

[1] http://www.win-raid.com/t832f39-Intel-Engine-Firmware-Repositories.html

Change-Id: Ie6ea3b4e637dca4097b9377bd0507e84c4e8f687
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18768
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-19 21:37:57 +01:00
Arthur Heymans 8e079000dc nb/i945/gma.c: Refactor panel setup
This reuses some of gm45 code to set up the panel.

Panel start and stop delays and pwm frequency can now be set in
devicetree.

Linux does not make the difference between 945gm and gm45
for panel delays, so it is safe to assume the semantics of those
registers are the same.

The core display clock is computed according to "Mobile Intel® 945
Express Chipset Family" Datasheet.

This selects Legacy backlight mode since most targets have some smm
code that rely on this.

This sets the same backlight frequency as vendor bios on Thinkpad X60
and T60.

A default of 180Hz is selected for the PWM frequency if it is not
defined in the devicetree, this might be annoying for displays that
are LED backlit, but is a safe value for CCFL backlit displays.

Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-18 16:54:08 +01:00
Lee Leahy 216712ae01 drivers/intel/fsp1_1: Fix issues detected by checkpatch
Fix the following error and warnings detected by checkpatch.pl:

ERROR: "foo * bar" should be "foo *bar"
WARNING: line over 80 characters
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: suspect code indent for conditional statements (16, 32)
WARNING: Comparisons should place the constant on the right side of the test

TEST=Build and run on Galileo Gen2

Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18886
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-17 22:13:34 +01:00
Lee Leahy 6ef5192627 soc/intel/broadwell: Fix other issues detected by checkpatch
Fix the following error and warnings detected by checkpatch.pl:

ERROR: switch and case should be at the same indent
WARNING: line over 80 characters
WARNING: storage class should be at the beginning of the declaration
WARNING: adding a line without newline at end of file
WARNING: __func__ should be used instead of gcc specific __FUNCTION__
WARNING: Comparisons should place the constant on the right side of the test

TEST=None

Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18885
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17 19:21:53 +01:00
Lee Leahy 8a9c7dc087 soc/intel/broadwell: Fix {}, () and conditional issues
Fix the following errors and warnings detected by checkpatch:

ERROR: open brace '{' following struct go on the same line
ERROR: return is not a function, parentheses are not required
ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement

TEST=None

Change-Id: I9414341b0c778c252db33f0ef4847b9530681d96
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18884
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-17 19:21:35 +01:00
Lee Leahy 23602dfd68 soc/intel/broadwell: Add int to unsigned
Fix the following issue detected by checkpatch:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=None

Change-Id: Iae22e724b6adae16248db7dc8f822f65bfadae5f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18873
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-17 18:03:59 +01:00
Lee Leahy 26b7cd0fa8 soc/intel/broadwell: Fix spacing issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '<=' (ctx:WxV)
ERROR: spaces required around that '<=' (ctx:VxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: spaces required around that '>=' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
ERROR: space required before the open parenthesis '('
WARNING: space prohibited between function name and open parenthesis '('
WARNING: please, no space before tabs
WARNING: please, no spaces at the start of a line

False positives are generated for the following test:
WARNING: space prohibited between function name and open parenthesis '('
in both pei_data.h and pei_wrapper.h

TEST=None

Change-Id: Icab08e5fcb6d5089902ae5ec2aa5bbee5ac432ed
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18872
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17 18:03:36 +01:00
Julius Werner 7504268318 google/veyron: Clean out unused board variants
We have code for certain Veyron variant names that were either never
made into an actual board (Gus, Nicky, Thea) or used for Google-internal
test boards that no longer exist (Pinky, Shark). Let's clean them out to
avoid confusing people.

Change-Id: Icdce5f0f3613e089d0994318b02dba54170f0c42
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18860
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-17 11:38:34 +01:00
Julius Werner 2d99f3b158 google/veyron: Work around RAM code strapping error
With a recent patch (google/veyron_*: Add new Micron and Hynix modules)
we switched RAM codes for Veyron boards to tri-state since we were
running out of binary numbers. Unfortunately we only tested that change
on Minnie and Speedy, and it turns out that it broke Jaq, Jerry and
Mighty. The "high" RAM code pins on those boards were incorrectly
strapped with 100Kohm resistors (as opposed to 1Kohm on Minnie and
Speedy), which is too high to overpower the SoC-internal pull-down we
use to differentiate "high" from "tri-state". Since we already used
tri-state codes on some Minnie and Speedy SKUs we have to hack up the
code to work differently on these two groups of boards to keep
everything working.

BRANCH=veyron
BUG=b:36279493
TEST=Compiled, confirmed ram_code called the right function depending on
board.

Change-Id: I253b213ef7ca621ce47a7a55a5119a167d944078
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18859
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-17 11:38:22 +01:00
Furquan Shaikh 336a34c81b mainboard/google/poppy: Enable EC SW sync
Now that EC on poppy is stable, it is time to switch on EC SW sync.

BUG=b:36178824
BRANCH=None
TEST=Verified that EC SW sync is done properly and device boots to OS.

Change-Id: I1395ad8af73128a8dd220351f5b5da157659b19e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18838
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17 08:32:19 +01:00
Zhuo-hao Lee 07f60aa56f soc/intel/apollolake: Reduce D3 cold delay for eMMC controller
eMMC Controller is taking over 100ms to resume during runtime which
results in I/O latency issues on the Apollo Lake system such as Snappy.
The cause is the Linux Kernel setting the firmware reset time to
100 ms by default.

This patch adds _DSM method for eMMC comtroller for specifying the
device readiness durations. Function index 9 returns package of five
integers to set D3 cold delay to zero and ACPI constant Ones for the
elements where overriding the default values is not desired.

BUG=b:35774937
BRANCH=none
TEST=update snappy coreboot and test i/o latency is under 100ms

Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com>
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Change-Id: Idcfe4252b20bead15c2e5b9cb000ff797295f06a
Reviewed-on: https://review.coreboot.org/18806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-17 03:36:09 +01:00
Lee Leahy 6f80ccc357 arch/x86: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

TEST=Build and run on Galileo Gen2

Change-Id: I3495cd30d1737d9ee728c8a9e72bd426d7a69c37
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18864
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17 03:18:24 +01:00
Lee Leahy e5f29e8bf8 arch/x86: Fix prefer errors detected by checkpatch
Fix the following warnings detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: plain inline is preferred over __inline__

TEST=Build and run on Galileo Gen2

Change-Id: I8ba98dfe04481a7ccf4f3b910660178b7e22a4a7
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18863
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17 03:18:04 +01:00
Lee Leahy 024b13d07c arch/x86: Fix space issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: space required before the open parenthesis '('
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: space prohibited after that open square bracket '['
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space required after that ';' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:ExV)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: spaces required around that ':' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: spaces required around that '<=' (ctx:WxV)
ERROR: spaces required around that '||' (ctx:VxW)
ERROR: space prohibited before that '++' (ctx:WxO)
ERROR: need consistent spacing around '+' (ctx:WxV)
ERROR: spaces required around that '<' (ctx:WxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: need consistent spacing around '>>' (ctx:WxV)
ERROR: "(foo*)" should be "(foo *)"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "foo * bar" should be "foo *bar"
ERROR: code indent should use tabs where possible
WARNING: space prohibited between function name and open parenthesis '('
WARNING: unnecessary whitespace before a quoted newline
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs
WARNING: Unnecessary space before function pointer arguments

TEST=Build and run on Galileo Gen2

Change-Id: I2d7e1a329c6b2e8ca9633a97b595566544d7fd33
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17 03:17:39 +01:00
Lee Leahy 9c7c6f7213 arch/x86: Fix issues with braces detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: open brace '{' following function declarations go on the next line
ERROR: that open brace { should be on the previous line
ERROR: else should follow close brace '}'
WARNING: braces {} are not necessary for any arm of this statement
WARNING: braces {} are not necessary for single statement blocks

TEST=Build and run on Galileo Gen2

Change-Id: I13d1967757e106c8300a15baed25d920c52a1a95
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18861
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17 03:12:39 +01:00
Lee Leahy d94cff6ab2 soc/intel/braswell: Fix most of the issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: that open brace { should be on the previous line
ERROR: return is not a function, parentheses are not required
WARNING: braces {} are not necessary for any arm of this statement
WARNING: line over 80 characters
WARNING: braces {} are not necessary for single statement blocks
WARNING: Avoid unnecessary line continuations
WARNING: break is not useful after a goto or return
WARNING: else is not generally useful after a break or return

False positives are generated by checkpatch for the following test:
ERROR: Macros with complex values should be enclosed in parentheses

TEST=Build for cyan

Change-Id: I19048895145b138a63100b29f829ff446ff71b58
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18871
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-17 02:36:36 +01:00
Lee Leahy 1072e7dcc3 soc/intel/braswell: Add int to unsigned
Fix the following warning detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=Build for cyan

Change-Id: Ib5c6a1bf5308a8add42d7371854b80ea53d7ae84
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18870
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-17 02:36:16 +01:00
Lee Leahy 6598b91fe3 soc/intel/braswell: Fix spacing issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxE)
ERROR: spaces required around that '=' (ctx:WxV)
ERROR: code indent should use tabs where possible
WARNING: space prohibited between function name and open parenthesis '('
WARNING: please, no spaces at the start of a line

TEST=Build for cyan

Change-Id: I84d4204585b498b695608c5008fdfb7961e2416f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18869
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-17 02:35:47 +01:00
Lee Leahy f4c4ab9826 soc/intel/skylake: Fix remaining issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
ERROR: Macros with complex values should be enclosed in parentheses
ERROR: "foo * bar" should be "foo *bar"
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '=' (ctx:VxW)
WARNING: space prohibited between function name and open parenthesis '('
WARNING: storage class should be at the beginning of the declaration
WARNING: char * array declaration might be better as static const
WARNING: please, no space before tabs
WARNING: braces {} are not necessary for single statement blocks
WARNING: else is not generally useful after a break or return
WARNING: static const char * array should probably be static const char * const

TEST=Build for glados

Change-Id: Ic14ca3abd193cfe257504a55ab6b74782b26bf6d
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18868
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17 02:35:27 +01:00
Lee Leahy b439a92939 soc/intel/skylake: Wrap lines at 80 columns
Fix the following warning detected by checkpatch:

WARNING: line over 80 characters

TEST=Build for glados

Change-Id: I79341f46ca06ac052f987975ccaf975470d27806
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18867
Tested-by: build bot (Jenkins)
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2017-03-17 02:34:52 +01:00
Lee Leahy 573564cca8 soc/intel/skylake: Add int to unsigned
Fix the following warning detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=Build for glados

Change-Id: Idc2ad265e8ed8cd7fd6d228cfbe4cbbcb9d3ebfc
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18866
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17 01:52:54 +01:00
Rizwan Qureshi 6a1503e9db google/poppy: Use rt5663 interrupt as GpioInt instead of PIRQ
The kernel driver for rt5663 expects to get an interrupt on both
a rising and falling edge, and using a legacy interrupt doesn't
provide that flexibility.

Instead configure this pin as a GPIO and use the interrupt through
the GPIO controller.  This allows using GpioInt() with ActiveBoth
setting and results in correct operation of the headset jack.

This is a clone of Duncan's patch for eve
at I6f181ec560fe9d34efc023ef6e78e33cb0b4c529

BUG=none
BRANCH=none
TEST=test on poppy that headset jack detect is read properly at
boot, and that plugging in and removing both generate a single
interrupt event in the driver.

Change-Id: I4aaa4164cb277a98ab5d5f033632f5e16bfb779e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18853
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16 16:25:40 +01:00
Duncan Laurie 887e7936f8 google/eve: Use rt5663 interrupt as GpioInt instead of PIRQ
The kernel driver for rt5663 expects to get an interrupt on both
a rising and falling edge, and using a legacy interrupt doesn't
provide that flexibility.

Instead configure this pin as a GPIO and use the interrupt through
the GPIO controller.  This allows using GpioInt() with ActiveBoth
setting and results in correct operation of the headset jack.

BUG=b:35585307
BRANCH=none
TEST=test on Eve that headset jack detect is read properly at
boot, and that plugging in and removing both generate a single
interrupt event in the driver.

Change-Id: I6f181ec560fe9d34efc023ef6e78e33cb0b4c529
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18836
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16 16:25:16 +01:00
Duncan Laurie b94e93531f i2c/generic: Add support for GPIO IRQ
Add support for using GPIO IRQ instead of PIRQ with an I2C device.

This allows a device to use an edge triggered interrupt that will
trigger on both high and low transitions.

The _DSD method for describing these GPIOs has a field for 'active
low' which is supposed to be 1 if the pin is active low, otherwise
is zero.  The value in here doesn't mean too much for GpioInt() as
those will end up using the value from GpioInt() when it actually
requests the interrupt.

BUG=b:35581264
BRANCH=none
TEST=test on Eve board that codec IRQ can be delcared as GPIO IRQ

Change-Id: I02c64c7fc28dc2d608ad40db889c7242892f16db
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18835
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-16 16:25:00 +01:00
Duncan Laurie 346cfe363e acpi_device: Add macro for GpioInt that uses both polarity
GPIO edge interrupts can report that they are ActiveBoth and will
generate an interrupt event on both rising and falling edges.

Add a macro so this type of GPIO interrupt can be used.

BUG=b:35581264
BRANCH=none
TEST=successfully use this interrupt type on Eve

Change-Id: I91408386538e442bddcacc9840e0aa14370a446c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18834
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-16 16:24:46 +01:00
Duncan Laurie 9462e14065 acpi_device: Prefix IRQ macros with ACPI
Switch some IRQ_* macros to ACPI_IRQ_* instead so they do not
fail at compile time if they are used.

BUG=b:35581264
BRANCH=none
TEST=successfully compile with ACPI_GPIO_IRQ_LEVEL_HIGH

Change-Id: Id4040eca4c7c9d8f7b4f0add411d5d6fe5ed1eb8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18833
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2017-03-16 16:24:39 +01:00
Kyösti Mälkki bf3091bae6 binaryPI: Fix SSE regression and align stack early
When allowing use of SSE instructions, stack must be
aligned to 16 bytes. Adjust x86 entry to C accordingly,
by pushing values to maintain the alignment.

For some builds, new toolchain and GCC-6.3 could emit
SSE instruction 'andps (%esp),%xmm0' with incorrectly
aligned esp, raising exception and thus preventing boot.

Change-Id: I452d40eadac2b743d0d8431809c9a81bf28c330a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-16 15:23:19 +01:00
Paul Menzel 824416078e asrock/e350m1: Include ASL for PS/2 controller
On the ASRock E350M1, with Linux 4.10 after resuming from S3, the PS/2
keyboard does not work. Adding the ASL code, fixes this.

The Linux messages change like below.

Before (equivalent to `i8042.nopnp`):

```
kernel: i8042: PNP: No PS/2 controller found.
kernel: i8042: Probing ports directly.
kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
kernel: serio: i8042 AUX port at 0x60,0x64 irq 12
kernel: mousedev: PS/2 mouse device common for all mice
```

After:

```
kernel: i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1
kernel: i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp
kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
kernel: mousedev: PS/2 mouse device common for all mice
```

Change-Id: I0a06311860398cac9cf1a077e3aba75da779f45d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18574
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-03-16 15:21:36 +01:00
Lee Leahy 4dddda294f cpu/intel: Fix the remaining issues detected by checkpatch
Fix the following error and warnings detected by checkpatch.pl:

ERROR: switch and case should be at the same indent
WARNING: Consecutive strings are generally better as a single string
WARNING: static const char * array should probably be static const char * const

TEST=Build and run on Galileo Gen2

Change-Id: I03d5d0d2db0d5e9b33c8ec807b236fe229bcc8f3
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:26:26 +01:00
Lee Leahy cdc50480c4 cpu/intel: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

TEST=Build and run on Galileo Gen2

Change-Id: I74f25da5c53bd518189ce86817d6e3385b29c3b4
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18850
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:14:27 +01:00
Lee Leahy 26eeb0f8ad cpu/intel: Fix brace issues detected by checkpatch.pl
Fix the following error and warning detected by checkpatch.pl:

ERROR: that open brace { should be on the previous line
WARNING: braces {} are not necessary for single statement blocks

TEST=Build and run on Galileo Gen2

Change-Id: Icdd6bd9ae578589b4d42002d200fa8f83920265e
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18849
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:14:09 +01:00
Lee Leahy 73a2894203 cpu/intel: Add int to unsigned
Fix the following warning detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=Build and run on Galileo Gen2

Change-Id: I207713a3370e5a9abed4535187aa2aaeef502d6f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18848
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:13:50 +01:00
Tim Chen 4239ff37b7 mainboard/google/reef: Increase PL2 Max to 15W
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_DVT_v0.6_20170314.xlsx)

1. Increase PL2 Max to 15W.

BUG=b:35583586
BRANCH=reef
TEST=build and verify PL2 Max value on electro dut

Change-Id: I13167e28267d5827d79a6bde31f077a01f2bd535
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18807
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16 04:13:39 +01:00
Lee Leahy 9d62e7e75e cpu/intel: Fix the spacing issues
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: spaces required around that '=' (ctx:VxV)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: need consistent spacing around '-' (ctx:WxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: need consistent spacing around '>>' (ctx:WxV)
ERROR: need consistent spacing around '<<' (ctx:VxW)
ERROR: spaces required around that '||' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
WARNING: space prohibited between function name and open parenthesis '('
WARNING: storage class should be at the beginning of the declaration

TEST=Build and run on Galileo Gen2

Change-Id: I6602fbc8602171ab6c2f3b6c204558ad2c811179
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18847
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:13:24 +01:00
Lee Leahy 7b5f12b9b2 cpu/intel: Indent with tabs
Fix the following error and warning detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
WARNING: please, no space before tabs

TEST=Build and run on Galileo Gen2

Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:13:06 +01:00
Lee Leahy dfc8a560d7 cpu/x86: Fix misc. remaining issues detected by checkpatch
Fix the following error and warnings detected by checkpatch.pl:

ERROR: trailing statements should be on next line
WARNING: storage class should be at the beginning of the declaration
WARNING: type 'long unsigned int' should be specified in [[un]signed] [short|int|long|long long] order

TEST=Build and run on Galileo Gen2

Change-Id: I9cfe42cf1836cfd40ffcf67237c818543f508feb
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18845
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:12:47 +01:00
Lee Leahy c5917079eb cpu/x86: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

TEST=Build and run on Galileo Gen2

Change-Id: I56ea28826963403dc0719f40c13782c56dc97feb
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18844
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:12:27 +01:00
Lee Leahy 8ca9a21a43 cpu/x86: Add int to unsigned
Fix the following warning detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=Build and run on Galileo Gen2

Change-Id: I97bbe8ba19680bdb99fa38daa5e18b440c338576
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18843
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:12:06 +01:00
Lee Leahy a15d8af140 cpu/x86: Remove braces and else if unnecessary
Fix the following warnings detected by checkpatch.pl

WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement
WARNING: else is not generally useful after a break or return

TEST=Build and run on Galileo Gen2

Change-Id: I2d6b22c66d52f5f2d24b15270ad4b52894adebc2
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18842
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:11:45 +01:00
Lee Leahy a07d0ddc44 cpu/x86: Use tabs for indent
Fix the following error and warning detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line

TEST=Build and run on Galileo Gen2

Change-Id: Ie6e4dd4c3eb0d2c44ecd008740dfc348d496fe78
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18841
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:11:27 +01:00
Lee Leahy 8bad6d2f90 cpu/x86: Fix various issues detected by checkpatch.pl
Fix the following errors and warning detected by checkpatch.pl:

ERROR: spaces required around that '=' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: need consistent spacing around '|' (ctx:WxV)
ERROR: need consistent spacing around '|' (ctx:VxW)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '==' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:ExV)
WARNING: space prohibited between function name and open parenthesis '('

TEST=Build and run on Galileo Gen2

Change-Id: I61d08055b207c607d5b7d72b0094ad8e24fbd106
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:11:10 +01:00
Lee Leahy 5f94541329 src/cpu/x86: Remove space between * and variable name
Fix the following error detected by checkpatch.pl:

ERROR: "foo * bar" should be "foo *bar"

TEST=Build and run on Galileo Gen2

Change-Id: I8b5342df3f42dbb4576aecf5b0a59f195ae8511e
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18839
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:10:47 +01:00