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32473 Commits

Author SHA1 Message Date
Elyes HAOUAS 23c1c4e153 commonlib/fsp_relocate: Fix typos 
Change-Id: I9426b88c0936c68d02554b580cc312902b8e5e13
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37810
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 17:50:22 +00:00
Kyösti Mälkki 94ce79d6c8 device/pciexp: Match Max_Payload_Size between ends of a link 
Ends of a PCIe link may advertise different Max_Payload_Size in
their PCIe Express Capabilities, Device Capabilities block.

For correct operation, both ends of the link need to have their
Device Control Max_Payload_Size programmed to match and not
exceed the other end's Device Capabilities.

Fixes: https://ticket.coreboot.org/issues/218

Change-Id: I8b1de13e9c73abb30e5ccc792918bb4f81e5fe84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2019-12-19 17:50:03 +00:00
Wim Vervoorn d1371508f5 {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC 
FSP logo handling used FspsConfig.LogoPtr and FspsConfig.LogoSize which
are chipset specific.

Create soc_load_logo() which will pass the logo pointer and size.
This function will call fsp_load_logo which will load the logo.

BUG=NA
TEST= Build and verified logo is displayed on Facebook Monolith

Change-Id: I30c7bdc0532ff8823e06f4136f210b542385d5ce
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37792
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 17:49:38 +00:00
Aamir Bohra 53490444f7 soc/intel/tigerlake: Add required header files in pch.c 
Add header files to fix build issues due to missing declaration
for get_pch_series and die_with_post_code functions.

Change-Id: Ie8ba4970ec1b73c1e481f54bcfbf95be87d9c442
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2019-12-19 17:49:13 +00:00
Karthikeyan Ramasubramanian 1e83e5c61a src/arch/x86: Build mainboard acpi_tables source if present 
Current build rules require adding blank acpi_tables in some of the
mainboards (eg. octopus, hatch). Update the build rules to compile the
acpi_tables.c only if it is present. This will help to avoid adding
blank acpi_tables.c source file.

BUG=None
TEST=Build test with octopus and hatch without blank acpi_table.c file.

Change-Id: I7dfacc6f4c737699b22acd96e17c9426d33574bd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
 2019-12-19 17:48:57 +00:00
Johnny Lin b9e8448384 drivers/ipmi: Add IPMI Read FRU function 
Implemented according to IPMI "Platform Management
FRU Information Storage Definition" specification
v1.0 for reading FRU data Product Info Area and
Board Info Area.
SMBIOS data can be updated with the FRU data.

Tested on OCP Mono Lake.

Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
(cherry picked from commit 8ac46b937c)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37095
 2019-12-19 17:48:30 +00:00
Bora Guvendik 3280b76729 storage/mmc: Fix wrong frequency setting for HS speed mode 
Emmc spec, JEDEC Standard No. 84-B51, section 6.6.2.3, selection
flow of HS400 using Enhanced Strobe states that host should change
frequency to ≤ 52MHz when switching to HS speed mode first. In
current code, mmc_select_hs400() calls mmc_select_hs() to do this,
however caps are not cleared, so when switching from HS200 to HS400,
caps will still have DRVR_CAP_HS200, and mmc_recalculate_clock() will
set 200Mhz instead of ≤ 52MHz. As a result, switching to HS400 will
intermittently fail.

BUG=b:140124451
TEST=Switch speed from HS200 to HS400 on WHL RVP.

Change-Id: Ie639c7616105cca638417d7bc1db95b561afb7af
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37775
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 17:48:15 +00:00
Eric Lai 25eb1b3149 mb/google/drallion: Clean up unused weak function 
Drallion only supports on board dimm. Remove the spd read from
SMBus. Since CB:37678 remove the Wilco 1.0 CML variants, weak function
is not needed.

BUG=b:140068267
TEST=boot into OS without issue
BRANCH=none

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37780
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 17:48:00 +00:00
Eric Lai 629abbe751 mb/google/drallion: Remove Wilco 1.0 CML code from drallion code 
Drallion supports D3 hot not D3 cold. Remove the code which used
for Wilco 1.0 CML.

BUG=b:140068267
TEST=boot into OS without any issues
BRANCH=none

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifc83fae7ac462d3e6595742d96952c2a2607c88b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Mike Wiitala <mwiitala@google.com>
 2019-12-19 17:47:52 +00:00
Bob Moragues f82fa746bf mb/google/hatch: Add mushu variant 
Create initial overlays and build for mushu

Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2019-12-19 17:46:19 +00:00
Kangheui Won bd3037bfa7 mainboard/google/puff: enable emmc 
enable eMMC in puff/overridetree.cb

BRANCH=none
BUG=b:146455177
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I432f437e0c9a618bbbf76d22976ea757c8fbdb83
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
 2019-12-19 13:47:40 +00:00
Elyes HAOUAS 9a5fc849fd mb/lenovo/g505s: Remove unused <stdlib.h> 
Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33901
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 06:54:31 +00:00
Elyes HAOUAS 88f5c7178e src: Remove unused 'include <arch/cpu.h>' 
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-12-19 05:58:50 +00:00
Elyes HAOUAS 0420e50b6b src/arch: Remove unused <stdlib.h> 
Change-Id: I79f065703b5249ca9630b06de7142bc52675076e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32820
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 05:57:07 +00:00
Elyes HAOUAS 608fbf8110 src/soc/intel: Remove unused <stdlib.h> 
Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33686
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 05:41:08 +00:00
Elyes HAOUAS d51ee90f12 src/soc/samsung: Remove unused <stdlib.h> 
Change-Id: I6a933295de7c41d62e6a95f955c098b49ea17f08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33689
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 05:39:09 +00:00
Elyes HAOUAS 8cf28dbf93 soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h> 
Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33688
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 05:38:43 +00:00
Elyes HAOUAS 38d2540674 src/southbridge: Remove unused <stdlib.h> 
Change-Id: I5728b44fdd680b21e951397a2390e24f9171ac34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32829
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 05:33:23 +00:00
Elyes HAOUAS dc987fecce src/northbridge: Remove unused <stdlib.h> 
Change-Id: I7a214196b05d3af06c8cd742a6154b0627a0d82f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33685
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 05:33:02 +00:00
Elyes HAOUAS b12c2761f4 src/{drivers,device,ec}: Remove unused <stdlib.h> 
Change-Id: I05422ee4b0aa5c02525ef0b4eccb4dc3ecf871e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32822
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 05:25:56 +00:00
Elyes HAOUAS 94b503094f src/security: Remove unused <stdlib.h> 
Change-Id: I0b5c375baf7911ebced2f8c43a88aae014c877ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33694
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 05:24:07 +00:00
Elyes HAOUAS dda17fa222 src: Use '#include <smp/node.h>' when appropriate 
Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-12-19 05:23:25 +00:00
Elyes HAOUAS 88f107012a soc/qualcomm/sdm845: Remove unused 'include <timestamp.h>' 
Change-Id: I9b91184ee1daf4dd40f17984ef2a30756e845906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-12-19 05:18:51 +00:00
Elyes HAOUAS 4b463c71c0 mb/*/{BiosCallOuts,mainboard,romstage}.c: Remove unused <device/pci_{def,ops}.h> 
Change-Id: I4dcdcb734e20830ac97d4a826de61017afc6ee67
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-12-19 04:36:23 +00:00
Elyes HAOUAS aa57187f82 mb/*/*/early_init.c: Remove unused <device/pci_{def,ops}.h> 
Change-Id: I4cd9d22d2105c270a3d1e8a0be40b594c7c8b226
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37687
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 04:30:29 +00:00
Elyes HAOUAS e5476db4aa mb/{msi,pcengines}: Remove unused <stdlib.h> 
Change-Id: I282d02d58a5740369371a6f0bbdf7e900e3edc56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-12-19 04:27:50 +00:00
Elyes HAOUAS 4540a990a5 src/mainboard/amd: Remove unused <stdlib.h> 
Change-Id: I61982309a4110f4f40193190e91224e909b575a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-12-19 04:25:20 +00:00
Elyes HAOUAS b85fe66e39 mb/{asrock,asus}: Remove unused <stdlib.h> 
Change-Id: I14d3579f232b1dcc95b4e0653520686965dbe727
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-12-19 04:24:46 +00:00
Elyes HAOUAS 7104cdb375 mb/{cavium,opencellular,roda,scaleway,ti}: Remove unused <stdlib.h> 
Change-Id: Iad616e98feaebc6d5ec058fbf438ac2002a6b934
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33903
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 04:23:48 +00:00
Elyes HAOUAS 45f05a13ed mb/{hp,intel}: Remove unused <stdlib.h> 
Change-Id: Ib6151ac245870a198afb71909a36a0840480d567
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-12-19 04:23:23 +00:00
Elyes HAOUAS 98b0ae6561 mb/{gizmosphere,google}: Remove unused <stdlib.h> 
Change-Id: If99c8ea1aa437f261e8ab3c8a164d01be8bc58e9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-12-19 04:22:57 +00:00
Elyes HAOUAS 20a329718e mb/biostar: Remove unused <stdlib.h> 
Change-Id: I03d1af0858952972c92b83375a55dbda87e69f8a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-12-19 04:13:19 +00:00
Elyes HAOUAS 3f870446a6 src/arch/arm: Remove unused 'include <stdint.h>' 
Change-Id: I35f3559d68866a734666b3a18038bdae628703c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37501
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 04:10:12 +00:00
Elyes HAOUAS cbea47c744 src/soc/qualcomm: Remove unused <stdlib.h> 
Change-Id: I0bb44636f9ce6a9f96f5909926b586d0a6cedd9e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37383
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 04:07:13 +00:00
Elyes HAOUAS 8eeff1e0f4 src/soc/nvidia: Remove unused <stdlib.h> 
Change-Id: I404d149cd1052fa0aef233bd0e0867524c738477
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37382
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 04:06:52 +00:00
Elyes HAOUAS 43d5f7e8ea src/soc/rockchip: Remove unused <stdlib.h> 
Change-Id: Ifdfd37a59273c3647802bc7cb9774e61f90fe441
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37381
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 04:06:24 +00:00
Elyes HAOUAS c00d46353c src: Remove unused include <device/smbus_def.h> 
Change-Id: Idba48b2182d38dd4945044c79c393c3fd514d720
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35988
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 03:56:04 +00:00
Elyes HAOUAS 3c24a40d53 src: Remove unneeded 'include <delay.h>' 
Change-Id: Ibf91c35aa389a91116463616a778212bb386756e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34230
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 03:38:20 +00:00
Elyes HAOUAS add0b4712d src: Remove unused 'include <halt.h>' 
Change-Id: Ic25022bdba15219f79cfe172dc2512c3e18bca70
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35124
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 03:35:01 +00:00
Arthur Heymans 494b031eb7 arch/x86: Drop uses of ROMCC_BOOTBLOCK 
Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-12-19 03:26:27 +00:00
Arthur Heymans 1cb9cd5798 Drop ROMCC code and header guards 
Change-Id: I730f80afd8aad250f26534435aec24bea75a849c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-12-19 03:25:05 +00:00
Elyes HAOUAS 4f66cb9b28 src: Add missing include <types.h> 
Change-Id: Iabe55bfbc8e047c0791c21d162767081a181b6c5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37411
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 03:19:05 +00:00
Elyes HAOUAS 3917904878 vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c: Add missing <stdlib.h> 
Change-Id: I70029700bfb297ac06561056da730731a2ca1e8b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33682
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 03:17:51 +00:00
Elyes HAOUAS c184e65ed9 vendorcode/cavium/bdk/libbdk-hal/device: Add missing <stdlib.h> 
Change-Id: I64876a2b6cffdabf3e365fc07017adb14f086ecc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37380
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 03:17:29 +00:00
Elyes HAOUAS 025cb700a1 vendorcode/cavium/bdk/libbdk-hal: Add missing <stdlib.h> 
Change-Id: Id52603c525cce1bead423d188e23f6efd50511a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37377
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-19 03:17:10 +00:00
Aaron Durbin 6dc2fda469 Revert "include/cpu/x86: Add STM Support" 
This reverts commit 297b6b862a.

Reason for revert: breaks smm. No code is using these fields. Original patch incomplete.

Change-Id: I6acf15dc9d77ed8a83b98f086f2a0b306c584a9b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37096
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-18 18:16:03 +00:00
Elyes HAOUAS 1a8dbfc899 cpu/x86/mp_init: Fix typo 
Change-Id: Iee9cd3dc51937774b990bc6f9e00bb82e0132e76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37811
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-18 16:29:15 +00:00
Elyes HAOUAS eb34d8bf18 src: Remove unused 'include <bootblock_common.h>' 
Change-Id: I9eedae837634beb5a545d97fdf9c1810faba5138
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37271
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-18 15:48:22 +00:00
Elyes HAOUAS f0b79daeba src: Remove unused 'include <pc80/mc146818rtc.h>' 
Change-Id: I72d7b83ef8c7f9b5b4b4376839279eff9b0a5f8f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37484
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-12-18 15:45:02 +00:00
Joel Kitching 85d44f4a5e vboot: remove 2lib headers from Makefile 
Only headers from firmware/lib should be imported.
As far as I can tell, nothing imports 2lib headers
directly anymore, so we can get rid of this CFLAG.

BUG=b:124141368, chromium:968464
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ie5f3fe1d0180113b332e57ed07d4cfe563e7ecf2
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-12-18 09:47:40 +00:00