7d30f2e754
start of 970 port
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-19 18:18:10 +00:00
e7884d1a36
start of 970 port
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-19 18:07:22 +00:00
58b971e799
start of 970 port
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-19 18:03:08 +00:00
1cf26a8884
We are adding this obsolete, deprecated part to support the momentum
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apache board. We're not filling in all the support, since it appears
nobody uses this part. If you really need parallel port support, add it.
We hope to remove this part in future if the only board using it
moves to a newer part.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-19 17:35:18 +00:00
20d943d9f9
adding support for dell 1850
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-19 17:02:34 +00:00
3182cad1a3
added the s1850
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-19 17:01:17 +00:00
ab327a3c08
- Added explanation of device tree enable.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-13 00:44:34 +00:00
6ab43fcc48
Updating FSF address in the code.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-05 18:17:45 +00:00
5dab7d650f
CK804 sata fix
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-01 07:32:04 +00:00
803719a22d
comments mods. THings are working better, so I'm less unhappy with
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this part :-)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-26 16:48:24 +00:00
a4baa1673e
* Added support for "fast" (64-clock) refresh
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* Added code to support remap window for 3 - 4 GB systems
* Fixed premature configuration of true row boundaries that resulted in some sections of DRAM not receiving JEDEC commands (see http://openbios.org/pipermail/linuxbios/2005-June/011752.html ).
* Redefined RCOMP_MMIO so that RCOMP registers can be configured on systems where A20M# is asserted.
* Disabled subsystem (vendor) ID configuration
* #ifdef'd out suspicious looking code (see http://openbios.org/pipermail/linuxbios/2005-June/011759.html )
* Added optional run-time checking of dual-channel compatibility of installed DIMMs
* Move JEDEC SPD and SDRAM definitions into reusable #include files
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-26 13:54:32 +00:00
87888630b2
sc520 support -- ethernet works
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-23 17:08:58 +00:00
a25120a30f
Bug fixes: read all 16 bits of DMA configuration; set up NMI/SERR handling in I/O space not PCI space. Comment out posted-memory-write code that looks to have been mis-inherited.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:54:18 +00:00
ef79223156
Bug fixes: read all 16 bits of DMA configuration; set up NMI/SERR handling in I/O space not PCI space. Comment out posted-memory-write code that looks to have been mis-inherited.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:53:44 +00:00
b140d56f63
Bug fix: enable secondary IDE only if enable_b is set.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:51:30 +00:00
3cec9c8433
Bug fix: enable secondary IDE only if enable_b is set.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:51:12 +00:00
b3d2d4d441
Rewrite i82801er_enable to do nothing if device does not have an enable/disable bit.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:50:38 +00:00
7557331605
Rewrite i82801dbm_enable to do nothing if device does not have an enable/disable bit.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-21 13:49:44 +00:00
e355b2ac60
Cleanup and add more debug output to EPIA-M auto.c.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 16:33:43 +00:00
1718c4771b
Make EPIA-M use CONFIG_TSC.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 16:33:10 +00:00
708743379a
Clean up vt8235_early_smbus a bit.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 16:18:30 +00:00
85793c2b3f
Rename Intel 82801CA constants.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 15:40:07 +00:00
706aed8eb9
Initial revision.
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Based on i82801er and LB v1 code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 15:34:03 +00:00
09e4ef6702
Cleanup. Only functional change is to drop hard-coding of vendor/subsystem ID.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:56:25 +00:00
eb065f0620
Add some P64H2-specific definitions, remove some generic PCI ones.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:55:41 +00:00
af0cf12eff
Initial revision.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:54:32 +00:00
eccc357ea0
Abort cpu_initialize if we detect that we've lost a race.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:53:45 +00:00
059182cc4f
Print a failure message if a sibling CPU fails to start.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:52:06 +00:00
0b1a5a4a92
Initial support for Intel XE7501DEVKIT.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:49:04 +00:00
ffc83041b7
Initial support for Intel XE7501DEVKIT.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:48:32 +00:00
71ad2f48c5
Moved E7501-specific definitions here from raminit.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-13 14:56:44 +00:00
61764f45dc
Initial revision.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-13 14:54:25 +00:00
e91619ac05
Initial revision.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 18:55:23 +00:00
8cbc4751d1
Don't write to CMOS when HAVE_OPTION_TABLE = 0.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 18:43:27 +00:00
d94e1d6e9d
Relocate the GDT to reserved memory, so it won't get clobbered by elfboot(), etc.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 18:41:30 +00:00
9b945c7cd8
Attempt to make comments more descriptive.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 18:40:00 +00:00
a7c70bcb3a
Fix hang during secondary CPU sibling init caused by nested spinlocks.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 18:38:10 +00:00
e50570112f
sc520 now builds fine. On to testing.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 15:20:28 +00:00
e118a047b9
moved to include/cpu/amd/sc520.h
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 13:43:59 +00:00
64473580ff
added include file for sc520
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 13:42:56 +00:00
c06ca3af71
updated to new svn repo
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 13:42:12 +00:00
ccf52a92f4
updating to working version from my pre-svn repo.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12 13:40:10 +00:00
2f25710285
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-09 21:03:08 +00:00
9a83c99bb9
Modifications for building LinuxBIOS under cygwin.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-09 20:06:21 +00:00
fc8a3d2c35
Remove unnecessary #include that prevents cross-compilation with gcc 3.4.3 under Cygwin.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-09 20:05:03 +00:00
740bb2a8ed
Correct transposed arguments in pnp_set_drq().
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-09 20:02:52 +00:00
246ae2129e
simplify code
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-08 17:17:25 +00:00
afa190e046
Add VIA C3 Nehemiah CPUID, as reported by Doug Bell.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-05 09:30:01 +00:00
ded1368b1a
Crude fixup of config files currently non parsable by buildtarget.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-29 09:54:25 +00:00
e251c42197
Changed udelay in delay_tsc to be more be more considerate of single
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processor environments.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-17 04:48:17 +00:00
Greg Watson