Commit Graph

36181 Commits

Author SHA1 Message Date
Angel Pons bea5ce7a4b arch/x86/smbios.c: Split out weak functions
The `smbios.c` file is rather long. To improve navigability, place weak
function definitions on a separate compilation unit.

Change-Id: Idd2a4ba52b6b23aad8fd63e66ffa747d49ea713d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:47:39 +00:00
Angel Pons 9630ced250 arch/x86/smbios.c: Factor out switch-case block
Most of `smbios_fill_dimm_manufacturer_from_id()` is noise. Factor the
switch into its own function to improve readability.

Change-Id: Ia0757c01572709d16589a4ed622ca2d2cb69dda2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:47:17 +00:00
Angel Pons 3c13da7897 arch/x86/smbios.c: Simplify assignment
We can reduce the amount of duplicated code with a ternary operator.

Change-Id: I8be95a62c54749d39e3e8821abd46d9f467a5a49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:47:02 +00:00
Angel Pons bf2f91c87c arch/x86/smbios.c: Clean up cosmetics
Put `__weak` at the beginning of functions and reflow lines to leverage
the increased line width of 96 characters.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I3a5fd2d4344b83e09f89053c083ec80aa297061e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:46:53 +00:00
Patrick Rudolph 42609d807b nb/intel/*: Fill in SMBIOS type 16 on SNB/HSW
Fill in the maximum DRAM capacity and slot count read from CAPID0_A
registers on Sandy Bridge and Haswell.

While the register isn't part of the Core Series datasheet, it can be
found in the corresponding "Intel Open Source Graphics Programmer's
Reference" datasheets.

Note that the values for DDRSZ (maximum allowed memory size per channel)
need to be halved when only one DIMM per channel is supported. On mobile
platforms, all but quad-core processors are subject to this restriction.

Tested on Lenovo X230:
On Linux, verify that `dmidecode -t 16` reports the actual maximum
capacity (16 GiB) instead of the currently-installed capacity (4 GiB) or
the max capacity assuming two DIMMs per channel is possible (32 GiB).

Change-Id: I6e2346de1ffe52e8685276acbdbf25755f4cc162
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-30 22:45:54 +00:00
Patrick Rudolph 5e007808cd smbios: Fix type 17 for Windows 10
The `GetPhysicallyInstalledSystemMemory` API call, at least on Windows
10, returns an error if SMBIOS tables are invalid. Various tools use
this API call and don't operate correctly if this fails. For example,
the "Intel Processor Diagnostic Tool" program is affected.

Windows then guesses the physical memory size by accumulating entries
from the firmware-provided memory map, which results in a total memory
size that is slightly lower than the actual installed memory capacity.

To fix this issue, add the handle to a type 16 entry to all type 17
entries.

Add new fields to struct memory_info and fill them in Intel common code.
Use the introduced variables to fill type 16 in smbios.c and provide
a handle to type 17 entries.

Besides keeping the current behaviour on intel/soc/common platforms, the
type 16 table is also emitted on platforms that don't explicitly fill
it, by using the existing fields of struct memory_info.

Tested on Windows 10:
The GetPhysicallyInstalledSystemMemory API call doesn't return an error
anymore and the installed memory is now being reported as 8192 MiB.

Change-Id: Idc3a363cbc3d0654dafd4176c4f4af9005210f42
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-30 22:31:24 +00:00
Matt Papageorge 95c42c3b04 mb/amd,google/mandolin,zork: Set EFS SPI platform config
Set platform defaults for SPI settings in Kconfig for EFS.

BUG=b:158755102
TEST=Build and boot test on Tremblye and Morphius. Verify
values in output image in a hex editor. Measure 1st x86
timestamp, perf improves by over a second.

Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 20:55:26 +00:00
Aaron Durbin 80e2dd8854 mb/google/zork: remove indirection for dxio lane configuration
There was a mix of open coding DXIO logical lane numbers and clkreq
pins. And there are separate macros depending on the baseboard
as well as processor type. Remove the indirection and supply the values
directly in the descriptors.

BUG=b:162423378

Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-30 20:05:55 +00:00
Jan Dabros 821b1e2f28 lib/bootmem.c: Improve bootmem_allocate_buffer algorithm
Since regions in bootmem are sorted by increasing base address, we may
bail out of the search loop as soon as the region_base is bigger than
the max address allowed.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I44b44bf9618fd0615103cbf74271235d61d49473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43512
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 17:13:28 +00:00
Marshall Dawson 1756e10a34 vc/amd/picasso/bl_uapp: Update header file
Update to match the 0.8.5.7B release of PSP blobs.

BUG=b:162057232
TEST=Boot Trembyle with, and without, new blobs.  Inspect vboot
     using a serial-enabled bootloader

Change-Id: I03f11cfc1dc8f511661def1c81421f8558dcd1f5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44041
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 16:41:12 +00:00
Marshall Dawson a1e578cc15 3rdparty/amd_blobs: Move pointer to 0.8.5.7B
BUG=b:162057232

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ifd4ac0655f7ada5ec10a266fdb2b930861959215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44040
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 16:40:58 +00:00
Matt Papageorge 8d481b4e9a amd/common/block/spi: Add EFS SPI configurations to Kconfig
The Embedded Firmware Structure should contain SPI speed, mode
and Micron support for the PSP to program. Add Kconfig options
to specify these values to use for future platform changes.

BUG=b:158755102
TEST=Test menuconfig and platform build for Trembyle and Mandolin.

Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42567
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 16:26:44 +00:00
Furquan Shaikh 27c9762f95 soc/amd/picasso: Split ops for internal and external PCIe GPP bridges
This change splits the device operations for internal and external PCIe
GPP bridges so that the external bridges use `pciexp_scan_bridge()`
instead of `pci_scan_bridge()`. `pciexp_scan_bridge()` is required for
external GPP bridges to enable ASPM on downstream devices if supported.

BUG=b:162352484
TEST=Verified on Trembyle:
$ lspci -s 1:00.0 -vvv | grep ASPM
LnkCap: Port , Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 <64u
      ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice2aa3e4758adccf7b0b89d4222fc65a40761153
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-30 15:58:28 +00:00
Lucas Chen 23ade0ee15 mb/google/zork/var/ezkinil: Configure boot media for new SKUs
Configure the correct eMMC present flag for Ezkinil new added sku_id.
0x5A020015  NVME present
0x5A020016  eMMC present
0x5A020017  eMMC present

BUG=b:159761042
TEST:none

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I1b89cc4568283d5dbebf0ab7ac578368d3a3637e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43753
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 15:17:06 +00:00
Felix Held e2379969e5 mb/google/zork: add USB over-current pin mapping to devicetree
BUG=b:162010077

Change-Id: Iba3e3ec62cdfd818077017abd28fa754c2ae7797
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-30 15:01:04 +00:00
BryantOu d9da698bbd mb/ocp/tiogapass: Add SMBIOS type8 data table
According to MP MB to port SMBIOS type8 data.

Tested=Use "dmidecode -t 8" to dump SMBIOS data,
and check if type8 tables are implemented.

Change-Id: I356e645774d78c623c1398c8b1473562e1529cf2
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-30 09:18:50 +00:00
Johnny Lin 5ea5336b6e mb/ocp/deltalake: Add VPD variable for FRB2 timer action
Tested on OCP Delta Lake, the timer action can be set correctly.

Change-Id: I1013169e12455e01214d089c9398c78143af4df8
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44019
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 09:11:50 +00:00
Evan Green b96d9b6e2f mb/google/dedede: Add Goodix touchscreen
Add overridetree info for the touchscreen.

BUG=b:160129126
TEST=cros flash-ap -b dedede

Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I55fc0749b824a0bf4b615d02bd8bc39bcdd589e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-30 05:26:42 +00:00
John Zhao efcfaa8b6c mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration
It is expected both of TCSS D3Hot and D3Cold are enabled by default.

BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on TGLRVP.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Id569d8191f82f12379b57a9c50aec31776220bb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-29 22:46:57 +00:00
John Zhao 5fdf2760a5 mb/google/volteer: Update TCSS D3Hot and D3Cold configuration
It is expected TCSS D3Hot is enabled. D3Cold configuration is
through SoC stepping determination. D3Cold is disabled on pre-QS
platform and enabled on QS platform.

BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 22:46:45 +00:00
John Zhao bd615d6f93 soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold
Update configuration for both of TCSS D3Hot and D3Cold. It is expected
D3Hot is enabled for all platforms. Because there are known limitations
for D3Cold enabling on pre-QS platform, this change reads cpu id and
disables D3Cold for pre-QS platform. For QS platform, D3Cold is
configured to be enabled.

BUG=None
TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0)
and enabled for QS (cpu:0x806c1).

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43980
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 22:46:29 +00:00
Felix Singer 048d9b5cba soc/intel/skylake: Enable HDA depending on devicetree configuration
Currently HDA gets enabled by the option EnableAzalia, but
this duplicates the devicetree on/off options. Therefore use
the on/off options for the enablement of the HDA controller.

I checked all corresponding mainboards if the devicetree configuration
matches the EnableAzalia setting.

Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 21:04:24 +00:00
Felix Singer 91dfb92038 soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Currently HECI3 gets enabled by the option Heci3Enabled, but
this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the HECI3 controller.

I checked all corresponding mainboards if the devicetree configuration
matches the Heci3Enabled setting.

Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 20:58:58 +00:00
Felix Singer aff69be254 soc/intel/skylake: Enable eMMC depending on devicetree configuration
Currently eMMC gets enabled by the option ScsEmmcEnabled, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the eMMC controller.

I checked all corresponding mainboards if the devicetree configuration
matches the ScsEmmcEnabled setting.

Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-29 20:57:39 +00:00
Felix Singer 87aecf811d soc/intel/skylake: Enable TraceHub depending on devicetree configuration
Currently TraceHub gets enabled by the option EnableTraceHub, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the TraceHub controller.

I checked all corresponding mainboards if the devicetree
configuration matches the EnableTraceHub setting.

Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 20:57:21 +00:00
Felix Singer ffe90c528b soc/intel/skylake: Enable SMBus depending on devicetree configuration
Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.

I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.

Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-29 20:47:56 +00:00
Felix Singer 57c8143350 soc/intel/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.

I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.

Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-29 20:45:53 +00:00
Felix Singer 0901d03085 soc/intel/skylake: Enable SATA depending on devicetree configuration
Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.

I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.

Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-29 20:45:29 +00:00
Kevin Chiu 3c0486913f mb/google/zork: update stapm parameter for berknip
sustained_power_limit = 12w
fast_ppt_limit = 24w
slow_ppt_limit = 20w

BUG=b:162377903
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage

Change-Id: I9baf9990e26edbbadfba85bc16b380c46684033d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-29 14:43:24 +00:00
John Zhao d05b15e860 mb/intel/tglrvp: Add support for USB Type-C connector device properties
This change updates TGLRVP configuration to have USB Type-C connector
device properties filled into ACPI SSDT.

TEST=Built and booted to kernel on tglrvp boards. Verified the USBC
scope under LPCB.EC0.CREC with required connector device properties.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-29 09:38:38 +00:00
Elyes HAOUAS c379d46c1c src/soc/rockchip: Add missing <{stddef,stdint}.h>
Change-Id: I0b7bdd9f46846bc9c3d9672b50dfe2fb166fcb78
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-29 09:37:22 +00:00
Elyes HAOUAS 441e191530 src/acpi: Add missing <{stdbool,stdint}.h>
Change-Id: Ic09c04cfa18408c61d7e99ea29bccc23acbd7144
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-29 09:37:10 +00:00
Jonathan Zhang b84bd303ee doc/getting_started: update name of file generated by "make savedefconfig"
Update kconfig.md to reflect that defconfig (instead of mini-config)
file is generated by running "make savedefconfig".

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4075e5b51e3c504eaad25e3abfc52ba593364ee9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-29 09:36:33 +00:00
Duncan Laurie 3715785a49 soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dB
The HSIO tuning guide recommendation for the default USB3 settings is to
have de-emphasis set to -3.5dB with the equation 20*log(X/64).  0x29 results
in a value close to -3.5dB and it is the value that was used for the default
on past platforms so I used it here as well.

BUG=b:160721468
TEST=Ensure WWAN device does not disconnect during use.

Change-Id: Ia594996cb55523dacce0d4bef98cc217321c62de
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-29 09:36:11 +00:00
Karthikeyan Ramasubramanian 70b73cfc78 mb/google/dedede/var/magalor: Generate SPD ID for supported parts
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR

BUG=None
TEST=Build the magalor board.

Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-29 09:35:29 +00:00
Usha P a5f9a4ae91 soc/intel/jasperlake: Clean up report_cpu_info() function
This patch uses the fill_processor_name function in order
to fetch the CPU Name.

TEST = Successfully able to build boot Waddledoo and verify the
cpu_name from CPU log "CPU: Genuine Intel(R) CPU 0000 @ 1.10GHz".

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I532e05d9bb71fdff24e086e81ec72ffe8dc2c22d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43480
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 09:35:19 +00:00
Rob Barnes ce036bd176 util/apcb: Strip SPD manufacturer information
Strip manufacturer information from SPDs before injecting into APCB.
This allows more flexibility around changing DRAM modules in the future.

BUG=b:162098961
TEST=Boot, dump memory info

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-29 09:35:05 +00:00
Elyes HAOUAS 7884c22f1f src/soc/samsung/exynos{5250,s5420}: Add missing <{stddef,stdint}.h>
Change-Id: I34b8083eb14d5f82699cf92744000a416d2816ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-29 09:34:55 +00:00
Angel Pons 9a5dd7accf lib/libgcov.c: Do not redefine `alloca`
This is already defined in <commonlib/helpers.h> and it gets included
implicitly by some other header. Fixes building with code coverage.

Change-Id: Id2dc6cc34b6f1d351d8e1b52d8cc4ada8666c673
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-29 09:27:33 +00:00
Michael Niewöhner 2a28c81614 mb/supermicro/x11-lga1151-series: correct superio interrupts
Add interrupts for all enabled superio devices to quiet the warning
about missing interrupts in devicetree.

Vendor uses interrupt 0x00 for all devices except SUART* and KBC, so
let's do that, too. This also changes SWC from 0x0b to 0x00.

Verified with superiotool on X11SSM-F.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7a6dc7345f020e53415a7d0d104ce93ab4b194fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonas Löffelholz
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-29 09:25:49 +00:00
Patrick Georgi 71a22e3cfc Documentation: Revise "24 hours wait period" rules
They're more or less the same but reworked for hopefully some more
clarity. There have been some best practices around documenting the
reason for expedited processing so let's make them official, too.

Change-Id: I620e48016a1ceda2ac43f26624ed21af01f6a0a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 09:18:26 +00:00
Johnny Lin dcc2eb9a93 mb/ocp/tiogapass: Configure IPMI FRB2 watchdog timer via VPD variables
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value in romstage. By default it would start the timer
and trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.

Add RO_VPD and RW_VPD sections.

Tested on OCP Tioga Pass.

Change-Id: I53b69c3c5d22c022130fd812ef26097898d913d0
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-29 08:39:29 +00:00
Tim Wawrzynczak a9d3e652f7 acpi: Fix dptf_write_fan_perf to include Revision field
When emitting a fan's _FPS (Fan Performance States) table, the revision
field was missing. According to ACPI spec 6.3, the current revision is
zero, so add that Package entry before the others.

BUG=b:149722146
TEST=verified first element of \_SB.DPTF.TFN1._FPS is 0

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If16d4751f1d924807f5087d93b348e58d5265197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43978
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 22:17:55 +00:00
Maxim Polyakov 82ec61e9d7 util/intelp2m: Add Intel Pad to Macro utility
This patch adds a new utility for converting a pad configuration from
the inteltool dump to the PAD_CFG_*() macros [1] for coreboot and GPIO
config data structures for FSP/sdk2-platforms/slimbootloader [2,3].
Mirror: https://github.com/maxpoliak/pch-pads-parser.git

[1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
[2] https://slimbootloader.github.io/tools/index.html#gpio-tool
[3] 3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h

Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35643
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 22:06:02 +00:00
Marshall Dawson 8079c5c1c2 soc/amd/picasso: Add controls for SMT and downcoring
BUG=b:159198385
TEST=confirm both using Mandolin

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I91654817608ab62e4104959b8876333911b90175
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 20:21:07 +00:00
Elyes HAOUAS 553a22e316 src/soc/amd: Add include <types.h>
BIT(x) needs <types.h>.

Change-Id: Icaeda969cae52d9c62d976db4ead0e734efa838c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28 19:29:01 +00:00
Rob Barnes 56e889cedb mb/google/zork: Add Bluetooth reset gpios to devicetree
Add bluetooth reset gpio 143 to dalboz baseboard devicetree
Add bluetooth reset gpio 14 to trembyle baseboard devicetree
Remove bluetooth reset_gpio when not supported on a specific board
variant.

BUG=b:157580724
TEST=Boot Ezkinil with Realtek 8822CE, observe log
[   12.240720] Bluetooth: af_bluetooth.c:bt_init() HCI device and connection manager initialized
[   12.249272] Bluetooth: hci_sock.c:hci_sock_init() HCI socket layer initialized
[   12.256520] Bluetooth: l2cap_sock.c:l2cap_init_sockets() L2CAP socket layer initialized
[   12.264575] Bluetooth: sco.c:sco_init() SCO socket layer initialized
[   12.273700] usb 3-2: GPIO lookup for consumer reset
[   12.273702] usb 3-2: using ACPI for GPIO lookup
[   12.273705] acpi device:18: GPIO: looking up reset-gpios
[   12.273707] acpi device:18: GPIO: looking up reset-gpio
[   12.273711] acpi device:18: GPIO: _DSD returned device:18 0 0 0
[   12.273737] gpio gpiochip0: Persistence not supported for GPIO 14
[   12.273960] usbcore: registered new interface driver btusb

Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-28 19:28:30 +00:00
Rob Barnes a223e65db2 device: Add find_dev_nested_path helper function
Add find_dev_nested_path helper function to simplify finding deeply
nested devices.

BUG=b:157580724
TEST=Find bluetooth device on dalboz

Change-Id: I48fa5fcad0030fb6dcea97b9fc76e1d3d3f9b28f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-28 19:28:22 +00:00
Martin Roth e7e6c4e1d7 soc/amd/picasso: Enable VBNV_BACKUP_TO_FLASH for psp_verstage
Enable the Kconfig flag VBOOT_VBNV_CMOS_BACKUP_TO_FLASH for psp_verstage
to save the vbnv data to the SPI rom.

BUG=b:161366241
TEST=Boot Morphius, Read rom from SPI and extract the RW_NVRAM region.
See that it's getting updated.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0d4b92fa321a8409468b8d8fc40be0d4b57b664b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43487
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 19:25:06 +00:00
Martin Roth e52edfcbff soc/amd/picasso: Init SPI in psp_verstage
SPI needs to be initialized to save VBNV (Vboot Non-Volatile memory)
to flash.

BUG=b:159811539
TEST=Build & boot.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iebf3ed3f5d6be0dda717d91d5b2fbcf2a1cc43cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-28 19:24:57 +00:00