GPIOs for I2C3 were being unset in amdinitmid if the GPIO
enable table wasn't passed. It had been initialy set in amdinitreset.
Pull the GPIO settings into their own file that can be used in
bootblock and later stages.
Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly
report in the FADT.
Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19836
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the basics for building as a ChromeOS device. ChromeOS
and ChromeEC are dependent on each other, so bring them in
together. The EC is a Nuvoton and you can find additional
details in the Chromium EC repo.
Add the Google HWID "Kahlee TEST 6421".
The chromeos.fmd for Kahlee takes advantage of the AGESA
located outside cbfs and includes typical RW, VPD, and
MRC areas.
There are some updates required to depthcharge, vboot, GPIOs,
and the ChromeEC before we have a complete-ish system.
Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update GPIO settings based on the schematic.
Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update for a single DIMM with an SPD at address A0.
Change-Id: I646f079c99cbaffd7094773243600c3030308325
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19833
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee does not use the AMD IMC. Remove the files and calls.
Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19832
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update for the Stoney Ridge FT4 package and the on chip UART.
Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19831
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copied from amd/gardenia. Update the appropriate board name strings.
Uses the soc/ structure.
Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the unused support code from the old multi-device hudson
SD controller. The binaryPI blob contains the correct steps
for setting up SD and the public BKDG doesn't completely document
the controller.
The sd.c file was using device IDs not associated with the Stoney
Ridge APU. The hudson_enable() code removed was also looking for
incorrect device IDs and the PM_MANUAL_RESET register doesn't
behave as the source indicates.
The SD default settings may be overridden. Future improvements
may include a few Kconfig options and a weak call to the mainboard
for overriding additional defaults.
BUG=chrome-os-partner:62580062
Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Kconfig selects for vboot and update the makefile to pick up
files to be used in verstage.
Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19756
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The format of the D14F3xA0 SPI Base_Addr register is different
than a traditional BAR. Change the function to preserve any
enables already in place. Change the AND mask to remove the
reserved field and the enables.
Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The following changes have been applied for GPIO:
1. Correct port id using by GPIO community 3 for CNL-LP.
2. Correct number of doubleword for each pad from 2 to 4.
Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
AHCI spec explicitly states that we may poll.
TEST=Ran FILO on kontron/bsl6 and observed that the controller
always becomes ready during the first delay.
Change-Id: If34694abff14d719d10d89bc6771dbfa12065071
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is (thankfully) not done by coreboot any more for recent chipsets.
Change-Id: If56e38037f7b1e53871ee63e6ff297028c59d493
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The mc_apl1 mainboard needs to disable the RAPL algorithm for a constant
power management of the processor package. An active RAPL algorithm
leads to negative effects with our real time software.
Change-Id: I09ca56a034fd3896a000e64cac35f12fb507a682
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Apollo Lake SoC supports configuration of Running Average Power Limits
(RAPL) for package domain. This feature is not required for all APL
mainboards. According to the APL SoC EDS Vol 4 chapter 18.4 Power
Limiting Control it is not necessary to enable the RAPL algorithm per
default. For that reason make the RAPL configuration selectable.
Change-Id: Ib737b162f72b76c15e5768859f9099e2e7ef6426
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If we dont have a constant TSC rate, timestamp table
has odd leaps and may appear to run backwards. Add
functionality to apply a factor such that all stamps
are in the same timebase.
Change-Id: Idab9c2c00e117c4d247db8cc9a2897640fa01edd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively
for TPS68470 PMIC in daisy chain mode.
* GPIO.1: Sensor SDA in daisy chain mode.
* GPIO.2: Sensor SCL in daisy chain mode.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC1 and PMIC2,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.
* Port represents an interface in a device.
* Endpoint represents a connection to that interface.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: If328864dbb61586a4887c7fcae740a12eda7cc92
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds mipi_camera.asl and enables
I2C2, I2C3, CIO2 and IMGU devices,
* Add TPS68470 PMIC1 and PMIC2 related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
KBLRVP has two PMIC's sitting on I2C2 and I2C3. CAM0 and
CAM1 power requirements are handled by PMIC1 and PMIC2 respectively.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: Ibaf26dad74ca1e7c9f415ae75c4ed8558ad99e2f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
init_igd_opregion itself is supposed to return cb_err so this adds
error handling, just like other implentations of write_acpi_tables do it.
this had been found by coverity:
*** CID 1378270: Error handling issues (CHECKED_RETURN)
/src/soc/intel/skylake/igd.c: 147 in write_acpi_igd_opregion()
141 /* If IGD is disabled, exit here */
142 if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)
143 return current;
144
145 printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
146 opregion = (igd_opregion_t *)current;
CID 1378270: Error handling issues (CHECKED_RETURN)
Calling "init_igd_opregion" without checking return value
(as is done elsewhere 5 out of 6 times).
147 init_igd_opregion(opregion);
148 update_igd_opregion(opregion);
149 current += sizeof(igd_opregion_t);
150 current = acpi_align_current(current);
TEST=Built
Change-Id: If6f5d53037f093607d89cfe8faf193d55de7f6c4
Found-by: Coverity (CID 1378270: Error handling issues (CHECKED_RETURN))
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/20766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.
Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sets RAPL PL1 power to ~6W.
Note: 7.5W setting gives a run-time 6W actual measured power.
Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime
and comparing to measured power on an instrumented board.
Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/19746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1
GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)
By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC
config.
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use a `for` instead of a `while` loop and use meaningful identifiers.
Also, don't use more than one variable for one and the same purpose,
don't use more (non-const) variables than necessary, don't alter more
than one variable per statement, don't compare pointers of different
types and don't do pointer arithmetic on `void *`.
This was meant as a fix up to a regression but that has already been
fixed.
Change-Id: I0c8fd118d127a26cfcf68bfb0bf681495821e80a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This line has a weird history. It got a `|| exit 0` removed lately which
obviously was there to fix the presence of the superfluous `test` at the
beginning. Now, remove the `test` too to make the clean target always
succeed again ;)
Change-Id: I9e069cf5d9ac8416cf350161439aa60798ef7b6b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20769
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The values were verified to be correct with the KabylakeFsp0001 from
github. Skylake FSP documentation disagrees so YMMV.
Change-Id: I1ee04dbbed48d5376dbc24ae70753b059f2646eb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20765
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SMBIOS memory HOB produced by glk FSP v52_27 has new structure
members, which are not available in current apl FSP. New FSP-m
header file in https://review.coreboot.org/#/c/20673/ lists new
SMBIOS structure members.
Break memory HOB save routine into different functions for glk
and apl to accomodate new changes.
Change-Id: I33c6e4f2842cebbb326b6a05436fa69e3836ffc6
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20674
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current implementation of itss_irq_init() uses 8 bit write access to
IRQ routing registers which is not supported on Apollo Lake.
This commit moves the register access from 8 bit to 32 bit so that this
function can be used with every platform.
Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the OEM settings for two ports. Fix and clarify comments to
reflect Rev. B of the board design.
Change-Id: I2812ea5945f67229872e78041c771606047bbbec
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20744
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Interrupt 11 is not used by legacy devices and so can always be used
for PCI interrupts. Full legacy IRQ routing is complicated and hard to
get right.
Change-Id: I6c718f4b9fb91ffcc4a136120581a4fcd7ec7231
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fixes warning by GCC 7.1:
note: did you mean to use logical not?
Change-Id: If8167c6fe88135ae89eb795eeda09e6937b1684f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Make sure to set only one bit instead of arbitrary bits set in argument.
Change-Id: I39426193d15d8581f79bc2a45c0edb53b19a2cd3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The full path to the passed/failed build lists needs to be specified.
On the builders, the absolute path is passed in, which conflicted with
the ${TOP} value, causing this to fail on the builders. When TOP was
removed from the path, the builders worked correctly, but it failed when
run locally. This fixes the path in either case.
Change-Id: Ia4370f4a2b84991edccfc723a3136b88ca27db7d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
coreboot was setting SPI FPR register to protect the
mrc_cache data range stored in flash. This programming was being done
after FSP Notify 1.
But, FSP was locking the SPI by setting FLOCKDN Bit during Notify
phase 1, due to which coreboot was unable to protect that range.
As solution, FSP introduced a new UPD SpiFlashCfgLockDown to skip
the lockdown of flash on interest of bootloader. Set that UPD to 0
to skip the lockdown of FAST_SPI flash from FSP.
The same is being done from coreboot after end of Post at finalize.c
file.
BUG=b:63049493
BRANCH=none
TEST=FPR can be set properly to protect the mrc_cache range. The
issue reported in the bug doesn't come when both software and
hardware WP is enabled with this patch.
Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A new UPD named SpiFlashCfgLockDown is added in the FSP-S
header file.
This change is going to come in FSP in the next FSP release.
This patch is pushed to urgently fix the SPI FPR locking issue.
CQ-DEPEND=CL:*414049
BUG=b:63049493
BRANCH=none
TEST=Built and boot poppy
Change-Id: I4725506103781a358b18ee70f4fdd56bf4ab3d96
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Marshall Dawson