Commit Graph

23014 Commits

Author SHA1 Message Date
Patrick Georgi 214dde058c crossgcc: fix edk2 tools_def template
Forgot the /bin/ part of the executable paths

Change-Id: I87d63ec18338e376787d02bb771471e746a17b62
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22640
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-30 16:51:16 +00:00
Subrata Banik a6802ec30f mb/google/poppy/variants/soraka: Set PCH thermal trip point to 75 degreeC
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.

BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.

Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30 16:27:20 +00:00
Subrata Banik 771d611f9e soc/intel/skylake: Set low maximum temperature threshold for Thermal Device
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.

BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.

Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30 16:27:12 +00:00
Chris Wang 94dc50e810 mb/google/nautilus: add synaptics touch screen support
Add synaptics touchscreen in the device tree so that the correct ACPI
device is created.

BUG=b:66462881
BRANCH=master
TEST=compiled/verify the touchscreen works

Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30 16:19:08 +00:00
V Sowmya 45a21381d6 soc/intel/{APL,GLK}: Use Intel SRAM common code
TEST:Build and boot reef. Verified that SRAM common code
is used to set the resources.

Change-Id: If9f5d400df09b4a0aa4b464d7f1f24320696b0aa
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/22608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-30 06:38:50 +00:00
V Sowmya c333b98fb8 soc/intel/common: Add Intel SRAM common code support
Add SRAM code support in intel/common/block to read
and use fixed resources on BAR0 and BAR2 for SRAM.

Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/22607
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-30 06:38:44 +00:00
Furquan Shaikh a3a84565af chromeec: Notify CREC device of wakeup events
Whenever there is a new EC event that could be wake-capable, notify
CREC device of this using notification value 0x2 i.e. device
wake. This allows Linux kernel to track active_count value correctly
for CREC device.

BUG=b:69118395
BRANCH=None
TEST=Verified on Soraka:
1. Put device into suspend
2. Wake up using mode change/lid open
3. Check that the active_count for GOOG0004 has increased
(cat wakeup_sources | grep GOOG0004)

Change-Id: I723f7f4e4c99e7a5b57c6296da66cf30cd413c27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-30 01:52:53 +00:00
Marc Jones a9f72776bd soc/amd/stoneyridge: Add mainboard call for SPD values
Add a mainboard function call to write the AGESA SPD buffer.
Removes the unneccesary dimm_spd.c file.

BUG=b:67845441

Change-Id: Id42622008b49b4559e648a7fa1bfd9f26e1f56a4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-29 23:58:06 +00:00
Marc Jones fede56bf81 google/kahlee: Add SPD function
Add the mainboard_spd_read function in romstage and call the variants
function. Grunt is the baseboard and has soldered down memory, so add
it for the default weak SPD functions and build the SPDs in cbfs.
Kahlee overrides the weak SPD function and falls back to the soc
I2C SPD functions.

BUG=b:67845441
TEST=Build and boot Kahlee.

Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-29 22:36:49 +00:00
Marc Jones 71f7f0a8f8 google/kahlee: Rename board_id to memory_sku
The GPIOs used in board_id are meant to indicate the memory
configuration. Rename board_id to memory_skus.

Report the board_id received from the EC.

BUG=b:69649438

Change-Id: I84bacead3daf829c97f595c4c11a243953243c29
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22561
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-29 22:35:05 +00:00
Furquan Shaikh ab85c45326 mb/google/poppy/variants/nautilus: Disable camera devices
This change disables camera devices until camera support is properly
added for nautilus.

Change-Id: I7de37cbf9c32fa063f55a2e54986e33b66acfa3b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-29 00:11:34 +00:00
Furquan Shaikh 6d0c7bc77a mb/google/poppy: Add variant support for camera asl
This change adds infrastructure to allow variants to define their own
camera.asl file.
- Poppy and soraka use the one provided by baseboard.
- Dummy file is added for nautilus since it does not have camera
support enabled yet.

TEST=Verified that DSDT table remains the same with and without this
change.

Change-Id: I0f0b489e74739aa4708283d58d8b7626b77a89a3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-29 00:11:26 +00:00
Subrata Banik fb15d463d2 soc/intel/skylake: Make use of Intel common DSP block
TEST=Build and boot soraka/eve.

Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28 20:29:36 +00:00
Lin Huang add7666a47 google/scarlet: support kd097d04 panel
Support kd097d04 dual mipi panel on Scarlet.

Change-Id: Ie8bc0cbb79840f1924a8cc111f2511292203731f
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28 19:17:56 +00:00
Lin Huang 18617bf21b google/gru: correct backlight gpio
it uses backlight enable pin as backlight gpio currently,
correct it and define the right backlight gpio.

Change-Id: I7c5abfd5bbbae015b899f3edc8892ea32bf82463
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28 19:16:17 +00:00
Lin Huang 25fb09b068 rockchip/rk3399: support dual mipi dsi
Refactor the mipi driver, so we can support dual mipi panel.
And pass the panel data from mainboard.c, that we can
support different panel with different board.

Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28 19:16:09 +00:00
Lin Huang 45f1b01324 rockchip/rk3399: mipi: properly configure PHY timing
These values are specified as constant time periods but the PHY
configuration is in terms of the current lane byte clock so using
constant values guarantees that the timings will be outside the
specification with some display configurations.

Derive the necessary configuration from the byte clock in order to
ensure that the PHY configuration is correct.

Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28 19:15:31 +00:00
Lin Huang 538b9ef66f rockchip/rk3399: improve mipi transfer flow
check GEN_CMD_FULL status before transfer, check
GEN_CMD_EMPTY and GEN_PLD_W_EMPTY status after
transfer.

Change-Id: I936c0d888b10f13141519f95ac7bcae3e15e95d9
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28 19:15:22 +00:00
Lin Huang f4acb92c77 rockchip/rk3399: mipi: correct Feedback divider setting
This patch correct Feedback divider setting:
1. Due to the use of a "by 2 pre-scaler," the range of the
   feedback multiplication Feedback divider is limited to even
   division numbers, and Feedback divider must be greater than
   12, less than 1000.
2. Make the previously configured Feedback divider(LSB)
   factors effective

Change-Id: Ic7c5c59be1d00c65c3b17cb3c4bfba8d7459e960
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28 19:14:39 +00:00
Lin Huang 2e3ebb604a rockchip/rk3399: mipi: correct phy parameter setting
As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0>
should depend on frequency, so fix it.

Change-Id: Ic4a90767bd1f22d5d784d4013dc7afb3149115c1
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28 19:14:32 +00:00
Lin Huang ecd600a0ca rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wide
Accroding to datasheet, feedback divider register high value is only
4 bit, it currently uses 5 bit, so correct it.

Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28 19:14:25 +00:00
Chris Wang 5220e5fba6 mb/google/poppy/variants/nautilus: set I2C speed to 400KHz
Add "speed_config" for each I2C port configuration to set speed to
400KHz.

BRANCH=master
BUG=none
TEST=compiled/verified

Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28 19:11:04 +00:00
Chris Wang 51de1802f3 mb/google/poppy/variants/nautilus: Change IA/GT/SA slow slew rate settings
Change IA/GT/SA slow slew rate settings.
System's audible noise will be reduced with them.

- Slow slew rate for IA/GT/SA : fast/16
- Fast PKG C-state ramp for IA/GT/SA: disabled

BRANCH=master
BUG=none
TEST=compiled/verified

Change-Id: Ibf11aba7bafb3b02c510905d7d904507eee6394b
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-28 19:10:55 +00:00
Vadim Bendebury 3b62d6b40a spi/tpm.c do not waste time on wake pulses unless necessary
The Cr50 secure chip implementation is guaranteed not to fall asleep
for 1 second after any SPI slave activity.

Let's not waste time on the wake up ping when it is not necessary.

BRANCH=cr50
BUG=b:68012381
TEST=using a protocol analyzer verified that the wake pulses are
     generated only when the new coreboot stage or depthcharge start,
     not on every SPI slave transaction.

Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28 18:35:28 +00:00
Martin Kepplinger eb72207fee payloads/seabios: Update stable from 1.10.3 to 1.11.0
SeaBIOS 1.11.0 was released on November 10th, 2017. Changes include

* Initial support for NVME drives
* Support for vga emulation over a serial port in SeaBIOS (sercon)
* Support for serial debugging using MMIO based serial ports
* Support for scsi devices with multiple LUNs
* Support for boot-to-boot persistent coreboot cbmem logs
* Improved coreboot vga (cbvga) mode setting compatibility
* Several bug fixes and code cleanups

See also https://www.seabios.org/Releases#SeaBIOS_1.11.0 and for all
details on the changes, use
  git log --oneline rel-1.10.3..rel-1.11.0
in the SeaBIOS repository.

Change-Id: Ie46a526593177c5241fbd979c7fa1934478f7382
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/22429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-28 18:00:41 +00:00
Subrata Banik d0586d29ea intel/common/block: Add SKL CSME device ID
This patch ensures SKL code is using CSME common
PCI driver.

TEST=Build and boot soraka/eve.

Change-Id: Ic229c60e434d83eb4a3e5392ce90a7d47fddbd73
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 13:10:39 +00:00
Patrick Georgi 0c2df6f027 util/crossgcc: Install a template for the edk2 build system
Add a CBSDK tool set template that can be used in edk2 simply by
appending $prefix/share/edk2config/tools_def.txt to Conf/tools_def.txt.
After that, build -t CBSDK uses the coreboot compilers, providing a more
predictable compiler choice.

Change-Id: I76b38c928b831ee6f31450aa0ad59b4f906f394d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-28 10:48:01 +00:00
Divya Chellap b96712dfd9 mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table
On shutdown, Soraka enters Deep S5 and not S5 state. Setting
pad reset config of a gpio to RSMRST will not preserve
the gpio config across deepSx and the gpio should be configured again.
The WLAN_PE_RST signal should be brought up early in the bootflow
for giving the device enough time to initialized before PCIE init in FSP-S.
Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in
early pad configuration in bootblock also.

BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot.

Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-11-28 05:37:16 +00:00
Martin Roth ec23f048d0 AMD platforms: Fix ASL comment that implies "\_SB" is southbridge
Change-Id: I6ee86396a1c5aaee248a275b42da801cedace586
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-28 03:53:32 +00:00
Chris Wang ad07dc84a4 mb/google/poppy/variants/nautilus: correct the SIO_EC_ENABLE_P2SK typo
correct the typo from SIO_EC_ENABLE_P2SK to SIO_EC_ENABLE_PS2K.

BRANCH=master
BUG=b:66462881
TEST=compiled/boot to ChromeOS.

Change-Id: Iaded458e202bc975c73cd295f7b363e2c9bfa861
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 01:01:30 +00:00
Chris Wang 0e1d022e26 mb/google/poppy/variants/nautilus: remove ALS for nautilus
nautilus doesn't support ALS. remove the definition from ec.h.

BRANCH=master
BUG=b:66462881
TEST=compiled/boot to ChromeOS.

Change-Id: Ib357328799015f78b18cd260db221e524e98cef7
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 01:01:24 +00:00
Martin Roth 17e7a1e0e0 mainboard/google/kahlee: Update Grunt for 16MB ROM chip
- Update Grunt to 16MB chip in Kconfig.
- Move chromeos.fmd into variant directory & update Kconfig with the new
location.
- Add Grunt specific chromeos.fmd file.

BUG=b:69691210
TEST=Build grunt; Build & Boot Kahlee

Change-Id: I8d2f5e3255984d0d9a18df560f84f6db03b73a78
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-28 01:00:08 +00:00
Martin Roth 320b41b148 mainboard/google/kahlee: Update chromeos.fmd
- Remove SI_ALL section.  This is no longer needed as the PSP dirctory
is placed into the RO coreboot section.
- Add 1MB Legacy section.
- Add Memory cache section. These sections are called "MRC", which is
an Intel term, but AMD platforms will use the same regions for saving
the same sort of data.

BUG=b:65497959, b:67035984
TEST=Build & boot kahlee

Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-28 00:59:53 +00:00
Kane Chen 73031bcce0 google/fizz: correct memory rcomp settings
Follow the schematic and Doc 573387 to correct the rcomp and
rcomp target settings for fizz

TEST= boot ok and the system can enter and resume from S3.

Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-27 03:55:42 +00:00
Gaggery Tsai 6919a9376e drivers/net: add SSDT ACPI declaration and WOL feature
This patch adds SSDT ACPI generator and declares _UID, _HID, _DDN and
also _PRW for WOL feature. Besides, adds a wake variable in chip
information.

BUG=b:69290148
BRANCH=None
TEST=Add register "wake" = "GPE0_PCI_EXP" in devicetree under r8168
     chip driver && dump SSDT to make sure _UID, _HID, _DDN and _PRW
     are filled correctly && put system into S3 && sudo etherwake -i
     eth0 $MAC to make sure the system could be woken up by WOL package.

Change-Id: Ibc9115e8a08ba2bfcb3ee1e34c73cf1976a6ba2d
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-27 02:44:02 +00:00
Philipp Deppenwiese 73add175cd util/intelmetool: Add bootguard information dump support
With this implementation it's possible to detect the state
of bootguard in intel based systems. Currently it's WIP and
in a testphase. Handle it with care!

Changes done:
* Add support for reading msr
* Read ME firmware version
* Print bootguard state for ME > 9.1
* Make argument -s legacy
* Add argument -b for bootguard (and ME) dumping
* Add argument -m for ME dumping
* Opt out early if CPU is non Intel

Change-Id: Ifeec8e20fa8efc35d7db4c6a84be1f118dccfc4a
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/16328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-11-25 12:59:54 +00:00
Patrick Rudolph 5e9dc37818 util/intelmetool: Fix lint errors and warnings
Clean the code to fix all errors and warnings.

No functional change.

Changes:
* Fix lines over 80chars
* Fix typos
* Restructure code to reduce indent level
* Move RCBA handling into own files
* Introduce helper functions for RCBA access
* Move GPL string into header
* Fix whitespace in macros

Change-Id: Ib8e3617ebb34c47959d6619dfbc7189045e6b8f7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-11-25 12:55:56 +00:00
Shelley Chen eca98ba460 google/fizz: Remove tpm i2c configs from Kconfig
We are disabling tpm over i2c, so the configs are not needed
anymore.

BUG=b:65056998
BRANCH=None
TEST=emerge fizz and make sure can still boot up.

Change-Id: Id88f32fa952801749544534442fc15d85fc1a892
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25 08:31:55 +00:00
Shelley Chen 5537f02bd5 google/fizz: Disable unused i2c lines
As cr50 has now switched to using SPI, no need to enable the i2c1
anymore.  Additionally, disabled unused I2C devices -- I2C0, I2C2 and
I2C3.

BUG=b:69374421
BRANCH=None
TEST=test on fizz celeron.  Make sure /dev/tpm0 created on (many)
     reboots.  cat /proc/interrupts.  Make sure # interrupts for 16
     after booting is reasonable (not > 10k)  and idma64.0,
     i2c_designware.0 are not listed with that interrupt line anymore.
     Should look something like this:

     16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP

Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25 08:31:40 +00:00
Vaibhav Shankar 6fd5a79d47 soc/intel/cannonlake: Add PM methods to power gate SD card controller
When system enters S0ix, system fails to power gate SD card
controller.

This patch implements PM methods to put the SD card controller
in D3 during S0ix entry.

TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
The System should not be blocked by sd card controller.

Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-23 05:03:14 +00:00
Matt DeVillier d18db73d49 google mainboards: select SYSTEM_TYPE_LAPTOP where appropriate
Some Google boards are missing this selection, leading them to being
incorrectly identified as type 'Desktop' in SMBIOS type 3 table.
Correct this by adding 'select SYSTEM_TYPE_LAPTOP' to the boards'
Kconfigs.

TEST: boot Linux and check correct chassis type listed via dmidecode

Change-Id: Ib1145e314812a3f300cfd1a435a687aa0862158a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23 05:02:35 +00:00
Jonathan Neuschäfer 482d16fb0a src/mainboard: Fix various typos
These typos were found through manual review and grep.

Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23 05:01:47 +00:00
John Zhao bfd62fabc9 soc/intel/cannonlake: Invoke pmc and hard reset only if CSE fails to reset
If CSE fails to do a global reset with the calling sequence of heci
reset/send/receive, then invoke pmc and hard reset.

TEST= Force global reset from early or late romstage. The function
send_heci_reset_message has the calling sequence of heci reset/send/receive.
It is observed timed out error (associated with heci_receive) occurs
only if global reset is forced during early romstage. If global reset is
trigged at late stage (i.e, after fsp_memory_init), then no timed out error
and CSE handles reset properly.

Change-Id: I5bb12554e5745d7704a1b684a3a51034bb35f787
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22549
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23 05:00:55 +00:00
Jonathan Neuschäfer 8f06ce3512 Constify struct cpu_device_id instances
There is currently no case where a struct cpu_device_id instance needs
to be modified. Thus, declare all instances as const.

Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23 05:00:17 +00:00
Arthur Heymans 46234ea36b sb/intel/i82801jx: Store initial timestamp in bootblock
The function to fetch this timestamp is already present.

Change-Id: I760aea8a867339764be9ca627b2ccdff4fd18e30
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23 04:59:50 +00:00
Arthur Heymans f1c8ede1a5 sb/intel/i82801ix: fetch initial timestamp in bootblock
TESTED on Thinkpad x200

Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-23 04:59:26 +00:00
Shelley Chen a35ad0e6ee google/fizz: Define smbios_mainboard_sku to return OEM IDs
Currently, mosys just returns "fizz" as model/chassis values.
Returning proper OEM IDs so that mosys can return the proper
variant.

BUG=b:67732053
BRANCH=None
TEST=mosys platform model; mosys platform chassis;
     Make sure returns the right variant string and not fizz.

Change-Id: I42e293e833b0f7c9870dc275561ad13256836e60
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-23 01:14:09 +00:00
Marc Jones cae58f1306 soc/amd/common: Include appropriate headers in dimm_spd.h
Change-Id: I69e8eaffefbda4fdfb89264a55762558950aa5e2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23 00:34:11 +00:00
Marc Jones 17431abab0 soc/amd/stoneyridge: Get entire DDR4 SPD
Set the SPD size to 512 to get the entire DDR4 SPD.

Change-Id: I0bdf8101de22533b2f4337d3c9e4423d62e6c66d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23 00:34:01 +00:00
Furquan Shaikh 8788fd6395 chromeec: Change the API for hostevent/wake masks to handle 64-bit
ChromeEC is getting ready to bump up the hostevents and wake masks to
64-bits. The current commands to program hostevents/wake masks will
still operate on 32-bits only. A new EC host command will be added to
handle 64-bit hostevents/wake masks. In order to prevent individual
callers in coreboot from worrying about 32-bit/64-bit, the same API
provided by google/chromeec will be updated to accept 64-bit
parameters and return 64-bit values. Internally, host command handlers
will take care of masking these parameters/return values to
appropriate 32-bit/64-bit values.

BUG=b:69329196

Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22 19:10:26 +00:00