This adds support for line-buffered console output to System76 EC firmware.
Once the print command is received, the EC firmware multiplexes the output
to any enabled console on the EC. This can be a memory ringbuffer, a
parallel port (using the keyboard connector), or i2c (using the battery
connector). Once the entire buffer is sent, it sets the command register
to 0, indicating completion. For more information, please see:
https://github.com/system76/ec/blob/master/doc/debugging.md
Tested on system76/lemp9 with CONSOLE_SYSTEM76_EC enabled.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I861bf3e22f40dd6c3ec7ba1d73711b399358e332
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Add a helper function to initiate AP reset through Embedded Controller
(EC).
BUG=b:162290856
TEST=Ensure that the EC resets AP on boards where the command is
supported.
Change-Id: I01d7dfec72a8a3f6d2c4844bc062672e494860d8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44188
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The while loop in \_SB.DPTF._OSC accidentally used <= instead of <, so
there was an error indexing into IDSP.
BUG=b:162043345
TEST=verify disassembled ASL, as well as no BIOS bug mentioned in
/var/log/messages
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I08c4152c59cc9eb13386c825aab983681cfa88ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This adds ACPI code for System76 EC and converts system76/lemp9
to use EC_SYSTEM76_EC.
Tested on system76/lemp9.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Michael Niewöhner
A recent Coverity scan found an issue with the way the
EC_HOST_EVENT_MASK macro was being used. It was being passed values
between 0 and 63, but since it is doing basically (1ULL << (value - 1)),
this caused a shift of -1 when `i` is 0 and also doesn't reach the 63rd
bit of the mask. This is fixed by incrementing the start and end
conditions of the loop by 1, so the event mask ranges from bits 0 to 63,
instead of -1 to 62.
Found-by: Coverity CID 1430218
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6a7cfa64545f3d313de24407f0a91b48368f2a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
GTSH was 2 instead of 20 (so it's 2 degrees K hysteresis), and TSRD was
accidentally defined to take 0 arguments, instead of 1.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I14d28bacf44ac65043060b8579b3fbcec758c56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The DPTF._OSC method incorrectly assumed that all available UUIDs would
be present in the IDSP package, but this is not always the case. Instead
of matching an incoming UUID against an index into IDSP, search the IDSP
package for the matching UUID.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I718b6abe09152647b14f7c1405b2d0d20035726b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
ec_fill_dptf_helpers() is used to generate all of the "helper" methods
that DPTF requires. A system with a Chrome EC is typically in charge
of fan PWM control as well as battery charging, so if DPTF needs to
manipulate those, then it requires Methods provided by the EC.
BUG=b:143539650
TEST=compiles
Change-Id: Ib30072d1d0748b31bcab240a0fd0e2f12d34aaa4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41894
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops codec.asl file from Chrome EC since it is now
unused.
Change-Id: I6c2f3e53b14aaf76b9c6d038a732e79a4d7bb2f1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43043
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds driver for audio codec device (HID `GOOG0013`) living
behind Chrome EC. This driver generates the required ACPI node for the
codec device. In a later change, GOOG0013 device will be dropped
the .asl file.
Change-Id: Ib2759eac60265ef81df70af1d4f1f72bd9d987e8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43041
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves `if EC_GOOGLE_CHROMEEC` from chromeec/Kconfig to
chromeec/i2c_tunnel/Kconfig. This is done to make it clear that the
Kconfig file in i2c_tunnel is sourced unconditionally, but the configs
in i2c_tunnel/Kconfig are conditionally defined based on the
evaluation of if condition.
This change addressed the feedback received on
https://review.coreboot.org/c/coreboot/+/40515/11/src/ec/google/chromeec/Kconfig#200.
Change-Id: I66cd91d6b1813ff6d0fb7be719e2da65ac6ac23b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43040
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For historical reasons, Windows has issues with certain names being
used for files and directories, 'con' or 'CON' being one of
them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in
order to work around this issue.
TEST=built volteer (only user of this driver as of now)
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
If a UCSI event comes in when the EC is in S0ix mode then the kernel
driver attempts a transaction but fails and this can leave the system
in an unexpected state where the only wake source is the power button.
This change will not notify the UCSI driver if the EC is in S0ix mode
and instead keep track of the event and send it on resume.
BUG=b:157923800
TEST=tested on drallion system:
1. Put drallion system into suspend
2. Attach power supply
3. Ensure the system can wake with keypress
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I43acb089385d9b41ac955f053e409daad67423f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change calls \PNOT () method when AC power state is initialized
to allow platform code to take appropriate action.
BUG=b:157752693
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I089e9096f78728ddc5df2d8cb8f22f65b30b02dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The orientation, etc. -switch properties are supposed to use the
connector device (underneath the MUX device) that belongs to the port
number in question. This patch finds the CONx device and uses that
to pass to the acpigen API.
BUG=b:154620502
TEST=on Volteer, dump SSDT and verify the *-switch properties point to
\_SB.PCI0.PNC.MUX.CON0 and CON1
Change-Id: Ie65c2d750f3d9f83285e0e4cc9642110c804bbad
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
According to the Wilco EC spec the BTSC bit of PWSR is always cleared
when PWSR is read so that battery status change events are only
triggered one time. Testing of the Wilco EC has verified this behavior.
This changes the way in which the battery status change bit is used from
checking the bit state against the previous value to always issuing a
battery event when the BTSC bit is set. The other bits in PWSR indicate
state directly and do not behave like the BTSC bit.
BUG=b:157113138
TEST=Deploy on Drallion and verify that battery events are generated
BRANCH=drallion, sarien
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8fbf2ee1158ddd790b04a20b1eb27a6cce4f5c81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>,
<stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes
each time when <types.h> is included.
Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Implementation of the ACPI objects for the Type-C Connector Class was
added in the previous patch. This patch removes the functionality from
the ChromeEC's SSDT generator, and uses acpigen_usb instead.
TEST=Verified contents of SSDT are the same.
Change-Id: Icdbcee1f989ee3146f7495e08fc13f9386791858
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The Linux ChromeOS EC driver now looks for 3 new properties under each
USBC.CONx device contained within the ChromeOS EC device. These
properties are just a reference to the device that controls the
switches for USB 2/3 muxing, SBU lines, and CC lines. It uses the new
function, soc_get_pmc_mux_device() to retrieve the device.
Change-Id: I03cd83f9b2901b5583053fac8ab6eab64717a07d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40618
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After removal of CAR_MIGRATION there are no more reasons
to carry around ENV_STAGE_HAS_BSS_SECTION=n case.
Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit
zero-initializers.
Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is currently used by trembyle. Add it in a common location so other
boards can use it.
BUG=b:147200751
BRANCH=none
TEST=Able to get ec codec on trembyle
Change-Id: Ie21cd813b0e3129f1c61d2de199532b25d3c70fa
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2000271
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41575
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboard specific dock-init mechanism introduced
https://review.coreboot.org/c/coreboot/+/36093 works on most boards,
but https://ticket.coreboot.org/issues/256 shows that some boards
(e.g. x201 and t410) need communication with h8 EC to enable or
disable dock, (in dock_connect() and dock_disconnect() respectively)
so they must be done after the h8 EC is brought up, which is not
garanteed in the above mainboard specific dock-init mechanism.
This time, a hook function h8_mb_init() will be called at the end of
h8_enable(). (in place of the ancient h8_mainboard_init_dock() removed
in CB:36093) Its default implementation is a weak empty function, but
could be overrided with a strong one for boards needing to perform
actions which should be done after h8 EC is brought up.
This should fix the regression detected in
https://ticket.coreboot.org/issues/256
Change-Id: I3674fbfeab2ea2cd2a4453a8e77521157d553388
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.
Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Also split "this is part of" line from copyright notices.
Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
It was always defined to the same value, and only used twice.
Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
.acpi_fill_ssdt() does not need to modify the device structure. This
change makes the struct device * parameter to acpi_fill_ssdt() as
const.
Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
h8_has_bdc() and h8_has_wwan() do not need to modify the device
structure. Hence, this change makes the struct device * parameter to
these functions as const.
This is being done in preparation to make struct device * parameter to
fill_ssdt as const.
Change-Id: Id3d65d2de7b5161b0e7cff26055c00d5dae967dc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40706
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves the code to control the ThinkLight to the common ACPI
folder for h8. This reduces code duplication and allows other ThinkPads
to include the same code for ThinkLight support.
Change-Id: I57de7516051bdcbb23fc21b4de352f265075893b
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change enables support for generating ACPI nodes for I2C tunnel for
any GOOG0012 device that is sitting behind the Chrome EC. It accepts a
config "remote_bus" which allows mainboard to configure the id of the
remote bus that is being tunneled.
BUG=b:154290952
BRANCH=None
TEST=Verified that SSDT node for I2C tunnel behind Chrome EC is
generated correctly.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Icfc0ec3725d7f1d20bcb5cb43a0a23aac72bf4eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds scan_static_bus() as .scan_bus() callback for Chrome EC
device which allows scanning of devices sitting behind the EC using
the topology provided by mainboard's devicetree.cb.
BUG=b:154290952
TEST=Verified with follow-up changes that devices behind EC are scanned
correctly.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id3630db56774fba1e3fc53bf349588c4c585773b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40514
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In ACPI tables, Chrome EC device (CREC - HID GOOG0004) is a child of
EC device (EC0 - HID PNP0C09). However, in coreboot device tree, there
is no separate chip/device for EC0. Thus, acpi_name() needs to return
EC0.CREC as the ACPI name for the Chrome EC device. By returning the
ACPI name as EC0.CREC, all devices that live under Chrome EC device
can simply call acpi_device_path()/acpi_device_scope() to emit the
right path/scope.
In the future, if we ever add a special chip driver for handling EC0
(HID PNP0C09), then the ACPI name for Chrome EC can be fixed to return
CREC.
BUG=b:154290952
TEST=Verified that acpi_device_path()/acpi_device_scope() return the
correct name for Chrome EC device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Iec4b0226d1e98ddeb0f8ed8b89477fc4f453d221
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40513
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Query the EC to get the top row layout, and if it provides one,
generate the SSDT for the PS2 keyboard.
Signed-off-by: Rajat Jain <rajatja@google.com>
Change-Id: I75d2eee32c82b9bee73436b08b5f615d1b388148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40032
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a wrapper command for the subject command
Signed-off-by: Rajat Jain <rajatja@google.com>
Change-Id: I29a4021c2ea0d1cbb4a72f56bf2232d8f9c80ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch adds voltage and curent parameters in
google_chromeec_get_usb_pd_power_info and remove power parameter. Caller could
use the voltage and current information to calculate charger power rating.
The reason for this change is, some applications need the voltage information
to calculate correct system power eg PsysPmax.
BUG=b:151972149
TEST=emerge-puff coreboot; emerge-fizz coreboot
Change-Id: I11efe6f45f2f929fcb2763d192268e677d7426cb
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Type C connector class driver in kernel (v5.4) expects the Type C ACPI
device under ChromeEC ACPI device scope. Currently the Type C ACPI
device is populated under ChromeEC device's parent. This leads to
incorrect casting of Type C's parent device and hence a crash. Move the
Type C device under ChromeEC ACPI device.
BUG=b:153518804
TEST=Build and boot the mainboard. Ensure that the USBC ACPI device is
populated under ChromeEC ACPI device.
Scope (\_SB.PCI0.LPCB.EC0.CREC)
{
Device (USBC)
{
Name (_HID, "GOOG0014") // _HID: Hardware ID
...
}
}
Change-Id: I628489bc420d7a3db4ad3cb93d085d568c6de507
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add command to query the EC for the keyboard layout. Also
add supporting data structures for the exchange.
Signed-off-by: Rajat Jain <rajatja@google.com>
Change-Id: I26aff6dd0e701e0cecb3b66bc54c5a23688f0109
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Obtaining the CBI_TAG_BOARD_VERSION value wasn't in the code base.
Add the binding for it so it can be used.
BUG=b:153640981
Change-Id: Ie2f289631f908014432596448e56b5048a196a10
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Kernel relies on the USB MUX interrupt to configure USB devices that
are connected on the Type-C ports for TGL. Adding in the Q1C Interrupt
so the Kernel can properly receive and configure USB devices
BUG=b:152902608
TEST=buld_packages for volteer and verified that Proto 1 and Proto 2
are now seeing extcon events
Change-Id: Ie3a2f829a295f090a03e72e12f19ecc5bb724952
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Prashant Malani <pmalani@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When EC_GOOGLE_CHROMEEC_SKUID is selected provide an
implementation of smbios_mainboard_manufacturer() so the code
doesn't need to be duplicated in the mainboards.
BUG=b:153767369
Change-Id: Ib65fe373a79d606cffcba71882b0db61be5a18c3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide CROS_SKU_UNKNOWN and CROS_SKU_UNPROVISIONED defintion so
callers can utilize the default and failing value without open coding it.
BUG=b:153642124
Change-Id: I447004e9016b6ab3306ea532721494ebbcda741d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40299
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`.read_resources` and `.set_resources` are the only two device
operations that are considered mandatory. Other function pointers
can be left NULL. Having dedicated no-op implementations for the
two mandatory fields should stop the leaking of no-op pointers to
other fields.
Change-Id: I6469a7568dc24317c95e238749d878e798b0a362
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Providing an explicit no-op function pointer is only necessary for
`.read_resources` and `.set_resources`. All other device-operation
pointers are optional and can be NULL.
Change-Id: I3d139f7be86180558cabec04b8566873062e33be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change replaces all uses of ec_current_image with ec_image since
Chromium OS EC has deprecated (sha 78d1ed61d) the use of enum
ec_current_image and instead changed it to enum ec_image.
BUG=b:149987779
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7e45ea6c736b44040561f0f8a80f817ade8db864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Check that there are actually USB-PD ports for which to
add data to SSDT, before actually generating SSDT data.
This prevents an empty scope from being generated on
devices without any USB-PD ports, which was breaking
parsing/decompilation on some older platforms (eg,
Braswell).
Test: build/boot google/edgar, verify SSDT table able to
be parsed via iasl after dumping.
Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39665
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the NPCE985LA0DX, as used on the 51NB X210
(to be added in a follow-on commit, and from which this was extracted).
Original source: https://review.coreboot.org/c/coreboot/+/32531/37
Change-Id: I5798fad7fd18083cde1aa647fd91ca9c5ce963b7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Matthew Garrett <mjg59@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Store LID status into LIDS and change device name to LID0.
Then Intel driver can reference it.
BUG=b:151134069
TEST=check LID status by evtest
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifdac938730eac034b626aa8ad9d52462f65137ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Move the ECPD (GOOG0003) device under CREC (GOOG0004) so that the ECPD AP
device drivers can access the parent EC device to communicate with the
EC. Also, update the Notify() call to reflect the new location of the
ECPD device.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: I830b030c7a063506f50f9cd51df3a5018e248fc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC")
added a new device_operations structure for chromeec for handling ACPI
SSDT generation. However, this resulted in the original
device_operations which handled lpc read resources to be skipped. This
change fixes the above regression by combining the device operations
for reading resources and ACPI SSDT generation into a single structure
and retains the old logic for enabling of pnp devices.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Leverage the common sku id space helper encoders and
set the sku id max to 0xff for legacy to ensure we
behave the same.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following introduces helpers that, by default,
accommodate a larger SKU id space. The following
is the rational for that:
Allow INT32_MAX SKU id encodings beyond UINT8_MAX.
This allows for the SKU id to accommodate up to 4 bytes
however we reserve the highest bit for SKU_UNKNOWN to be encoded.
However, the legacy UINT8_MAX encoding is supported by leveraging
the Kconfig by overriding it with the legacy max of 0xff.
Follow ups migrate boards to this common framework.
V.2: Fixup array size && drop sku_id SKU_UNKNOWN check and pass
whatever is set to userspace as firmware doesn't care about
the value.
V.3: Use SPDX-License header.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch.
Change-Id: I805b25465a3b4ee3dc0cbda5feb9e9ea2493ff9e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Correct the offset for the Topstar driver enable/disable bit,
which was off by 2 bits compared to a dump of the AMI UEFI ACPI.
This prevents the fan mode (FANM) from being inadvertently changed
and hopefully fixes some intermittent issues with fan speed on
resume from suspend.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Ibc3c39d5b14c753eed6d1ed8cbf161717f8d04e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39105
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Upcoming patches for the Linux kernel (5.6 ?) would like to consume
information about the USB PD ports that are attached to the device. This
information is obtained from the CrOS EC and exposed in the SSDT ACPI
table.
Also, the device enable for this PCI device is moved from ec_lpc.c to
a new file, ec_chip.c, where EC-related ACPI methods can live. It
still allows other code to call functions on device enable (so that
PnP enable for the LPC device still gets called).
BUG=b:146506369
BRANCH=none
TEST=Verify the SSDT contains the expected information
Change-Id: I729caecd64d9320fb02c0404c8315122f010970b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
thinkpad_acpi maps the battery hotkey (KEY_BATTERY) on scancode 0x01 and
the lock hotkey (KEY_COFFEE) on scancode 0x02.
On the Thinkpad X1 Carbon (and possibly others), the hotkeys for Fn-F2
and Fn-F3 are different from the default one so a new layout has to be
defined.
Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add EC ACPI reporting of current temp and platform critical temp.
Adapted from ACPI dump of ODM AMI firmware.
TEST: check reporting of current/critical temps via lm-sensors
from ACPI on Librem 13v1 and 13v4 boards.
Change-Id: I92641fbbdda46e0c388607a37f7a7cc2dcd6c26d
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Serves two purposes:
(1) On some platforms, FSP initialization may cause a reboot.
Push clearing the recovery mode switch until after FSP code runs,
so that a manual recovery request (three-finger salute) will
function correctly under this condition.
(2) The recovery mode switch value is needed at BS_WRITE_TABLES
for adding an event to elog. (Previously this was done by
stashing the value in CBMEM_ID_EC_HOSTEVENT.)
BUG=b:124141368, b:35576380
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I30c02787c620b937e5a50a5ed94ac906e3112dad
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set CPU ID and cores to EC then EC will adapt power table
according to the CPU ID and number of cores.
BUG=b:148126144
BRANCH=None
TEST=check EC can get correct CPU id and cores.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38566
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new functions to get (from the EC):
1) The number of USB-PD ports
2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS)
BUG=b:146506369
BRANCH=none
TEST=Instrumented calls to these and verified the data
Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The new host command provides these static capabilities of each USB-PD port:
1) Port number
2) Power role: source, sink, dual
3) Try-power role: none, sink, source
4) Data role: dfp, ufp, dual
5) Port location: these come from power_manager
BUG=b:146506369
BRANCH=none
TEST=compiles
Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add new mailbox command support. Set CPU ID and cores to EC.
EC will according to different CPU to set different power table.
BUG=b:148126144
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I135d2421d2106934be996a1780786f6bb0bf6b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
The firmware configuration (fw_config) field is store in the CBI EEPROM
and it should be used to make firmware customization instead of
sku/variant id.
BUG=b:145519081
TEST=builds
Change-Id: I790998a29e724ecdff8876cca072267537b7cea6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy ec_commands.h directly from Chromium OS EC repo at sha e57217a250.
This is needed for the FW_CONFIG CBI field definition.
Change-Id: Id010721033ebe32ac9c9482d666cf790442a26ee
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
IMD provides support for small and large allocations. Region IMD Small memory is 1 KB
with 32 Bytes alignment, this region holds smaller entries without having to reserve a
whole 4 KB page. Remaining space is assigned to IMD Large to hold various regions with
4 KB alignment.
The UCSI kernel (kernel version 4.19) driver maps the UCSI_ACPI memory as not cached.
Cache mapping is set on page boundaries and all IMD Small is within the same page.
If another driver maps the memory as write-back before the UCSI driver is loaded then
the UCSI driver will fail to map the memory as not cached.
Placing UCSI_ACPI in IMD Large region will prevent this mapping issue since it will
now be located within its own page. This patch will force UCSI_ACPI region to be
located in IMD Large region.
BUG=b:144826008
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Id00e76dca240279773a95c8054831e05df390664
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All other messages in `ec/lenovo/h8` are prepended with *H8*, so also prepend
the EC version log message with *H8*.
EC Firmware ID 79HT50WW-3.4, Version 7.01A
No CMOS option 'usb_always_on'.
H8: BDC detection not implemented. Assuming BDC installed
H8: WWAN detection not implemented. Assuming WWAN installed
No CMOS option 'fn_ctrl_swap'.
Change-Id: Ib4f341946a336b57bd96c053a05364276caad1ac
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After C_ENVIRONMENT_BOOTBLOCK became mainstream, coreboot build system
starts to produce larger bootblock, conflicting with former default
offsets.
This change makes these offsets configurable before building, with
default values lower than before, to better fit the larger bootblock.
Change-Id: Ie022663a4d0df7f431865b55f7329a9ebb90863b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37778
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Assume that LIMIT_POWER is not requested if the ec does not support it.
Do this by checking the command code in the response message instead
of return value.
BUG=b:146165519
BRANCH=None
TEST=Boot puff with EC which does not support LIMIT_POWER param.
Change-Id: Ib2f5f69a53f204acebfab3e36aab2960eeec1204
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
If the EC doesn't support the EARLY_EC_SYNC we don't properly set power
limits to reasonable defaults and can wedge the AP by browning out at
the end of vboot.
BRANCH=none
BUG=b:146165519
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I4e683e5a1c5b453b3742a12a519cad9069e8b7f7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37930
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not
enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized),
which indicates the TEVT method is empty.
The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses
this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT.
The TEVT method will be removed from the ASL code when the EC does not support TEVT.
BUG=N/A
TEST=Tested on facebook monolith.
Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node]
moved the PS2K ACPI device from under the SIO device to under
the LPCB, and while this fixed the keyboard under Windows for
Skylake devices, it was insufficient for Baytrail and Braswell
devices (and likely Apollo Lake/Gemini Lake too).
Moving the PS2K device under PCI0 allows the PS2K to be functional
under Windows for all Chrome-EC platforms.
Test: build/boot various Chrome-EC devices from IVB, HSW, BDW,
BYT, SKL, BSW, and KBL platforms, verify keyboard functional
under both Linux (4.x and 5.x) and Windows 10.
Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37542
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI methods to the Wilco EC for controlling a privacy screen
on the device.
BUG=b:142237145, b:142656363
TEST=none
Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36044
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves the traditional POSIX stdbool.h definitions out from
stdint.h into their own file. This helps for using these definitions in
commonlib code which may be compiled in different environments. For
coreboot everything should chain-include this stuff via types.h anyway
so nothing should change.
Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Discussed in CB:36093, in the past many lenovo boards need to declare
an empty h8_mainboard_init_dock() to satisfy h8.c.
Now the confusing H8_DOCK_EARLY_INIT might be retired, and if a
mainboard needs dock init (done with h8_mainboard_init_dock() in the
past) in ramstage, (discussed in CB:4294 where H8_DOCK_EARLY_INIT is
introduced) it can just do it in its own chip_ops.enable_dev function.
Tested on X200. Testing on other affected targets may be necessary.
Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate.
Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All of the EC_EVENT_* macros can be replaced with the EC_HOST_EVENT_*
macros defined in ec_commands.h, which is synchronized from Chromium OS
ec repository.
BRANCH=none
BUG=none
TEST=emerge-kukui coreboot
Change-Id: I12c7101866d8365b87a6483a160187cc9526010a
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Quite a few new functions added here in order to support the use-case
of performing EC software sync within coreboot.
Most of these functions are related to retrieving the EC's hash, and
writing a new image into the EC's flash.
BUG=b:112198832
BRANCH=none
TEST=With whole patch series, successfully performed EC software sync
Change-Id: I0d3c5184dbe96f04b92878f2c19c7875503a910a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change all uN integral types to uintN_t. Make the names of host
command params/responses consistent. Use static struct initialization
to ensure all fields are initialized.
BUG=none
BRANCH=none
TEST=compiles
Change-Id: Ibe1e29e88975c85eea215adedc5f5e483243e0d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: If3ee38f3eaa8e6d1c1b0393d0ba289f708e0ae5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36293
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: Iaa35790a38c36091a228007d739b970cb66a3e1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36264
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: Ieb54664a6528ce67634991f64a5f3c411822cdf4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36260
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows to read and set bits in the EC ram in the bootblock or
verstage. This can be useful if one needs to read a keyboard key as an
input for get_recovery_mode_switch in vboot.
Change-Id: I20b2264012b2a364a4157d85bfe5a2303cc5e677
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Don't set a default bus type for the Chrome EC on x86. The platform
must select the bus, typically LPC or ESPI.
BUG=b:140055300
TEST=Build tested only
Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It's been some time and there are 1420 new commits. Including one that
allows reproducible builds \o/ and one that breaks building with empty
$(CC) :-/
Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30679
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fastboot support in vboot_reference is unused, unmaintained, and
produces compile errors when enabled. Since there is no current
or planned use cases for fastboot, remove it.
BUG=b:124141368, chromium:995172
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I06ea816ffb910163ec2c3c456b3c09408c806d0b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35002
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel platforms using eSPI EC communication have just been enabling
the EC_GOOGLE_CHROMEEC_LPC option for simplicity. This does basically
the same, but at least marks it as eSPI in Kconfig for clarity.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35128
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are required to cover the absensce of .data and
.bss sections in some programs, most notably ARCH_X86
in execute-in-place with cache-as-ram.
Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
After ChromiumOS CL:1293132 and CL:1295890, Chrome EC can store the flag
telling if the last reboot was triggered by AP watchdog for some boards
(e.g., Kukui).
This CL adds a new function google_chromeec_get_ap_watchdog_flag(),
which reads the AP watchdog flag from Chrome EC, and updates the tables
of reset causes and reset flags.
A new Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is added for
elog_handle_watchdog_tombstone() to determine if watchdog reset was
triggered by the AP watchdog flag from EC instead of the tombstone in
AP.
BUG=b:109900671,b:118654976
BRANCH=none
TEST=test with https://review.coreboot.org/c/coreboot/+/31843
Change-Id: I7a970666a8c6da32ac1c6af8280e808fe7fc106d
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Copy ec_commands.h directly from ChromiumOS EC repository (CL:1520574).
Since ec_commands.h already defines usb_charge_mode and only
USB_CHARGE_MODE_DISABLED is used in coreboot, enum usb_charge_mode is
removed from ec.h.
To avoid redefinition of the BIT macro, #ifndef check is added to
include/types.h.
BUG=b:109900671,b:118654976
BRANCH=none
TEST=emerge-kukui -j coreboot
Change-Id: I7ed5344fc8923e45e17c3e2a34371db6f80b079d
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31885
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
google_chromec_get_event() depends on the main copy of EC which is
used by ACPI subsytem in the kernel for querying events.
google_chromeec_get_event() also clears the event from EC. Thus if the
kernel has to identify the wake source, it has no way to do that. Thus
instead depend on events_copy_b to log the wake source. Please look at
go/hostevent-refactor for more info.
BUG=b:133262012
BRANCH=None
TEST=Hack hatch bios and make sure hostevent log is correct.
Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c
Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For files built in ramstage and smm -classes, testing
for !__PRE_RAM__ is redundant.
All chip_operations are exluded with use of DEVTREE_EARLY
in static devicetree, so garbage collection will take care
of the !__SMM__ cases.
Change-Id: Id7219848d6f5c41c4a9724a72204fa5ef9458e43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The BBST() method writes an updated status flag mask that is intended
to be stored back in the battery object. This value needs to be
passed as a reference to an object to prevent it from being evaluated
at the time the method is loaded or it will not actually update the
BSTP value in the battery device.
This was tested by instrumenting the _BST method in the primary
battery and ensuring the value can be updated by the BBST method.
Change-Id: Ia8e207a2990059a60d96d8e0f3ed3c16a55c50f4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
We are seeing an EC interrupt after setting the EC RAM offset that
indicates that the EC should transition to S0ix mode and this is
preventing the kernel from going into S0ix on the first try.
As a workaround if we read back from the EC RAM while still in the
_DSM handler it seems to prevent this problem.
BUG=b:130644677
BRANCH=sarien
TEST=ensure s0ix entry works on the first try with sarien
Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for the UCSI specification in order to
provide information about the Type-C port and an interface to
perform power and data role swap.
This change is split across the DSDT and SSDT, with the shared
memory and operation region declared in the SSDT after being
allocated in CBMEM.
The OS will fill in the registers in the system memory region and
then call the _DSM method wtih a read or write argument. The DSM
method will copy the required registers to/from the system memory
and the EC and perform the write or read action.
Responses from the EC will generate a new SCI with event code 0x79
which will notify this UCSI ACPI device and the OS driver will take
action to read status from the EC.
BUG=b:131083691
Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I1eb4163fb36a47b584f1fc9dd3c012e2930e9866
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This command is working as written, but it is not actually correct
as to what the format of the command should be. Fix this and add
define the other radios. There is no change in the command send to
the EC.
Change-Id: Ia551b08561b673d27bec2f900d97b746699b30c4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
On Wilco devices, if any of the coreboot stages fails with a fatal
error, set the diagnostic LEDs with the Wilco EC. The last saved
post code is used to determine the error code sent to the EC.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).
TEST=Forced a fatal error in both bootblock and verstage to confirm
diagnostic LEDs during these stages. This works on cold-boots only. Bug
b:132622888 tracks the mailbox failures on warm boots.
Change-Id: If865ab8203f89e499130f4677fec166b40d80174
Signed-off-by: Keith Short <keithshort@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adds support for the KB_ERR_CODE command on the Wilco EC. This command
is used to drive diagnostic LEDs on the platform after a failed boot.
This change also adds the Wilco EC mailbox command support to bootblock
and verstage so that those stages can use the KB_ERR_CODE command.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: I96d17baf57694e4e01c676d80c606f67054cd0c3
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32776
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add function to wait for sense registers to become valid.
* Add function to retrieve Fn-Key state.
Tested on Lenovo T500:
* It takes about 700msec for the registers to become valid.
Tested on Lenovo T520:
* It takes less than 150msec for the registers to become valid.
Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The EC can return a board ID value similar to the Chrome EC.
In order to use this for the board version returned by SMBIOS
this commit implements the board_id() function for mainboards
that use this EC.
BUG=b:123261132
TEST=Check /sys/class/dmi/id/board_version to see that it
is reflecting the value that the EC provides.
Change-Id: I3fbe0dc886701f37d2424fe7a2867fd860fa1ec0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32276
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This progress code enables keyboard backlight control that
otherwise would only work 30 seconds after boot. This code
is already defined but it was not being sent by coreboot.
It is run in the "post device" step between the other defined
progress codes.
BUG=b:130754032
Change-Id: Ica6c622e568cb236c17bf3edb6639d0177510846
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I added a method to fill out the _BIX package structure but never
hooked it up to the expected _BIX method that the OS uses.
This change adds _BIX method and uses the existing method to fill
it out. It also adds ^ before the _UID in _BIF to match _BIX as
the _UID is one level above the method.
Change-Id: I0de91369b6780fd9432990732c1078a73f6a3419
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When using FSP with debug enabled it takes too long to get to ramstage
and send the first progress code to the EC. The same thing has been
reported to happen when 2x16GB memory is installed.
BUG=b:127875364
TEST=boot with FSP debug and ensure EC does not try to turn off the
system while it is still booting.
Change-Id: I5676354f5e53540273a9029411507f91864735a1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This reverts commit 51169b7dda4a1978d622e329a1c40e384471c165.
I was not ready to enable this option yet, until it is enabled
in depthcharge it needs to stay off in coreboot or depthcharge
will attempt to do software sync without a proper driver.
Change-Id: I4840812d0541f822502cfc5c66bed27edf4d2ecc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32007
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will be used to distinguish the mainboard SKU so that the
correct EC firmware can be bundled with the board.
This is read from EC RAM so it can be used by an ACPI method in
the future.
BUG=b:119490232
Change-Id: I71b8017fc4b88e793dfe709e1cb1ab0f0bcdc4fa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable software sync by default if VBOOT is enabled.
The slow update option is also needed, but this is moving
to depthcharge so it is not defined here.
Change-Id: I046661fae7315f84e96293532b4e1568558df962
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If the command does not respond the driver should not wait for
it to complete before returning.
Tested with SMI debug enabled to ensure that the final command
does not report a failure.
Change-Id: I7c1bfa19a92e8332ac1aa6ff95f94ff4cbdf789d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To ensure the power button functions as expected in firmware ensure
that the EC is not in "S0ix supported OS" mode and expecting the
power button to be handled by the virtual button interface.
BUG=b:128409889
TEST=Verify that the power button works at the developer screen
when the system is rebooted from within Chrome OS. Also ensure
that it works when external warm reset signal is asserted by H1.
Change-Id: Ic323515e3b8be08bac4f0f82e25f2f78c2f22833
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There are two known reverse-engineered ways to manage battery
thresholds.
This patch implements them and adds a way to enable them for
different mainboards.
Tested on W530 with 4.18.3-gentoo kernel and X220 with 4.20.11.
Works fine with new Linux userspace API for controlling battery
thresholds, available since 4.17.
(/sys/class/power_supply/BAT0/charge_(start|stop)_threshold).
The new API is supported by TLP (you might need to set NATACPI_ENABLE=1
in /etc/tlp.conf).
tpacpi-bat works fine too.
Signed-off-by: Alexey Kharlamov <der@2-47.ru>
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The function (preprocessor macro) we need is defined
in <endian.h> not <swab.h>.
Change-Id: I3a86c7050bf853e3a56a15421132240e19f40912
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Various instances of google_chromeec_command() can return non-zero number
(both positive and negative) to indicate error -- fixing cbi_get_uint32()
and cbi_get_string() so they follow the same convention.
BUG=b:123676982
BRANCH=kukui
TEST=build with kukui/flapjack configurations
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c
Reviewed-on: https://review.coreboot.org/c/31585
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch clarifies the definition of google_chromeec_command.
Currently absence of the definition isn't causing any problem because
wrapper APIs check 'ret != 0' or wrapper APIs check 'ret < 0' for an
interface which returns only negative error codes.
However, there is a chance that a new wrapper API will be addedl which
check 'ret < 0' to catch errors, assuming other interfaces behave the same.
Or existing wrapper APIs will be broken as soon as they're compiled for
another interface.
BUG=chromium:935038
TEST=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f
Reviewed-on: https://review.coreboot.org/c/31613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change fixes the power status events for AC and battery
events from the EC. The register that was being used is not
returning the expected information.
BUG=b:125472740
TEST=enable ACPI debug in the kernel and verify that AC and
battery insert/remove are detected properly.
Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On my Thinkpad T420 the default 3000ms SeaBIOS timeout is too short,
it takes nearly 5000ms for my keyboard to become ready.
Timing out before it's ready leads to pretty bad behavior: I cannot use
my keyboard at all to control SeaBIOS, nor the subsequent GRUB instance.
Linux is fine though, possibly because it does its own keyboard init.
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: Id1681bf3921c8b5dc124d4c4e9072f146f84f3a2
Reviewed-on: https://review.coreboot.org/c/31279
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data.
On this platform, interrupts are routed via the GPIO controller so need to be
registered using GpioInt instead of Interrupt.
BUG=b:123750725
BRANCH=grunt
TEST=MKBP events still received (with matching EC and kernel changes)
Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add an ACPI device that is compatible with the Intel Virtual
Button kernel driver for reporting tablet mode state and various
virtual button events that may come from the EC.
This driver is used in Windows and in the Linux kernel at
drivers/platform/x86/intel-vbtn.c
Because of a check in the kernel driver it expects the board to
define the SMBIOS enclosure type as convertible for the check at
driver load time for tablet/laptop and dock/undock to work.
The virtual tablet mode button will proxy the tablet mode state
sent from the Sensor Hub to a SW_TABLET_MODE event in the kernel.
The virtual power button is used during S0ix for the EC to wake
the system with an SCI. There are separate press and release
events which are sent for completeness, although the kernel driver
will ignore the release event.
BUG=b:73137291
TEST=Test that the power button can wake the system from S0ix.
Also verify that the device is reported as laptop mode at boot.
Change-Id: I0d5dc985a3cfb1d01ff164c4e67f17e6b1cdd619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31208
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a separate ACPI device for the Wilco EC event interface so that the
OS drivers can bind to it separately. Since the event handling is all
done with ACPI and not mailbox calls this will be implemented as a
standard acpi_driver in the kernel.
BUG=b:119046283
TEST=veriy device exists in DSDT
Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
1) In the EC _REG method set the flag indicating S0ix support in the OS.
2) Add a function that can be called by the LPI _DSM method to indicate
to the EC that the OS is entering or exiting S0ix.
BUG=b:73137291
Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31094
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modifiy Makefile so that we can get board ID in verstage.
BRANCH=none
BUG=b:117916698
TEST=manually
Change-Id: Idcdb6e07f565c937185cab811abac0ce47e5e3a7
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Send required EC command to enable ACPI S3 wake up from lid switch.
BUG=b:120748824
TEST=Put Sarien system into S3 and then wake up from lid switch
successful.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I13f3469847b0886147b8b624311a1ece796f847b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
A programmable logic device used by Kontron as EC on their COM express
modules. The name `kempld` is taken from Linux kernel sources, as is the
I2C driver. The meaning of the acronym is unclear, probably: Kontron
Embedded Module PLD.
Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Commit 8cf8aa2 [ec/google/chromeec: Use common MEC interface]
changed the return mechanism for the checksum on reads/writes
for MEC devices, but incorrectly handled the passed-in csum
parameter by not dereferencing. This led to the returned csum
value always being zero, which causes all EC commands with non-
NULL data_in to fail with a checksum error.
Fix this by storing the returned checksum in a temp variable,
and only assigning to csum when the pointer isn't NULL;
Test: build/boot google/chell, verify EC hello command succeeds,
keyboard backlight turned on at boot.
Change-Id: I7122c3fdc5a19f87f12975ee448728cf29948436
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Re-write the UAO handling code as it had stopped working (#171)
(the flag was not getting read from the RTC properly in SMM)
Remove the SMM code as it's not needed (but EC flag won't be set
upon entering S3 now)
Set the EC flags on boot the same way other flags are set
Document bitwise operators for clarity
Propagate changes to other Thinkpads
(updated X201 to have 2 bits for the flag as it only had 1)
Per Nicola Corna's previous commits, 0x0d is set for "AC only"
"AC only" does exhibit different behaviour - the USB port is
turned on a few seconds after entering S3, rather than < 1 sec,
regardless of AC status
Tested on X220
Change-Id: If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Send the EC command required to turn the camera power on
and verify that it shows up on the USB bus.
Change-Id: I9e9ba712a11cef85cde91ac21a4b6b5090ef58dc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is a dependency issue with the EC DPTF code accessing
methods that are external, but once the mainboard includes the
relevant code they become internal and the current version of
IASL used by jenkins will fail to compile it.
Until the new IASL is deployed everywhere wrap the EC DPTF code
and expect that the mainboard will explicitly enable it.
Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the support needed for DPTF. This includes the methods to
write trip point values, read temperatures, and handle events.
This was tested on a sarien board by inspecting AML debug output
with the kernel while monitoring temperatures and trip points in
sysfs and controlling temperatures with a fan to ensure that when
a trip point is crossed an SCI is generated and the event is
handled properly.
Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29761
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Disable debug output from read/write methods by default
- Use argument to _REG to disable SCI when EC is unregistered
- Change read/write macros to sync level 2 so they can be called
when a mutex is already held
- Define some missing events
Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29760
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extended events will be handled by the OS kernel driver, but that
driver needs a method exposed by ACPI to read the event data from
the EC and into a buffer.
Tested by generating a hotkey event and reading the buffer from
the Linux kernel driver with acpi_evaluate_object().
Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29674
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EC command to enable WiFi radio and send that command at
startup. Tested to ensure WiFi is functional on a sarien board.
Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29673
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the COM1 ACPI device based on the existing Kconfig option
CONFIG_DRIVERS_UART_8250IO instead of expecting the mainboard to
also define another value for ACPI.
Change-Id: I69361cc2c245cfcad3e4f57567bf56d5a26f0b06
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29672
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.
Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29886
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
OEM name can be stored in CBI. This change can support for fetching
the OEM name from CBI.
BUG=b:118798180
TEST=Verified to get data from CBI
Change-Id: I4938c4d60fcad9e1f43ef69cc4441d1653de7e24
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
In order to support Multi-DPTF profile, Device DPTF Profile Number is
introduced into EC_ACPI_MEM_DEVICE_ORIENTATION ACPI Space at offset
0x09. This bit field stays along with Tablet Mode Device flag.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes(base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: Ie14916ac16c50cbe0990021e2eb03d5121cd0e07
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES
since it aligns with the use-case.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes (base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
EC_SYNC_IRQ from EC to host is level-triggered in practice and
configuring it as edge-triggered on the host results in host missing
events if there are multiple events queued on the EC side. This is
because Linux kernel driver reads one event per irq and the EC does
not de-assert the interrupt line until all events are drained
out. This results in event queue being filled up completely on the EC
and the host failing to see any of those events.
This change configures EC_SYNC_IRQ as level triggered to allow the
host to read events from the the EC as long as the line is asserted.
BUG=b:118949877
Change-Id: Id3fcfa0445f83865d57975a7bbc179dca047ba4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
If remaining charge is more than x% of the full capacity, the
remaining charge is raised to the full capacity before it's
reported to the rest of the system.
Some batteries don't update full capacity timely or don't update it
at all. On such systems, compensation is required to guarantee
the remaining charge will be equal to the full capacity eventually.
On some systems, Rohm charger generates audio noise when the battery
is fully charged and AC is plugged. A workaround is to do charge-
discharge cycles between 93 and 100%. On such systems, compensation
was also applied to mask this cycle from users.
This used to be done in ACPI, thus, all software components except EC
was able to see the compensated charge. This patch is part of the
effort of moving the logic to EC. With this and the EC changes, EC
can see what the rest of the system sees, thus, can control LEDs
synchronously (to the display percentage).
Another rationale of this move is EC can perform more granular and
precise compensation than ACPI since it has more knowledge about the
battery and the charger.
CQ-DEPEND=CL:1312204
BUG=b:109954565,b:80270446,chromium:899120
BRANCH=none
TEST=Verify charge LED changes to white (full) on Sona synchronously
to the display percentage.
TEST=Verify charge LED changes to blinking white (low) on Sona
within 30 seconds synchronously to the display percentage.
Change-Id: I0b51911b90dc2e7fcf5c730c54d9fda1fea76aa9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/29441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add a way for the mainboard to provide a wake pin that the EC
will use to wake the system. This defines a _PRW object.
Change-Id: I94954104bbb8226683c37abc8c0465fe3c62a693
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29408
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The speakers start up muted, and the EC must be told by the BIOS
to unmute it. This helps prevent popping noises on boot/resume.
Change-Id: I693f1d01e46e19362ef8fd0d5b3f4930967b5a12
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI devices for the basic SuperIO functionality provided by the EC
for PS/2 keyboard, PS/2 mouse (trackpad emulation), and legacy UART.
The specific defines to enable these devices should be declared by the
mainboard before including this ASL, the same as the Chrome EC behavior.
Change-Id: I910940ebf26b8758ab12d695e1eba9c668c640c6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add methods to handle ACPI EC events at runtime. Currently only
some common events are handled like lid switch and battery info,
and the event status is printed for debug on other events.
Change-Id: Ic0bd070940c8a2dfa6a251f3464301418bdb69c1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the expected objects (_BST, _BIF, _BIX) for reading battery
information and status from the embedded controller, and the
expected objects for reporting AC power status.
The battery was tested by booting with a battery attached and checking
that it is present in /sys/class/power_supply/BAT0 and that the values
are consistent and within expected ranges.
The AC device was tested by checking the AC status in sysfs when AC
is inserted or removed while the system is running.
Change-Id: Ie996891c383c9e990736690aef9795512ad6d35a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the base ACPI support for the Wilco embedded controller, using
ASL 2.0 syntax throughout.
This includes the EC device and its resources, as well as the layout
for the EC RAM and the functions needed to read and write to the EC RAM.
The EC RAM address space is typically read/write, and so the ACPI EC
device expects that a defined Field can be read and/or written. With
this EC the read and write address spaces are different. For example,
a read from address zero will return data that is unrelated to what a
write to address zero expects.
This makes using a typical OperationRegion to describe the EC RAM
address space somewhat impracticle, since field definitions would
overlap. Instead, methods are provided for reading and writing to an
EC RAM offset, and the EC RAM layout is defined as a Package that
describes offset+mask for read or write fields within the EC RAM.
Change-Id: If8cfdf2633db1ccad4306fe877180ba197ee7414
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function for use in bootblock stage that performs early init
of the EC, in particular setting it up for UART passthrough so a
legacy serial port can be used by the host.
This needs to be called by the mainboard that intends to use it
in bootblock in order for the UART to be available in later stages.
Some of the PNP style programming may look odd, but it is following
the EC specification which is not entirely standard. This code has
been tested on a board with this EC and it is functional.
Change-Id: I9d6935a9fdf0d7290a94bf2ee565ef2a7c00ecc7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29121
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Send a command to the EC on the way into S3 suspend state telling
it to save the PS/2 data, and on resume send it a command for
restoring the PS/2 data that was previously saved.
Change-Id: Ic4b5d6d2656dbb1c476b9211b0d60c71b0cd7b32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29120
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Elyes HAOUAS