The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
On RW boot path psp_verstage call cbfs_map which calls chain of
_cbfs_alloc, cbfs_boot_lookup and cbfs_get_boot_device. Then
cbfs_get_boot_device initializes MCACHE which is used later.
However on RO boot path psp_verstage doesn't try to find anything in the
CBFS which results RO MCACHE not to be initialized. Add
cbfs_get_boot_device(true) to explicitly initialize MCACHE on recovery
boot.
BUG=b:177091575
BRANCH=none
TEST=build and boot jelboz
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54711
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The default of CBFS_MCACHE_SIZE is increased to 0x4000 in CB:54146 but
we have limited space on the PSP thus cannot afford it.
BUG=b:177091575
BRANCH=none
Signed-off-by: Kangheui Won <khwon@chrmoium.org>
Change-Id: I94dd782ae00d0b18ad6dd2fc061e4318bda88579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This will change the names of the GPP bridges, but this ok since there
is no hand written ASL that references these names.
BUG=b:184766519
TEST=Boot picasso and dump ACPI
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54028
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is still causing boot errors on zork:
coreboot-4.13-3659-g269e03d5c42f Fri May 7 22:03:11 UTC 2021 bootblock starting (log level: 8)...
Family_Model: 00820f01
PSP boot mode: Development
Silicon level: Pre-Production
Set power off after power failure.
PMxC0 STATUS: 0x800 BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
FMAP: area COREBOOT found @ 875000 (7909376 bytes)
ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106
BUG=b:177323348
TEST=Boot ezkinil to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I68b4b73670e750207414f0d85ff96f21481be8ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53933
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs.
Hence move it to the common location.
BUG=None.
TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards.
Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Currently, some of the PSP Soft Fuse bits are hardcoded in the Cezanne
and Picasso makefiles.
This makes it impossible for platforms to change them. This change puts
the hardcoded bits in Kconfig, allowing them to be modified by the
platform.
BUG=b:185514903
TEST=Verify that the correct Soft Fuse bits are set.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I190ebf47cb7ae46983733dc6541776bf19a2382f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52422
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up Kconfig and psp_trasfer.h files before copying over to cezanne.
TEST=build, flash and boot on jelboz360
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ib370d93e23c15a2fe4c46051ed3647d2d067bb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52563
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The functionality to restore the previous power state after power was
lost that could previously be enabled by selecting
MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved
by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's
Kconfig instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab9578ebea89651dc2389bf6ca93ca3f3507eb47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since Cezanne needs the exact same code, move it to the common directory
and add a Kconfig option to add this functionality to the build.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add GRXS and GTXS support. Move the gpio method into common place.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The KBRST_L pin will cause a reset when driven or pulled low even when
the GPIO mux is set to GPIO and not native function. So when you want to
use that pin as general purpose output the keyboard reset input
functionality needs to be disabled by selecting this option in the
board's Kconfig file to avoid causing a reset by writing a 0 to the
output level bit when it's configured as an output.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: I517ad551db9321f26afdba15d97ddb61be1f7d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I2C driver is replicated in each generation of AMD SoCs. Introduce a
common I2C driver that can be used across all the AMD SoCs. To begin
with, peripheral reset functionality is moved into this common driver.
SoC specific I2C driver passes the SCL pin configuration in order for
the common driver to reset the peripherals. More functionality can be
moved here in subsequent changes.
Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as
an effort towards using inclusive language.
BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz.
localhost ~ # i2cdetect -y 0
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- --
60:
70:
localhost ~ # i2cdetect -y 1
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:
Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 64d0ad347b. In the
current revision 3.001 of the PPR #56569 the register exists and the bit
definitions match.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7a97843c3dac897f79f229b660b7e30b34eef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
When USE_PSPSECUREOS isn't selected, we get stuck in FSP-S.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60d0e5ab0bd9f4d76cc48d08ca05d27c60e898c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The exact same mechanism is used on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We also want to support uCode loading on cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as
IOAPIC IDs and Picasso had Kconfig options to configure that, but still
used the common SMBus controller code that used CONFIG_MAX_CPUS as ID
for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID
Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a
mismatch between the ID that gets written into the FCH IOAPIC register
and the ID in the corresponding ACPI table. In order to avoid that add
defines to each SOC's southbridge.c and use them in all soc/amd code.
Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since SMM is in TSEG on the platforms which is the default, drop the
SMM_TSEG condition for the default of SMM_TSEG_SIZE.
Change-Id: I7bd965c0794efa12ea4886a55522cc5193a1d3ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50498
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common code gets moved to soc/amd/common/block/cpu/smm, since it is
related to the CPU cores and soc/amd/common/block/smi is about the SMI/
SCI functionality in the FCH part. Also relocation_handler gets renamed
to smm_relocation_handler to keep it clear what it does, since it got
moved to another compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was the only I/O base address in Kconfig, no board changed it and
if a board changed it, it needs to make sure that it won't overlap with
other I/O resources, so just use the same value as constant in the
define instead of the value from Kconfig. Also remove the PICASSO_
prefix from ACPI_IO_BASE.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once.
Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Zork platform was not booting with MCACHE enabled since psp_verstage
had following issues with MCACHE.
Fix all the issues and re-enable MCACHE for Zork.
* psp_verstage should call vboot_run_logic, not verstage_main.
vboot_run_logic calls after_verstage which handles RW MCACHE build.
* It should avoid low-level apis for cbfs access.
cbfs_map will build RO MCACHE if it's the first stage, while other
low-level apis won't.
* It should call update_boot_region before save_buffers
MCACHE should be transferred to x86 so we should build it before
calling save_buffers
BUG=b:177323348
BRANCH=none
TEST=boot Ezkinil
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I08c5f8474600a06e3a08358733a38f70787e944a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cezanne doesn't have eSPIx00034 register define in PPR. Currently only
Picasso need this option.
Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug, so there is no need to specify a MMIO address for the early EHCI
BAR configuration.
Change-Id: I5e904c160c68805a8606a8b2d1ab4fb6172066e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug.
Change-Id: I2dae22c0db294f5334d9796d90f432d6c8d304df
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The SoC code has in implicit dependency on this option, so select it in
the SoC code instead of the mainboard code.
Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This partially reverts commit 6f8f9c969b
by moving CONSOLE_UART_BASE_ADDRESS back to the SoC-specific code, since
the number and base addresses of UARTs turned out to be rather SoC-
specific. The help text for the AMD_SOC_CONSOLE_UART option also
contained those base addresses, so remove that as well.
Change-Id: I01211ec62421c56f22ed611313d6245a05bdea67
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49372
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is causing boot errors on zork:
coreboot-v1.9308_26_0.0.22-18590-g4598a7bed945 Wed Dec 16 17:32:25 UTC 2020 bootblock starting (log level: 8)...
Family_Model: 00820f01
PSP boot mode: Development
Silicon level: Pre-Production
PMxC0 STATUS: 0x800 BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
FMAP: area FW_MAIN_B found @ 312000 (3137280 bytes)
ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106
BUG=b:177323348
TEST=Boot ezkinil to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f2bbdd9c87c4efdfb0042e90a20b489fa0efced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.
Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was used as a guard to not raise SMI with
APM_CNT_GNVS_UPDATE. The handler has been removed
now completely.
Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The actual UART initialization code will be factored out in follow-up
commits.
Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This allows factoring out the common initialization for the integrated
UARTs.
Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due the location of X86_RESET_VECTOR, the anchor point
for linking the bootblock is at the end, which equals
ROMSTAGE_ADDR.
Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The architectural requirement is for the address to be
located at the end of bootblock -0x10 bytes, so the
definition was redundant with other Kconfig variables.
Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the
code.
Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The functionality in smi_util applies for all 3 AMD SoCs in tree. This
patch additionally drops the HAVE_SMI_HANDLER guards in the common
block's Makefile.inc, since all 3 SoCs unconditionally select
HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any
functionality that is only present when that option is selected.
Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.
Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Now that the initial version of the Picasso FSP binaries have finally
landed, we can set the default paths to point to them now.
Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42472
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in
the corresponding SoC code, so remove it from the SoC's Kconfig and
reanme it in the mainboard's Kconfig to MANDOLIN_LPC.
Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding functionality in the SoC's Makefile.inc was removed in
commit ef3395d990
Change-Id: Iba84d9deb155ce314b3a3588781752b83a21486b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
AMD family 17h and newer don't use cache as RAM, since the RAM is
already initialized by the PSP when the x86 cores are released from
reset. Therefore they use a different linker script as the rest of the
x86 chips in coreboot do. Since there will be support for newer
generations than Picasso will be added, move those linker scripts from
soc/amd/picasso to soc/amd/common/block/cpu/noncar.
TEST=Timeless build of amd/mandolin and amd/gardenia result in identical
binaries.
Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
SOC_AMD_COMMON needs to be selected to be able to select
SOC_AMD_COMMON_BLOCK which only includes the Kconfig files from the
function block sub-folder. Removing SOC_AMD_COMMON_BLOCK and the
corresponding Kconfig file and make SOC_AMD_COMMON include all Kconfig
files from the sub-folders simplifies this a bit.
Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
