Tested on OCP Delta Lake, the timer action can be set correctly.
Change-Id: I1013169e12455e01214d089c9398c78143af4df8
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44019
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is expected both of TCSS D3Hot and D3Cold are enabled by default.
BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on TGLRVP.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Id569d8191f82f12379b57a9c50aec31776220bb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
It is expected TCSS D3Hot is enabled. D3Cold configuration is
through SoC stepping determination. D3Cold is disabled on pre-QS
platform and enabled on QS platform.
BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update configuration for both of TCSS D3Hot and D3Cold. It is expected
D3Hot is enabled for all platforms. Because there are known limitations
for D3Cold enabling on pre-QS platform, this change reads cpu id and
disables D3Cold for pre-QS platform. For QS platform, D3Cold is
configured to be enabled.
BUG=None
TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0)
and enabled for QS (cpu:0x806c1).
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43980
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently HDA gets enabled by the option EnableAzalia, but
this duplicates the devicetree on/off options. Therefore use
the on/off options for the enablement of the HDA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableAzalia setting.
Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently HECI3 gets enabled by the option Heci3Enabled, but
this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the HECI3 controller.
I checked all corresponding mainboards if the devicetree configuration
matches the Heci3Enabled setting.
Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently eMMC gets enabled by the option ScsEmmcEnabled, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the eMMC controller.
I checked all corresponding mainboards if the devicetree configuration
matches the ScsEmmcEnabled setting.
Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Currently TraceHub gets enabled by the option EnableTraceHub, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the TraceHub controller.
I checked all corresponding mainboards if the devicetree
configuration matches the EnableTraceHub setting.
Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.
I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.
Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.
Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This change updates TGLRVP configuration to have USB Type-C connector
device properties filled into ACPI SSDT.
TEST=Built and booted to kernel on tglrvp boards. Verified the USBC
scope under LPCB.EC0.CREC with required connector device properties.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The HSIO tuning guide recommendation for the default USB3 settings is to
have de-emphasis set to -3.5dB with the equation 20*log(X/64). 0x29 results
in a value close to -3.5dB and it is the value that was used for the default
on past platforms so I used it here as well.
BUG=b:160721468
TEST=Ensure WWAN device does not disconnect during use.
Change-Id: Ia594996cb55523dacce0d4bef98cc217321c62de
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
BUG=None
TEST=Build the magalor board.
Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch uses the fill_processor_name function in order
to fetch the CPU Name.
TEST = Successfully able to build boot Waddledoo and verify the
cpu_name from CPU log "CPU: Genuine Intel(R) CPU 0000 @ 1.10GHz".
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I532e05d9bb71fdff24e086e81ec72ffe8dc2c22d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43480
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Strip manufacturer information from SPDs before injecting into APCB.
This allows more flexibility around changing DRAM modules in the future.
BUG=b:162098961
TEST=Boot, dump memory info
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is already defined in <commonlib/helpers.h> and it gets included
implicitly by some other header. Fixes building with code coverage.
Change-Id: Id2dc6cc34b6f1d351d8e1b52d8cc4ada8666c673
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add interrupts for all enabled superio devices to quiet the warning
about missing interrupts in devicetree.
Vendor uses interrupt 0x00 for all devices except SUART* and KBC, so
let's do that, too. This also changes SWC from 0x0b to 0x00.
Verified with superiotool on X11SSM-F.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7a6dc7345f020e53415a7d0d104ce93ab4b194fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonas Löffelholz
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
They're more or less the same but reworked for hopefully some more
clarity. There have been some best practices around documenting the
reason for expedited processing so let's make them official, too.
Change-Id: I620e48016a1ceda2ac43f26624ed21af01f6a0a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value in romstage. By default it would start the timer
and trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.
Add RO_VPD and RW_VPD sections.
Tested on OCP Tioga Pass.
Change-Id: I53b69c3c5d22c022130fd812ef26097898d913d0
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When emitting a fan's _FPS (Fan Performance States) table, the revision
field was missing. According to ACPI spec 6.3, the current revision is
zero, so add that Package entry before the others.
BUG=b:149722146
TEST=verified first element of \_SB.DPTF.TFN1._FPS is 0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If16d4751f1d924807f5087d93b348e58d5265197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43978
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new utility for converting a pad configuration from
the inteltool dump to the PAD_CFG_*() macros [1] for coreboot and GPIO
config data structures for FSP/sdk2-platforms/slimbootloader [2,3].
Mirror: https://github.com/maxpoliak/pch-pads-parser.git
[1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
[2] https://slimbootloader.github.io/tools/index.html#gpio-tool
[3] 3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h
Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35643
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the Kconfig flag VBOOT_VBNV_CMOS_BACKUP_TO_FLASH for psp_verstage
to save the vbnv data to the SPI rom.
BUG=b:161366241
TEST=Boot Morphius, Read rom from SPI and extract the RW_NVRAM region.
See that it's getting updated.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0d4b92fa321a8409468b8d8fc40be0d4b57b664b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43487
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SPI needs to be initialized to save VBNV (Vboot Non-Volatile memory)
to flash.
BUG=b:159811539
TEST=Build & boot.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iebf3ed3f5d6be0dda717d91d5b2fbcf2a1cc43cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Two usb Type-C ports under the actual mux device. Each port has its own
ACPI device entry. These nodes are the ones that the USB Type-C
port/connector device will refer to in order to configure the mux.
TEST=Built image-tglrvp-up4.bin successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I8423ddbb5bc189899a9e19e7da6e2ee7b7fecc18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The commit hash is the same as the SeaBIOS one, and is indeed from the
SeaBIOS repository.
Change-Id: I820b9b748778050fc694c13b1e2b2fc80885b4f1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43749
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, if PSPBTLDR_FILE is empty, the md5sum will hang forever on
stdin, leading to the appearance of a hung script. This is
confusing.
There's no option to md5sum to say "you must use this file", so instead,
use dd with if to ensure we at least get an error if the file is not found.
Not optimal, but better than what we have now.
Change-Id: Ia13035bc592bdf2a515dfd2e052ae9135e218612
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fill in the new fields introduced with version 3.0 and install the new
entry point structure identified by _SM3_.
Tested on Linux 5.6 using tianocore as payload:
Still able to decode the tables without errors.
Change-Id: Iba7a54e9de0b315f8072e6fd2880582355132a81
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rearrange code to unify with the rest of xx20/xx30 boards. No functional
changes - just smaller diff output.
Change-Id: I5867b2a90b2e53a3a9dd919701f1e185cb39cf78
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Replace functionally identical files with t440p/acpi/superio.asl which
is licensed under more flexible terms (GPL-2.0-only or no licensing
terms vs. GPL-2.0-or-later). Apart from licensing terms these files are
identical.
This makes diff between boards smaller.
Change-Id: I1cd4a85b65ceaa0a383416e7276ad41a41783cb7
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43685
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
BUG=b:161215903
BRANCH=NONE
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib61af2399541c4caf4a310a34e778e0ba1cbd3ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43802
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow schematic to modify USB port setting and clean up I2C clock tuning.
USB2 [0]: USB Type C Port 0
USB2 [1]: USB Type C Port 1
USB2 [2]: None
USB2 [3]: USB Type A Port 1
USB2 [4]: None
USB2 [5]: Camera
USB2 [6]: None
USB2 [7]: WLAN module - BlueTooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: USB Type C Port 1 (Sub/B side)
USB3 [2]: None
USB3 [3]: USB Type A Port 1
USB3 [4]: None
USB3 [5]: None
BUG=b:161407664
BRANCH=NONE
TEST=Build the coreboot image on madoo board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia73593f52adee3806e725127891f084a08bf1360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43750
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.
BUG=b:153588771
TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If59502aec7c3ab55864a518d626cde52aee18373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43746
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a missing newline to a printk in the max98373 driver.
BUG=none
TEST=verified BIOS boot log is properly formatted on volteer.
Change-Id: I1c989729bdc71736975901566023e0057a6d0556
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This adds the PCI ID of the realtek 5261 PCIe to SD Express card
reader.
BUG=b:161774205
TEST=none
Change-Id: I4d5e6cfca59b02adc74a0c148281a92421fe209d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Johnny Lin