Commit graph

59 commits

Author SHA1 Message Date
Marc Jones
f9ea7edea8 update all FADT version 3.0 to use the get tables function
Most FADT report using ACPIv3 FADT table. Using the get revision
function keeps the table versions in sync.

Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27 15:49:32 +00:00
Arthur Heymans
6cfa4f763d soc/intel/broadwell/Kconfig: Clean up redefined config options
All broadwell board set HAVE_IFD_BIN to default n, overloading the option in
soc, therefore just use the defaults in sb/intel/common/firmware.

Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28011
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13 15:45:14 +00:00
li feng
3130a93bfa skylake: Remove "IshEnable"
Remove "IshEnable" from soc_intel_skylake_config since it's not
used anymore.

Enable/disable ISH by checking if ISH device is turned on or not.

Refer to https://review.coreboot.org/#/c/coreboot/+/26485/.

BUG=b:79244403
BRANCH=none
TEST=Built.

Change-Id: I4d2889af118659852431c87cb516fd19b577efc5
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11 10:48:12 +00:00
Elyes HAOUAS
b0f1988f89 src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:32:34 +00:00
Subrata Banik
c4986eb7f4 soc/intel/common/block: Add common chip config block
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.

For now, adding i2c, gspi and lockdown configuration which will be used
by common code.

BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.

Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06 06:23:45 +00:00
Subrata Banik
ce23d4c6f1 soc/intel/skylake: Add option to skip coreboot MP init
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.

Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init

Default coreboot does MP initialization.

Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05 15:51:27 +00:00
Youness Alaoui
d319b98279 purism/librem_bdw: Rename Broadwell baseboard from BDL to BDW
My bad, it seems the acronym for Broadwell is BDW, and not BDL, so
I'm renaming librem_bdl into librem_bdw and changing the KConfig
options accordingly.

Change-Id: I8e992aa3474863236adf8893fcbe37c1b801fa25
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26237
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11 18:23:48 +00:00
Youness Alaoui
0cf89bf20a purism/librem_bdl: Add support for Librem 15 v2
Adding new librem_bdl variant for the Librem 15 v2, which is very similar
to Librem 13 v1, with the following differences:
- SATA ports 0 and 1 instead of 0 and 3
- SATA DTLE IOBP value is 7 instead of 9 for port 0
- There is no LAN device
- There are two SODIMM slots, and DQs are interleaved
- USB ports are different

Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:09:20 +00:00
Youness Alaoui
b799e0df3d purism/librem_bdl: Convert to variant setup
Convert the purism/librem13v1 to a variant setup, in
preparation for adding the librem15v2 board as a new variant.
The Librem 13 v1 and Librem 15 v2 are nearly identical, so
this minimizes new code to add support for the latter.

Also update the URL in board_info to an archive.org link.

Change-Id: I00bb82b9e895e2464ddaa92915c01ce0e35933a2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:08:18 +00:00
Youness Alaoui
42ff2c05d9 purism/librem13v1: Fix space->tabs and disable ME pci device
Change-Id: I7ffcea7bff988d3d4269e1334fc938932aed2eb4
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-08 03:00:15 +00:00
Youness Alaoui
ab0fdcd73d purism/librem13v1: Disable PCI Express AER capability
The Librem 13v1 does not seem to have working AER and this option
was needed and tested on the Librem 13v1. Without it, the linux
console gets spammed with AER errrors.

Change-Id: I13d0afa085b426920d7a946e6209f924ce29ae52
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08 02:59:44 +00:00
Youness Alaoui
3f42a26b42 purism/librem_skl: Add AC/DC LoadLine to VR Config
The FSP 2.0 needs to set the ac_loadline and dc_loadline for
each VR config. Without it, the Loadline is considered to be
0 mOhm and this causes CPU temp to jump all over the place
whenever the CPU is used.

This is necessary since there are no VR_CONFIG icc mappings for
Skylake SKUs, only KabyLake.

These values were copied from the Google Poppy devicetree.

Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06 06:43:00 +00:00
Youness Alaoui
cb8f04dc83 purism/librem_skl: Set TCC Activation at 95C
Set the Thermal Control Circuit (TCC) activaction value to 95C
even though FSP integration guide says to set it to 100C for SKL-U
(offset at 0), because when the TCC activates at 100C, the CPU
will have already shut itself down from overheating protection.

This was tested on Purism Librem 13 v2. A bisect showed that the
immediate shutdowns happened after commit [1] was merged which led
to this solution.

[1] ec5a947b (soc/intel/skylake: make tcc_offset take effect)

Change-Id: Idfc001c8e46ed3b07b24150c961c4b9bc9b71a62
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06 06:42:15 +00:00
Youness Alaoui
0601f1e164 purism/librem_skl: Enable VMX and Intel SpeedStep in devicetree
Although VmxEnable is currently ignored by FSP, a forthcoming patch
explicitly enables it in coreboot, so set it in anticipation of that.

Enable Intel SpeedStep to ensure the ACPI tables are generated for
the C-states/P-states which are required for the xen-acpi-processor
module to be loaded. Without it, the Qubes 4.0-rc4 installer will
complain at boot about modules that could not be loaded.

Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06 06:41:38 +00:00
Youness Alaoui
59d89a8e59 purism/librem_skl: Enable TPM support
Change the GPIO to match the TPM-enabled motherboards, and add TPM
support in devicetree and enable the config.
After changing the GPIO table, the librem 13v2 and librem 15v3 now
have the same GPIOs, so use a single gpio.h file instead of one
file per variant.

Change-Id: I425654c1c972118aa81c27961246238c2eef782d
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/23683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06 06:41:20 +00:00
Duncan Laurie
f5116952bb soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it.  Otherwise, disable the
PCI device if it has been enabled in devicetree.

To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.

This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.

Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28 22:52:38 +00:00
Youness Alaoui
be78775a93 ec/purism: Fix CPU Turbo value (PPCM) set by the EC
The EC needs to set the PPCM value depending on whether
Turbo is enabled or not, and the values differ between
Broadwell (0, 1) and Skylake (1, 2) platforms.

Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-26 10:25:58 +00:00
Youness Alaoui
6aa28d93b3 purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O port
The LPC I/O ports for EC communication were not set properly,
causing ectool to fail to read the Index I/O from the EC.

The EC Index I/O is on port 0x380 and the LPC I/O port needs to be
decoded by the PCI device for it to be accessible.

Correct the value for the Librem 13v1, 13v2 and 15v3.

Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-26 10:25:41 +00:00
Youness Alaoui
9c1bb6d8dd purism/librem_skl: Improve boot time by enabling SPD Word Read
This speeds up the SPD read ('calling FspMemoryInit' phase) from
218ms to 134ms consistently.

Tested on both the Librem 13 v2 and Librem 15 v3.

Change-Id: I44fbe96c256972bd074537159771d61fe7adf082
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-22 19:36:27 +00:00
Martin Roth
888c9f6097 mainboard/purism/librem_skl: Fix line length > 80 characters
Make lint-stable was giving an error on this.

Change-Id: I06d11d86151f683b82b6df537e3de8c52d33e8b4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-12-11 18:54:58 +00:00
Matt DeVillier
a547e40992 purism/librem_skl: add new variant Librem 15 v3
Add new board librem15v3 as a variant of the librem_skl baseboard.

Changes from the librem13v2:
- Change board name and version
- Change GPIO A18, A19, A20, D9, D10 and D11 from NC to GPIO
- Enable PCI device 1c.4
- Change USB port definitions in devicetree

TEST: build w/SeaBIOS, boot PureOS on Librem 15 v3 hardware

Change-Id: I7c762a34f5b961c908e4a29ec331da4b0dea9986
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22048
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-26 06:40:33 +00:00
Matt DeVillier
435299461f purism/librem13v2: convert to variant setup
Convert the Purism Librem13v2 board to a variant setup,
in preparation of adding the librem15v3 as a new variant.
The 13v2 and 15v3 are nearly identical, so this minimizes new
code to add support for the latter.

Change-Id: I5d648cdb8f63c03de5474253203b3d0853673294
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22047
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-26 04:06:03 +00:00
Matt DeVillier
fb1cd09596 purism/librem13v2: migrate from FSP 1.1 to 2.0
Migrate the Librem13v2 from using FSP 1.1 to
the public/GitHub FSP 2.0 Skylake/Kabylake release:

- select FSP 2.0 in Kconfig
- adjust romstage/ramstage functions as required
- refactor pei_data functions
- remove VR_RING domain from devicetree (unsupported in FSP 2.0)
- add SataSpeedLimit parameter to work around power-related issue
  when operating at SATA 6.0Gbps speed

TEST: build/boot Librem13v2, observe successful boot, lack of
SATA-related errors in dmesg.

Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-23 16:56:37 +00:00
Youness Alaoui
c25c998888 purism/librem13v2: Update microcode length in CBFS
Microcode blob has been updated, so update the length to match

Change-Id: I46ac10e5c6cd6492c98a7034649797f301101abc
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22 01:58:16 +00:00
Youness Alaoui
a8b35be75e purism/librem13v2: Fix USB settings and set OC pin
The USB settings were wrong in some places, or missing and the
USB_OC values were taken from the schematics.

Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22 01:58:11 +00:00
Youness Alaoui
c5b9658961 purism/librem13v2: Update devicetree settings
Disable SataDevSlp and update other values to match vendor/AMI firmware.

Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22 01:58:06 +00:00
Youness Alaoui
3d60718f82 purism/librem13v2: Change DRAM Rcomp/DQS values
The RComp values have been updated to match what is shown in the schematics.

Extracting the Memory configuration blob from the original BIOS (A blob
which contains the correct binary sequence matching the RComp values appears
in object with GUID 2D27C618-7DCD-41F5-BB10-21166BE7E143), I could find
and confirm the DQ and DQS mapping.

Small code cleaning in romstage.c with no effect.

Change-Id: I35c734269b365fd759e9bd56224a80a8a8df5a57
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-22 01:58:01 +00:00
Youness Alaoui
c0a32cad28 purism/librem13v2: Add reading of serial number from CBFS
Check CBFS for 'serial_number' field, and use value if exists;
otherwise use value set at compile time.

Change-Id: I4b50f6310ca32b9dd372db075a5b5729e3b06619
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22040
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22 01:57:56 +00:00
Furquan Shaikh
219ebb969b skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")

This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.

BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.

Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-09 20:20:40 +00:00
Hannah Williams
1760cd3eb4 soc/intel/skylake: Use common/block/gpio
Other than switch to use common gpio implementation for skylake based
platform, also apply the needed changes for purism board.

Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 22:32:33 +00:00
Jonathan Neuschäfer
cbe8c58e07 mb/purism/librem13v2: Remove redundant MAINBOARD_VENDOR setting
Unlike Chromebooks, Purism laptops are only sold under one vendor name,
so MAINBOARD_VENDOR only needs to be set in src/mainboard/purism/Kconfig.

Change-Id: If0b33df01ff3327272d089b7efb8e64fa1233fdf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21591
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-22 04:54:34 +00:00
Subrata Banik
c204aaa23b soc/intel/skylake: Add LPC and SPI lock down config option
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.

Remove EISS bit programming as well.

TEST=Build and boot Eve and Poppy.

Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25 17:58:08 +00:00
Martin Roth
467a87abce Fix files with multiple newlines at the end.
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24 15:08:08 +00:00
Nico Huber
5f9c6734fc lib/spd_bin: Use proper I2C addresses
Use the plain address instead of the weird shifted encoding (e.g. if
we'd use `0xa0` as address, it's actually `0x50` encoded into a write
command).

Change-Id: I6febb2e04e1c6de4294dfa37bde16b147a80b7a8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-29 15:41:02 +00:00
Matt DeVillier
1e1bbb17a0 purism/librem13v2: Fix HDA verb values, use azalia macros
Use verb table values from AMI firmware, consolidate NID
definitions using azalia macros. Fixes headphone jack detection
and microphone.

Change-Id: Ia31be6efc7afe921ad91b400f66694d951f0a260
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-16 16:19:13 +02:00
Youness Alaoui
eacac20bd5 purism/librem13v2: Add audio support
Initialize the audio codec without depending on DSP binary blobs.
The hda_verb.c was copied from the intel/kblrvp rvp7 variant, and the
hda_verb.h file was copied from the purism/librem13.

The IoBufferOwnership FSP option in devicetree has to be 0 for the azalia
driver to work.

Change-Id: Ifa36ac0839daedfa59c497057da0ace04d401f2a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16 16:19:04 +02:00
Youness Alaoui
d8cbd5633f purism/librem13: Disable L1 sub states support
Some NVMe devices (Intel 600p series for example) seem to lock up
in D3 drive power state (L1.2 PCIe power state).
Disabling L1 substates fixes it.

Change-Id: I00a327dc91d443beb565fe4e72aaf816e40a007c
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-16 16:16:49 +02:00
Matt DeVillier
739ded5c18 purism/librem13v2: Fix EC_SCI_GPI value
Existing value was copied from librem13 v1 board, use value
obtained from AMI firmware.

TEST: Observe Windows boots correctly, function keys work
under both Windows and Linux.

Change-Id: I0ea6cc4602ce1047cb803acc65cbca1af1f480b0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-16 16:09:09 +02:00
Youness Alaoui
f739e7f56a purism/librem13v2: Add Kconfig defaults
Add default values for MAINBOARD_VERSION and CBFS_SIZE.

Change-Id: Ib6461cef78f3fea448baf1ada456e3c8335f1543
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-06-16 16:06:04 +02:00
Matt DeVillier
2ae2742065 purism/librem13v2: Clean up devicetree
- remove unused I2C, serialIO defs
- set PL2 override, VR mailbox cmd based on SKL-U ref board,
  as values copied from google/chell are for SKL-Y

Change-Id: I3a138c28d0322df6cb41ec1a845ae31602cb69a7
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16 16:04:31 +02:00
Matt DeVillier
2fa66164d8 purism/librem13v2: Update USB config
Update devicetree USB config based on board spec.
Leave OC pins set to skip since the info is unavailable.

Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16 16:04:22 +02:00
Youness Alaoui
debb785d59 purism/librem13v2: Update PCI config
Update devicetree PCI config based on board spec:
- enable PCIe Root Ports 5 and 9 (wifi and nvme respectively)
- enable PCIe CLKREQ on RP9, disable on RP5
- enable USB OTG
- enable P2SB

Note: PCIe RP5 is on 0.1c.0 despite this being labeled as RP1

Change-Id: Ia71ed25bd41668df1ee3e4b4e28f54482722452c
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09 17:03:27 +02:00
Matt DeVillier
0ff3b73990 purism/librem13v2: Don't disable PM timer
Needed for UEFI booting via Tianocore;
with PM timer disabled, payload hangs.

Change-Id: I6c65cb9d3e6a10baea4cc1e2d9e94c36fe419561
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09 17:03:19 +02:00
Youness Alaoui
9d8cd507a6 purism/librem13v2: Enable SATA, disable eMMC support
Change-Id: Ib63e5e8a1bcbc25c288dec7d1ef6c06239ada34b
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09 17:02:42 +02:00
Youness Alaoui
6b8570d864 purism/librem13v2: Add microcode values in Kconfig
The FSP Temp RAM init will fail if the mircocode values are set
to 0. A valid microcode update needs to be included and its size
and offset need to be set in the config.

Change-Id: I26d05bd7b37c8d91bf34f399c7c4189f9d3dd34a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19936
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09 17:02:31 +02:00
Youness Alaoui
0e977fca9c purism/librem13v2: Add memory init code
Adding code to setup the spd information from sodimm.
Adapted from intel/kblrvp.

Change-Id: I0403f999dac1bdef0e9e1abe7c9c62407e223bb1
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09 17:02:21 +02:00
Youness Alaoui
34a30a648f purism/librem13v2: Add GPIO pad configuration
The GPIO configuration matches the one from the original BIOS.
Some configs don't make much sense, but I kept it as is so it
would match (such as a NC pin with TX set to 1, or RXINV enabled).

Remove unnecessary early GPIO config.

Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19934
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09 17:02:14 +02:00
Matt DeVillier
2766ebf585 purism/librem13v2: Select SERIRQ_CONTINUOUS_MODE
Like other devices using ENE embedded controllers, the librem13v2
requires this config option for the PS2 keyboard and mouse
(trackpad) to function properly.

Change-Id: Ifba13b93a1fe2e76b2790d1c273fd9e2b5368ab0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09 17:02:06 +02:00
Youness Alaoui
047475cbd7 purism/librem13v2: Add initial directory for librem13 v2
Add the initial directory for the port of the Librem 13 v2.
The base implementation was copied from the google/chell directory
and the chell references were replaced. spd directory was removed
since the RAM is not soldered on the MB. The Kconfig, board_info.txt
and devicetree.cb files were modified to match the Librem 13 v2
hardware information. The romstage.c, mainboard.c, Makefile.in and
dsdt.asl were modified to remove chromeos specific code. The boardid.c,
chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c
files were removed from the tree, and the acpi directory was replaced
with the acpi directory from the purism/librem13 board.

These changes allow us to remove the references to chromeos specific
code and allow coreboot to compile when the librem13v2 board is selected.

Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09 17:01:58 +02:00
Matt DeVillier
ab5b4c19c3 purism/librem13v1: Set FADT revision to ACPI 3.0
The FADT revision was set to 5, but we do not implement the
ACPI v5.0 specification, which prevents Windows from booting.
Setting it to v3 (matching most other boards) fixes the issue
and Windows now boots normally.

Bug found by Matt DeVillier, fix tested by Youness Alaoui on
Librem 13 v1 hardware.

Please also see commits 00d250e228 (intel/skylake: Switch FADT
to ACPI version 3.0) [1] and 27e6042bb7 (intel/apollolake:
Switch FADT to ACPI version 3.0) [2].

[1] https://review.coreboot.org/19453
[2] https://review.coreboot.org/19146

Change-Id: Ide97cbf64f7b05018433436431ab4723b217fe22
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09 17:01:41 +02:00