Commit Graph

38859 Commits

Author SHA1 Message Date
Zheng Bao 9ca96f35f7 soc/amd/picasso: Fix the typo in GPIO define
Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16 17:17:57 +00:00
Arthur Heymans 8346307603 soc/intel/xeon_sp: Move DMICTL lock
On SKX FSP-M does not return if this is set too early.

Tested on OCP/Tiogapass, boots.

Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 14:58:44 +00:00
Arthur Heymans c7b63edeb4 mb/ocp/tiogapass/devicetree.cb: Add P2SB device
This fixes ocp/tiagopass not booting as after FSP-S the P2SB is
accessed to read out or reconfigure the HPET and PCH IOAPIC BDF.

Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48654
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 14:58:21 +00:00
Kyösti Mälkki 413539536d soc/amd/common/gpio_banks: Drop underscore in __gpio
The local function names were chosen such that they don't
collide with <gpio.h> so the prefix is unnecessary.

Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16 13:44:53 +00:00
Huayang Duan 5d6192aefe soc/mediatek/mt8192: Do the dramc pinmux selection
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16 08:03:59 +00:00
Kyösti Mälkki 97b76f7191 arch/x86: Link gdt_init.S into bootblock
Followup work forces gdtptr and gdt towards the top of
bootblock. They need to be realmode-addressable, i.e.
within top 64 KiB or same segment with .reset.

Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-16 06:31:55 +00:00
Angel Pons 54b5e20cf8 soc/intel/broadwell: Drop unnecessary `sa_dev`
Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46982
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:31:22 +00:00
Kyösti Mälkki dc873cc0c6 arch/x86: Clean up bootblock assembly
We have identical gdtptr16 and gdtptr. The reference in
gdtptr_offset calculation is not accounted for when
considering --gc-sections, so to support linking
gdt_init.S separately add dummy use of gdtptr symbol.

Realmode execution already accessed gdt that was located
outside [_start16bit,_estart16bit] region. Remove latter
symbol as the former was not really a start of region,
but entry point symbol.

With the romcc bootblock solution, entry32.inc may have
been linked into romstage before, but the !ENV_BOOTBLOCK
case seems obsolete now.

Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-16 06:31:03 +00:00
Ren Kuo 5283c337bf mb/google/dedede/var/magolor: Add Wifi SAR for magolor and maglia
Add wifi sar for magolor and maglia:
Using tablet mode of fw config to decide to load custom wifi sar or not.
same wifi sar value for magolor and maglia (shared firmware)

BUG=b:173001370, b:173001251
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Cq-Depend: chrome-internal:3453724

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I44ab68c9ee5deced90d3858161571ab4b39b4c8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48448
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:30:33 +00:00
Seunghwan Kim 447db3a8a9 mb/google/dedede/var/sasuke: Add memory part and generate DRAM ID
This change adds memory part used by variant sasuke to
mem_part_used.txt and generates DRAM ID allocated to the part.

BUG=b:172104731

Change-Id: Ie8d66261cb5b4493afb1c677839f807bca994af5
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48451
Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:30:18 +00:00
Hsin-Hsiung Wang 04de09986b soc/mediatek/mt8192: Correct return value of VM18 voltage
The voltage of vm18 should be microvolt instead of millivolt.

BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Iea5b46c1df358dc350506d29cc033d01631b37b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16 06:29:40 +00:00
Weiyi Lu dac4fa6ded soc/mediatek/mt8192: Keep CONN MCU in reset state
Keep the CONN MCU in reset state to prevent CONN from asserting the
clk26m request to SPM.

TEST=clk26m request from conn has been released.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16 06:29:24 +00:00
Ricardo Ribalda 752fc6026f mb/google/poppy: Fix race condition in acpi camera_pmic
Newer kernels can re-schedule new acpi command calls during a Sleep().

This causes that the following trace fails to detect the cameras:
[   15.764725] drivers/acpi/power.c:358 Power resource [OVFI] turned on start
[   15.772180] drivers/acpi/power.c:358 Power resource [OVTH] turned on start
[   15.834970] drivers/acpi/power.c:362 Power resource [OVFI] turned on start
[   15.852456] drivers/acpi/power.c:415 Power resource [OVFI] turned off start
[   15.955987] drivers/acpi/power.c:420 Power resource [OVFI] turned off end
ERROR!!
[   16.030896] drivers/acpi/power.c:362 Power resource [OVTH] turned on end

Which can be triggered more frequently if the Sleep() commands in OVTH
 _ON Method are increased.

To avoid the race condition, we create a new Power Resource that
handles the common resources of both cameras and make both cameras
depend on that resource. This also simplifies the acpi table by removing
a Mutex.

BRANCH=poppy
BUG=b:171955583
TEST=while true; do if ssh $DUT "dmesg | grep \"failed to find sensor\" "; then  break;  fi; ssh $DUT reboot; sleep 30 ; done
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>

Change-Id: I25df0225699759c1828b8791c5bdee66529858a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48631
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:29:20 +00:00
Eric Lai 1a8c20324a mb/google/zork/: Remove WRDD from Vilboz
After checked, this project doesn't need this feature.

BUG=b:173066178
BRANCH=zork
TEST=check no WRDD method in acpi.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9a662953f3047d771f2df919ac80d0440842738e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48621
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:28:59 +00:00
Matt DeVillier 087c4f2894 mb/purism/librem_cnl: Use FMAP-based SPD cache
Use a FMAP region to cache SPD data, providing improvements in boot
time and detection of change in DIMM population (which FSP will
sometimes fail to detect / fail to invalidate the MRC cache).

Adapted from implementation used in google/hatch.

Test: build/boot Librem Mini v2, verify SPD cache used, changes
in DIMM population properly detected.

Change-Id: I15cb9aa8b00d39d098a0f901aee026bac1161a80
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48549
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:28:51 +00:00
Huayang Duan c1ce6f80c4 soc/mediatek/mt8192: Do dramc init settings
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16 06:28:34 +00:00
Kyösti Mälkki 1ad7bc4c60 soc/amd/common: Use only byte access for IOMUX
Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42978
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:28:21 +00:00
Seunghwan Kim 133f8e329b mb/google/octopus/variants/casta: Add support zinitix touchpad
This change adds support zinitix touchpad for casta/bluebird.

BRANCH=firmware-octopus-11297.B
BUG=b:175618033
TEST=built and verified touchpad worked on casta

Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48634
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16 06:28:11 +00:00
mtk15698 70ba37c54f soc/mediatek/mt8192: Enable DCM
Enable DCM settings.

Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1
Signed-off-by: mtk15698 <michael.kao@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16 06:28:01 +00:00
Wenbin Mei 1985894e74 soc/mediatek/mt8192: ufs: Disable reference clock
UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16 06:27:12 +00:00
Weiyi Lu 92d59931c4 soc/mediatek/mt8192: Initialize audio pll tuner frequency
Add AUDPLL TUNER init code.

TEST=Boots correctly on MT8192EVB.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16 06:26:51 +00:00
Felix Held e501f9b3dd soc/amd/picasso/smi: add missing bits to GEVENT_MASK
GEVENT_MASK should cover all GEVENT pins, but was missing
SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8.

Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-12-15 20:14:54 +00:00
Kyösti Mälkki 8c1e603800 soc/amd/common,picasso: Place some ENV_X86 guards
Base address symbols for ACPIMMIO banks that would not get
assigned at runtime must not resolve at linker-stage either.

The build of PSP-verstage should pass without the preprocessor
macros that have x86-centric view of memory space.

Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-15 19:34:10 +00:00
Kyösti Mälkki 79d0ea4b7e soc/amd/common: Move lpc_util to verstage_x86
The file seems to be all about PCI configuration access.

Change-Id: I1e64d3d7df3caa33ee92961fe7246d03f2707ab4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43328
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15 19:32:31 +00:00
Kyösti Mälkki 5f2f44a4cf soc/amd/common: Redo ACPIMMIO_BASE and _BANK
Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42894
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15 18:52:28 +00:00
Kyösti Mälkki d786520de1 soc/amd/common: Refactor SMBus base arguments
Replace SMBus base addresses with proper symbols.

Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42074
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15 18:50:13 +00:00
Arthur Heymans c2503dbe88 soc/intel/xeon_sp: Fix final MTRR usage
The region top_of_ram -> cbmem_top is used by FSP and cbmem, but is
also just regular DRAM. Marking it as such improves the final MTRR
solution a lot and fixes MTRR starvation depending on the setup.

Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47868
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15 17:49:39 +00:00
Matt DeVillier 6452a9fcfc mb/purism/librem_mini: Adjust PL1/2 levels
While the Librem Mini (v1/v2) are more than capable of higher
PL1/2, they currently ship with a 40W power supply, so set PL1/2
accordingly to avoid power spikes above the PSU rating (which can
result in unexpected showdowns/reboots)

Change-Id: Ia7f89e885f1af29cbbb67d6fb844257ba2b87417
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-15 01:57:38 +00:00
Huijuan Xie bde9708200 mb/google/asurada: Initialize display
Enable ANX7625 panel and configure display in mainboard_init() to
support display in firmware screen.

BUG=b:155713214
BRANCH=none
TEST=Recovery screen is shown in recovery mode.

Signed-off-by: Huijuan Xie <huijuan.xie@mediatek.corp-partner.google.com>
Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-15 01:53:26 +00:00
Hung-Te Lin 4b3269e21d mb/google/kukui: help payload to identify correct speaker amp type
Kukui based devices may use different speaker amplifiers, for example
MAX98357A, RT1015, or RT1015Q/automode. To help payloads identifying
which component was installed on board, we want to pass the speaker GPIO
in different name. This can be set in Kconfig as CONFIG_SPEAKER_GPIO_NAME.

BUG=b:174534548
TEST=emerge-kukui coreboot depthcharge chromeos-bootimage
BRANCH=kukui

Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I4b44b026bee4d3b58646eee207aea0120071dd46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-15 01:51:09 +00:00
Huayang Duan 7265bab69e soc/mediatek/mt8192: Define DRAM registers and APIs
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ifc64fb6c60d57184c4a2f9febe765b5cb69b39ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44699
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15 01:44:14 +00:00
Shreesh Chhabbi 860c68449d src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL
Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config
option. Select CAR_HAS_SF_MASKS for Tigerlake.

During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x
are not being reset to default as
per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5.
Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient.

Bug=b:171601324
BRANCH=volteer
Test=Build and boot to ChromeOS on Delbin.

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-14 23:05:57 +00:00
Shreesh Chhabbi 87c7ec7c06 soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config option
SF Mask MSRs' Programming which was done under this config
selection will be moved under a new config option called
CAR_HAS_SF_MASKS. This segregates the eNEM programming
sequence based on sub features supported in each processor.

Bug=b:171601324
BRANCH=volteer
Test=Build volteer build and boot on Delbin EVT.

Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14 23:05:25 +00:00
Angel Pons 5f73432737 sb/intel/common/smbus_ops.c: Clean up read resources
Using `pci_dev_read_resources` works just as well on bd82x6x (the
allocator does the same) and allows dropping the i82801gx check.

Change-Id: I1cb05131a82ebb7c45827eff8e09e445d9c695b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48538
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 21:03:28 +00:00
Angel Pons 3ee6d7bf22 configs: Add a weird config for Asus P8Z77-V LX2
This is not meant for actual use, but to build-test several options.
Please do not try to use it on real hardware. Or maybe do try.

The purpose of this config is to build-test the individual options, not
their combination. So, for instance, if it would be hard to keep options
x, y and z build together in the future, this config shouldn't block a
change but should instead be adapted, e.g. split into multiple chunks.

Change-Id: I80e8fe3982025b61148e7c2b05dd0727d65ee2f4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-14 21:01:17 +00:00
Bora Guvendik befa58145d mb/intel/tglrvp: Enable CNVi Bluetooth for UP4
Turn on CNVi Bluetooth for UP4 in devicetree.

BUG=none
TEST=Boot to OS, check BT enumeration.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I6a3ec7014c41713697e0fcc90e28bc7bbe6aa1e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-12-14 20:15:01 +00:00
Patrick Rudolph 4ce5b63294 mb/prodrive/hermes: Update PCIe slots in devicetree
* Drop PcieRpSlotImplemented on internal slots
* Add PCIe port 15 that connected to CNVi/M.2 E

Change-Id: Iaa05affa760b447fc1725e674b12366684a63720
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14 20:10:59 +00:00
Sridhar Siricilla d9d711c7f5 soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.

BUG=b:174694480
Test=Verified on Tigerlake platform

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48281
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 18:42:25 +00:00
Sridhar Siricilla 551bd92b2b soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage
This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync()
must be called after DRAM initialization.

BUG=b:174694480
Test=Verified on Drawlet

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 18:42:19 +00:00
Sridhar Siricilla 1a2b702848 soc/intel/common: Move CSE Lite driver functionality into romstage
The patch sets up the CSE Lite driver in the romstage instead of ramstage.
With this change, CSE Lite driver sets CSE's boot partition and triggers
CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM
initialization as HMRFPO_ENABLE HECI command (which is used by
cse_fw_sync()) is expected to be executed after DRAM initialization. With
this change, it improves the cold boot time by ~154ms.

Test=Verified on JSL and TGL platforms
BUG=b:174694480

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 18:42:12 +00:00
Sridhar Siricilla 4c2890d47e soc/inte/common: Replace #if macro with if C-language constuct
This patch modifies CSE Lite driver to use 'if' C-lanugage construct
instead of #if macro and adds 'if SOC_INTEL_CSE_RW_UPDATE' to the prompts
of CSE Update related KConfigs to prevent appearing them in the menu.

TEST=Built the code for drawcia

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14 16:12:52 +00:00
Sridhar Siricilla abeb688154 soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BP
The patch triggeres CrOS recovery mode if the sizes of CSE CBFS RW blob
and CSE RW boot are different.

TEST=Verified on drawcia.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48423
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 16:12:43 +00:00
Angel Pons 20c8aa71d1 soc/intel/braswell: Use Kconfig value for TSEG size
SoC selects HAVE_SMI_HANDLER, so TsegSize is always set to 8 MiB. Also,
use SMM_TSEG_SIZE in place of a magic number.

Change-Id: I139e1073426051fea5d30b6ce3dd9746e0e985a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14 11:06:33 +00:00
Angel Pons 233ae1919b soc/intel/braswell: Clean up devicetree settings
Remove unreferenced settings and factor out common settings. Many of
these are not mainboard-specific, and all boards use the same value.

Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14 11:05:51 +00:00
Angel Pons 68cf57cf33 soc/intel/skylake: Drop always-zero ProbelessTrace dt setting
This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.

Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14 10:40:51 +00:00
Angel Pons 950cdbc3e2 soc/intel/skylake: Drop always-zero PowerLimit4 dt setting
Unset devicetree settings default to zero, so the devicetree setting can
be removed. Looks like no one needs it anyway.

Change-Id: Iad94538c5465347b37a99c6c9f20988168661593
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14 10:40:44 +00:00
Angel Pons 124e9f293b soc/intel/skylake: Drop never-set DdrFreqLimit dt setting
Only Google Eve uses a non-zero value, but it overwrites in C code.
Drop the devicetree setting, since no mainboard uses it.

Change-Id: I14e0e0cb9baa2b1f8f795e6bc6ffbee300f2243d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14 10:40:21 +00:00
Arthur Heymans 86d195b192 soc/intel/xeon_sp/skx: Hook up microcode blob
TESTED on ocp/tiagopass: Microcode updates are properly applied (via
FIT). Tested with out of tree patches to report the revision.

Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-14 10:38:34 +00:00
Angel Pons 63a078e66d soc/intel/skylake: Drop unreferenced PttSwitch dt setting
The value for this setting is not used anywhere. Drop it.

Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14 10:25:02 +00:00
Angel Pons 056c3a9ff2 soc/intel/skylake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48571
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14 10:24:54 +00:00