With the current timeout of 1000 cycles of 100 microsecond would see
timeout occurs on OCP Delta Lake if the log level is set to values
smaller than 8. Because the prink(BIOS_SPEW, ..) in ipmi_kcs_status()
creates delay and avoid the problem, but after setting the log level
to 4 we see some timeout occurs.
The unit is millisecond and the default value is set to 5000 according
to IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or greater
is recommended.
Tested=On OCP Delta Lake, with log level 4 cannot observe timeout
occurs.
Change-Id: I42ede1d9200bb5d0dbb455d2ff66e2816f10e86b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45103
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new memory.c to support DDR4 memory types.
Use the new meminit_ddr() and variant_memory_sku() for eldrid variant
code on memory.c
The initial settings override the baseboard from volteer and fine tune
gpio.c and overridetree.cb on eldrid's configuration.
BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that Eldrid
can boots. NOTE that tests the ddr4 side of the implementation.
Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Allows the AM335X to boot from the coreboot generated MLO by:
- Fixing the load address in the MLO header to be the start of SRAM
- Fixing the way that the bootblock size is calculated (which is
embedded into the MLO so that the MLO knows how much to load into
SRAM). The previous method relied on parsing cbfstool output - the
output has changed format since this was originally written so this no
longer works. Directly using the filesize of the built binary is
probably a more stable way of doing this.
As part of this, the start addresses of SRAM and DRAM were fixed to be
consistent with the AM335x Technical Reference Manual (spruh73, rev Q).
TEST: Booted Beaglebone Black from MLO placed at offset 0x00 on an SD card
Change-Id: I514d7cda65ddcbf27e78286dc6857c9e81ce6f9e
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44381
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The console is initialized before mainboard_init, so the peripheral
should be initialized in bootblock_mainboard_early_init rather than
bootblock_mainboard_init.
Change-Id: I9f4ba29798eb0b1efea76f5ade4a234fb35a2f83
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select
CPU_INTEL_COMMON directly, to avoid dependency problems.
Tested with BUILD_TIMELESS=1: Without including the config file in the
coreboot.rom, both OCP Tioga Pass and Delta Lake remain identical.
Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45041
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This ports Linux commit 71f677a91046599ece96ebab21df956ce909c456
"Handle configuration without P2A bridge".
Quote:
The ast driver configures a window to enable access into BMC
memory space in order to read some configuration registers.
If this window is disabled, which it can be from the BMC side,
the ast driver can't function.
Closing this window is a necessity for security if a machine's
host side and BMC side are controlled by different parties;
i.e. a cloud provider offering machines "bare metal".
P2A stands for primary to AHB.
Tested on Prodrive Hermes, which uses an AST2500. The machine still
boots, has a high resolution framebuffer working in EDK2, and its
boot time has been reduced by 2.5 seconds as it no longer runs into
a timeout due to disabled P2A bridge.
Change-Id: I3293dc35ae89c010154e02eff904ec3a68c96683
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Fixes complains about missing INT configuration by the pciexp kernel
modules.
Tested with Linux 5.5 on Prodrive Hermes.
Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The three Intel Apollo Lake boards (apl_rvp, leafhill and minnow3) do
not define MAX_CPUS, which would then default to 1. Since this is most
likely an oversight, use the same value as other Apollo Lake boards.
To ensure this does not happen again, factor out MAX_CPUS to SoC scope.
Change-Id: I5ed98a6b592c8010b59eca7ff773ae1ccc4cd7b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
APL does not support Hyper-Threading, and has at most four CPU cores.
Change-Id: Ib2ffadc0c31cdd96bec8eed5364c984acb2e1250
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45143
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both Gemini Lake boards in the tree use the same value.
Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Update critical and passive policy for TSR0.
BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sushi is not a real product, just a test of the new_variant program.
The effort to keep it up-to-date with the rest of Hatch is no longer
worth it. Remove the variant.
BUG=b:168030592
TEST=build bot is successful, hatch-cq builds successfully
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I2b0036f3cbdea4bfaed1274ab87a20d24c75de57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CB:44774 introduced the non-existent SPD path. This is preventing the
device from booting up.
BUG=b:168053219
TEST=Build and boot drawcia board to OS.
Change-Id: I70ca5f4cf2c8e2e88ea5b1514b656caafb732743
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SMBus code is linked unconditionally since commit 0e3c59e. This change
drops that obsolete part from the help text.
Change-Id: I603ab012760684021be1b5eca5d0ddff69463b79
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Most of them are needed for SMBIOS type 17 creation.
Tested=With FSP WW36 verified the printed hob values match
with FSP hob data.
Change-Id: I02f4600f1be39e2576d7c84a5a6b6672ebb7034b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support SPI flash dual read funciton which change spi mode (1-1-1)
to dual mode (1-1-2).
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Iabd3668fc4bc42137b7743144fc1cced4fe72737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44852
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To minimize the quirks the kernel has to apply, the headset mic is set
to its correct value in coreboot.
Tested on lemp9, audio is functional.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I6b59de95f01360a5f7779f87f39edeb75dedc215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43631
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PSTACK2 (IOU3) should be stack number 4, mainboard uses stack number as
the index to access the bus number array read by get_stack_busnos().
Without the fix it would get the wrong bus number (0xb1).
Tested=On OCP Delta Lake, dmidecode -t 9 to verify slots bus number on
IOU3 are correct (0xb2).
Change-Id: I1c9e49bbc9a00de82d1fc67b3b4ed47e03eacdda
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:162232776
TEST=Measured the I2C bus frequency as 389 KHz, high time as 870 ns and
low time as 1580 ns.
Change-Id: I67d2725a7fc8d83e3fa8a56cfa86540c4e6f0971
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45084
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:163743035
TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and
low time as 1680 ns.
Change-Id: I60a5f6814fb9818c724f6b6fe465ea49d0de0f97
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45083
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP v3333 or later, provides a new UPD to Skip configuring
GPIO settings from FSP. coreboot should provide all the
required GPIO configuration for the platform when this UPD
is set.
BUG=b:166790597, b:146390704
BRANCH=none
TEST=build and boot volteer proto2
Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44913
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update FSP headers for Tiger Lake platform generated based FSP
version 3333. Previous version was 3313.
Changes Include:
1. Update comments
2. Add new UPD for Gpio Override support
BUG=b:166790597
BRANCH=none
TEST=build and boot volteer proto2
Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie3f0688143eef532946c7a2141909c1ac173fc2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44912
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clone entirely from Jasperlake
List of changes on top off initial jasperlake clone
1. Rename from jasperlake to elkhartlake
2. Remove irelevant devices asls (ipu,ish,camera clock,gpio_op)
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44812
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clone entirely from Jasperlake
List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jsp" with "mcc"
4. Rename structure based on Jasperlake with Elkhartlake
5. Clean up upd override in fsp_params.c will be added later
6. Sort #include files alphabetically as per comment
7. Remove doc details from espi.c until it is ready
8. Remove pch_isclk & camera clocks related codes
9. Add new #define NMI_STS_CNT & NMI_EN as per comment
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Unlike other platforms, Apollo and Gemini Lake have VmxEnable on FSP-S.
Note that this will enable VMX by default on both of these platforms.
Change-Id: I6a4470e0e64b10f07edfcf270bb02c7cd6a8fa1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select
CPU_INTEL_COMMON directly, to avoid dependency problems.
Tested with BUILD_TIMELESS=1, UP Squared does not change.
Gemini Lake already selects this through SOC_INTEL_COMMON_BLOCK_SGX.
Change-Id: If737fa6d8700f435c8692c80244f0e71657c2236
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The PRM does not describe the relevant bits, but Linux's i915 driver
handles these bits the same way for both Ironlake and Sandy Bridge.
Change-Id: Ice7412e335752bd7e297ad50f685effcefbd41d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
All boards currently have backlight on either LVDS or eDP.
Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Configure eldrid to use CSE Lite.
BUG=b:158140797
TEST=cd to volteer's asset_generation folder, execute
"./gen_all_variant_images.sh" and verify that all variant
images are produced.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I357abdac4102f358d3aa1cb50f600312039ef140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
The SMRR MSRs can be locked, so that a further write to them will cause
a #GP. This patch adds that functionality, but since the MSR is a
core-level register, it must only be done once per core; if the SoC has
hyperthreading enabled, then attempting to write the SMRR Lock bit on
the primary thread will cause a #GP when the secondary (sibling) thread
attempts to also write to this MSR.
BUG=b:164489598
TEST=Boot into OS, verify using `iotools rdmsr` that all threads have
the Lock bit set.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4ae7c7f703bdf090144637d071eb810617d9e309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The IA32_MTRR_CAP register has a bit which indicates that the SMRR MSRs
can be "locked" and this patch adds the definition for that.
BUG=b:164489598
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
ashk