Commit Graph

25233 Commits

Author SHA1 Message Date
Patrick Rudolph 6308e0e92f mb/hp: Add new port compaq_8200_elite_sff
Add new port based on autoport.

The board uses a NPCD378 SuperIO, that is full of custom hardware.

The 8MiB flash SOIC-8 can be accessed after cutting of a part of the
DIMM slot holder. The flash IC has no diode, powering a part of the
board while flashing externaly, including the Standby-LED.

The following have been tested and is working:
* Native raminit with up to four DIMMs
* Libgfxinit on DisplayPort
* USB
* EHCI debug
* Serial on RS232
* Ethernet
* PCIe on x4
* PCIe on x16
* SATA
* Booting GNU Linux 4.14 using SeaBIOS 1.11.1 as payload
* Flashing internaly
* PS/2 is working

Untested:
* PCI slot
* LPT port
* VBIOS
* S3 resume

Not working:
* PSU fan managment (runs at 100%)
* Half of SuperIO functionality is unknown

TODO:
* Reverse engineer remaining SuperIO registers
* Reverse engineer SMM

Fixes on follow-up commits:
* Added PSU fan control
* Reverse engineered some of Super IO's HWM registers
* Added SMBIOS tables for IPMI

Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25385
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24 15:05:19 +00:00
Kyösti Mälkki 21fa51475d AMD geode/lx: Remove generic_sdram.c include
The file under lib/ will be removed with K8 and
Geode LX is the only other platform using it.

Change-Id: Id49d72358ecfc4aae4980e3ae787952073e5c838
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24 13:33:57 +00:00
Kyösti Mälkki bb748c5f92 AMD: Remove some leftover includes
Change-Id: I740d945693b4f16495488fb76ad6d1ee531185ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24 13:23:52 +00:00
Angel Pons 963500fe0b mb/gigabyte/ga-h61m-s2pv: Add new mainboard
Tested with GRUB 2.02 as a payload, booting Arch Linux with
latest kernel. This code is based on the output of autoport
as well as existing ga-b75m-d3h and ga-b75m-d3v mainboards.

Working:
 - Serial port I/O
 - S3 suspend/resume (broken with SeaBIOS 1.11.1)
 - USB ports and headers
 - Gigabit Ethernet
 - Integrated graphics (libgfxinit)
 - PCIe x16 graphics
 - PCIe x1
 - SATA controller
 - Hardware Monitor
 - Fan Control (fancontrol on linux works well)
 - Native raminit (4+4GB, 4+2GB, 2+2GB, DDR3-1333)
 - Native graphics init with libgfxinit
 - flashrom, using the internal programmer. Tested with coreboot,
   as well as with the vendor firmware. Backup chip is untested.
 - NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
   tested with values different from the default.

Untested:
 - VGA BIOS for integrated graphics init
 - DVI port. It can detect a "fake" display, that is, an
   EEPROM connected to the DVI port.
 - PS/2 ports
 - Audio: Only rear output (green) has been tested.
 - EHCI debug.
 - Parallel port
 - Non-Linux OSes
 - ACPI thermal zone and fan control (probably not working)

Not working:
 - SATA devices with Tianocore (payload issue)
 - PCIe to PCI bridge. It seems to be poorly supported on Linux,
   it lacks a public datasheet and vendor BIOS behaves in the
   same way: The bridge and the devices behind it appear, but
   drivers fail to find devices attached to the bridge.

Change-Id: I598a0b75093a0f1aef2ac615035d66786a8c22cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-24 13:22:57 +00:00
Kyösti Mälkki f7741d7964 Remove leftover AMD CIMX RD890 northbridge support
Change-Id: I3f2cea79a11a52e94f479b25f22eb3726af38fa3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24 13:22:34 +00:00
Kyösti Mälkki d644a2788f Remove leftover AMD CIMX RD890 vendorcode
Change-Id: Ic7d80b25c0815f3816ae40646d024e0d9fe61f08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24 13:21:32 +00:00
Kyösti Mälkki 87027645e0 Remove leftover VIA vt82c686
Change-Id: Id215fb22c3cf1890fd001e2f7a9a7bd0105c1747
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24 13:21:10 +00:00
Kyösti Mälkki 1607406b7c Remove leftover Intel i82801b support
Change-Id: If85d73745ec858155c501aa637fd27a62a41dd68
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24 13:20:56 +00:00
Kyösti Mälkki 2202a12d05 Remove leftover Intel i82801a support
Change-Id: Ibcecd34d552cd1a4d945c74996d47223a39dc5c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24 13:20:44 +00:00
Kyösti Mälkki 5b3bf4ad27 nb/amd/amdfam10: Get rid of device_t
Change-Id: Iac6be374842063cc383af20c73900e3699a72653
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24 13:20:00 +00:00
Kyösti Mälkki 57d71c8278 sb/amb/rs780: Get rid of device_t
By mistake this was forgotten from previous commit touching
the same directory.

Change-Id: I23e3e579ccbcb8a251cdde11215ec171b78b7159
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26494
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24 13:18:53 +00:00
Kyösti Mälkki 219bacccb5 mb/packardbell/ms2290: Get rid of device_t
Change-Id: I42b19d660b681cca8fea7d2f52b43c8daceb5e35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24 13:18:22 +00:00
Kyösti Mälkki b130a78257 mb/emulation/qemu-q35: Get rid of device_t
Change-Id: I74461e75abce6cdd0c7a16b3a6589de3486a1a3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24 13:18:07 +00:00
Arthur Heymans 0d284959dc nb/intel/x4x: Adapt post JEDEC for DDR3
Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24 13:05:32 +00:00
Arthur Heymans 3fa103a602 nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings
Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24 13:04:47 +00:00
Arthur Heymans b4a78045d5 nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings
When programming the final dram attribute and dram boundary settings,
on DDR3 dram one also needs to enable ZQCAL in the CxREFRCTRL (DRAM
Refresh Control) register as documented in "Intel ® 4 Series Chipset
Family" documentation.

Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-24 13:04:17 +00:00
Arthur Heymans b5170c3e92 nb/intel/x4x: Implement write leveling
DDR3 adapted a fly-by topology which allows for better signal
integrity but at the same time requires additional calibration. This
is done by settings the targeted rank in write leveling mode while
disabling output buffer on the other ranks. After that the DQS signal
gets sampled over DQ until a transition from high to low is found.

Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24 13:03:45 +00:00
Arthur Heymans f1287266ab nb/intel/x4x: Add DDR3 JEDEC init
Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs)

This also modifies the send_jedec_cmd function as DDR3 dimms can have
ranks mirrored which needs to be accounted for.

The ddr3_emrs1_config array is placed externally since it is also
needed for write leveling.

Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24 13:03:15 +00:00
Nico Huber 9129f1aae9 device: Always build device_simple.c for less code duplication
Change-Id: Iec0a11d67d7641996f26b3a01352be762006ebb6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24 12:17:51 +00:00
Elyes HAOUAS 7094f4ea61 src: Add space after 'while'
Change-Id: I44cdb6578f9560cf4b8b52a4958b95b65e0cd57a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-24 12:17:31 +00:00
Sumeet Pawnikar 20d7c876bd mb/intel/glkrvp: Remove unused DPTF_CPU_ACTIVE_ACx defines
GeminiLake platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx
defines. Removing these for GeminiLake RVP board as these are not being used.

Change-Id: I810809bf58198a028e6cfcdbd68887f5f154a0ad
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/26469
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24 12:17:18 +00:00
Sumeet Pawnikar ed70c18975 mb/google/reef: Remove unused DPTF_CPU_ACTIVE_ACx defines
ApolloLake based reef platform is fan-less design. We do not need
these DPTF_CPU_ACTIVE_ACx defines. Removing these from all reef
variants as those are not being used.

Change-Id: Id3cb7f7826a5e02cf447c70ab5cdc9b5d86982ca
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/26468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24 12:17:11 +00:00
Elyes HAOUAS 2526fd4a3d src: Remove space after `defined`
Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26460
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24 12:16:59 +00:00
Elyes HAOUAS ee8ce8d208 nb/intel/sandybridge: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: If36a879fbe7a93a214d74dbfa6fb3ee2d09a044a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24 10:36:37 +00:00
Emil Lundmark 9d5f9f2671 chromeec: Add support for controlling USB port power
This maps a bit field to the EC (EC_ACPI_MEM_USB_PORT_POWER) that can be
used to control the power state of up to 8 individual USB ports. Some
Chromeboxes have their GPIO pins for controlling USB port power wired to
the EC, so they cannot be accessed directly by coreboot.

Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://review.coreboot.org/26471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-24 09:24:18 +00:00
Elyes HAOUAS 5eec229d96 mb/intel/glkrvp: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I791a69aeca9b44daabc9a3e5fb9ac92e6b22f3e5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-24 06:49:03 +00:00
Elyes HAOUAS ab3a24ba2e mb/nvidia/l1_2pvv: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: Ife8ca30322d83c6d9276e79c057f12a901d6e8f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26312
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24 06:48:47 +00:00
Amanda Huang 6fcf7de925 mb/google/poppy: Enable SAR config on Nami
This change enables SAR config on Nami with CHROMEOS option.

BUG=b:75077304
BRANCH=master

Change-Id: I8217333db2db6c0fd5e1c144dedd3692b1e1e6a3
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-24 06:42:02 +00:00
Richard Spiegel 17da4f423a mb/google/kahlee/dsdt.asl: Add method _SWS
_SWS is the recommended method of wake source retrieval. Now that PM1I and
GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code.

BUG=b:76020953
TEST=Build grunt

Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-23 17:54:12 +00:00
Richard Spiegel dbee8aea32 stoneyridge: Store wake parameters in NVS
ACPI _SWS needs information on PM1 and ACPI events (though events can be
read directly). Unfortunately PM1 is cleared in normal path and in resume
path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS.

BUG=b:75996437
TEST=Build and boot grunt recording serial. Run suspend stress test, after
3 resumes closed file and examined for the message indicating what was
being saved to NVS. Two different path, normal boot (first boot) and
resume path had different PM1.

Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23 17:54:02 +00:00
Nico Huber 514bd56af9 3rdparty/libgfxinit: Update submodule pointer
Update to current master. Beside a minor workaround for GCC 8
compatibility, this includes only refactorings and preparations
for G4x support.

Change-Id: I6b2aa6bd9d41b852dacd8e1dfe89d92c8a548121
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26420
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23 12:43:03 +00:00
Patrick Georgi 2e8b770a9e 3rdparty/chromeec: Update to latest master
Includes the necessary changes to build with gcc 8.1

Change-Id: Ie8c3dede4d702ab7838162dbff09f94df34b7c91
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-23 12:02:58 +00:00
Elyes HAOUAS 0f5957a960 soc/amd/common/block/pci: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I82089475eb43d58303d1091f35aee06f1f04b4a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-23 09:57:45 +00:00
Elyes HAOUAS 777ccd4396 soc/amd/stoneyridge/: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-23 09:56:59 +00:00
Kyösti Mälkki 532001ae73 sb/amd/rs780: Get rid of device_t
Change-Id: Ica3b6f2d0b270930df77d528e70bd15972da8757
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23 09:31:47 +00:00
Kyösti Mälkki a211c1bf94 sb/amd/sr5650: Get rid of device_t
Change-Id: If03864d5e32dfc4a2e5e11a96a4df62699ca4392
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23 09:30:20 +00:00
Kyösti Mälkki f129aed5c2 mb/siemens/sitemp_g1p1: Get rid of device_t
Change-Id: I2362c46c0b525fa67833e52f210265da1926142c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-05-23 09:28:39 +00:00
Kyösti Mälkki ccb950265a mb/emulation/qemu-i440fx: Get rid of device_t
Change-Id: I11c35d22d9a9cba3cdb6af0ec1d2c01de8c20b6e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23 09:27:33 +00:00
Kyösti Mälkki 90ac7365ad nb/amd/pi: Get rid of device_t
Change-Id: I9b1c597f5c6995f19e9697e8aa698fa672a220b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26473
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23 09:26:56 +00:00
Matthias Gazzari d88cd70877 util/intelmetool: Add Makefile target for OLDARC definition
This allows one to compile intelmetool with support for older ME
versions by setting the OLDARC preprocessor definition.

For example, compiling with OLDARC enabled avoids the "ME: GET FW
VERSION message failed:" error on the Lenovo X201i (ME version 6.0).

Change-Id: I5eb0da7663e795f790e2723bb334447380724b56
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/26450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-23 08:31:45 +00:00
Kyösti Mälkki e2c2a4c42b nb/amd/agesa: Get rid of device_t
Change-Id: I5bd1c1cd71bd9541c1a95d444cd8d5ff40687dde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26436
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23 08:20:39 +00:00
Nick Vaccaro b5ad535d5d mb/google/poppy/variants/nocturne: enable MKBP
BUG=b:79617938
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", flash nocturne,
boot to kernel, run evtest and verify that cros-ec-buttons is present
and functional.

Change-Id: Id710782e1f4e18eaac2a90c7c0f91af5223dbce3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23 08:19:06 +00:00
Nick Vaccaro ba959ad2db mb/google/poppy/variants/nocturne: enable I2C #5 bus
Enable I2C #5 for rear camera and SAR.

BUG=b:79784124
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage' and verify i2c bus #5
is detected.

Change-Id: Ic5b754fb97231aeab0278d71f8ced9343c30feda
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23 08:18:54 +00:00
Nick Vaccaro 8c4b526fd2 mb/google/poppy/variants/nocturne: deassert audio amp reset
Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of
reset.

BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel,
and verify sound works via "aplay /dev/random"

Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23 08:18:41 +00:00
Nick Vaccaro 006114bbe0 mb/google/poppy/variants/nocturne: add touchscreen register info
- add ACPI register information for touchscreen WCOM digitizer

BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage" and verify
touchscreen on Nocturne board works.

Change-Id: I9790a930e8ed2748d568ce58c931ce34b3e22007
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-23 08:18:32 +00:00
Elyes HAOUAS 66faf0c286 sb/intel/i82801dx: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I36f064b67f14556e38b41b7f64c3e27d8d935367
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-23 05:22:57 +00:00
Elyes HAOUAS 17c59f5da5 sb/intel/i82870: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I751b72733de2e3bf3aebd1bc85dc83ec1c406faa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-23 05:20:25 +00:00
Srinidhi N Kaushik 5af546c5e4 soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI Init
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With 
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table 
entry for this range which caused a page fault. Since this test 
is anyway not exhaustive, we will skip the memory test in FSP.

There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.

FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence 
skipping SPI clock programming in FSP.

CQ-DEPEND=CL:*627827
BUG=b:78599939, b:78599576, b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26284
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22 15:52:20 +00:00
Srinidhi N Kaushik ee3158fd6c vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.3
Update FSP header files to match FSP Reference Code Release v2.0.3 for
Gemimilake

CQ-DEPEND=CL:*627827
Change-Id: I17438f18fc3a1ea7ad9bd69a06adb1330d917257
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26285
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22 15:52:11 +00:00
Martin Roth 2626ecdf50 Documentation: Update doxygen config files
- Update the config files to 1.8.13
- Unify the coreboot and coreboot_simple configs.  The only difference
now is that coreboot uses the graphviz library to generate call graphs
and other things, while coreboot_simple does not.  This means that the
doxygen_simple target builds in just over a minute, while the doxygen
build target takes roughly an hour.
- Both targets now only document coreboot proper.  While at times it
might be useful to see links to code from src/vendorcode, 3rdparty, or
util, these directories also really clutter up the doxygen output. To
make it easier to see the coreboot code, all of these directories are
excluded.

Change-Id: Iefc667ee2f65859f151f5a97b7b9d182e8ed31f7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22 07:27:58 +00:00