Commit Graph

23358 Commits

Author SHA1 Message Date
Pratik Prajapati 0e5eb46bb7 intel/common/block/sgx: Add API to enumerate SGX resources and update GNVS
Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 is called
to enumerate SGX resources.

Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:06:21 +00:00
Pratik Prajapati 90ebf96df5 soc/intel/skylake: Add GNVS variables and include SGX ASL
- Add GNVS variables for SGX
- Include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
  driver would let loaded

Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:06:15 +00:00
Pratik Prajapati 03a2353df6 soc/intel/apollolake: Add GNVS variables and include SGX ASL
- Add GNVS variables for SGX
- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
  driver would let loaded

Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:06:02 +00:00
Pratik Prajapati 771d4833d1 intel/common/acpi: Add common SGX ASL
- Add EPC device for SGX. Kernel SGX driver expects EPC device.
- Hid is INT0E0C
- version of the object is 1.0, so _STR is "Enclave Page Cache 1.0"

Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:05:53 +00:00
Martin Roth ba142c5ef0 vendorcode/amd/pi/00670F00: Remove S3 restore functions
These functions are not currently used, and were not in the original
AGESA source code drop.

The structs involved here were marked "private" in AGESA headerfiles
and should not be exposed. They could be handled as anonymous structs
and required allocation size is communicated by other means.

BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.

Change-Id: Iec346205470150257fd9d09131d54231b321740b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-20 17:49:02 +00:00
Martin Roth 2960043155 soc/amd/common: Set AltImageBasePtr to 0
In the original AGESA headers, AltImageBasePtr is a UINT32, so don't
set it to VOID.  0 works for either UINT32 or VOID *, as demonstrated
by the other 7 places in this file where it's already set to 0 instead
of NULL.

Change this location to 0 to support either version of the headers.

BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.

Change-Id: Ib6f3883e08231a6ca896c2ee2ef631c77feafedd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20 17:48:56 +00:00
Martin Roth 7eb363c505 Stoney Ridge Platforms: cast AGESA tables to void *
In the original AGESA headers, these tables are not defined as const.
Cast them to void * so that they'll work with either version of the
headers.

BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.

Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20 17:48:49 +00:00
Martin Roth c450fbe909 Stoney Ridge Platforms: Make AGESA callout tables common
There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.

Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd

Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.

Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4.  A bug has been filed for support for
the upcoming Grunt platform.

BUG=b:67209686
TEST=Build and boot on Kahlee

Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-20 17:48:37 +00:00
Patrick Georgi 44aaf6137d util/genbuild_h: improve robustness against corrupt .git directories
The new test lets git check if $top is actually a git repo, instead of
just looking for clues.

BUG=chromium:776174
BRANCH=none
TEST=`mv .git .foo; mkdir .git; util/genbuild_h/genbuild_h.sh` provides
a valid build.h instead of failing because git is unhappy about the
.git directory.

Change-Id: I7fcc64d66e0b59fca1479b4c142fd0559aa984f4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-20 09:40:09 +00:00
Jonathan Neuschäfer fe84292eeb board_status/towiki: Fix link to last report for "clone" boards
I noticed that the "last known good" field for the ThinkPad R400 pointed
nowhere. Instead of

	https://www.coreboot.org/Supported_Motherboards#lenovo.2Ft400

it pointed to

	https://www.coreboot.org/Supported_Motherboards#lenovo.2Fr400

which does not exist because if a board is marked as a "Clone of"
another one in board_info.txt, towiki uses the original board's reports
to derive the "last known good" date and color.

Change-Id: Ie235ca8e8691f49d041de7c5770eae77cdd444a7
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-10-20 02:22:23 +00:00
Kamil Wcislo 70b92456eb mainboard/pcengines/apu2: add apu3 and apu5 variants
Apu3 and apu5 are additional variants of apu2 board.
Apu3 has no LPC connector exposed, but has additional USB header. It has
also 2 slots for SIM cards and one of the gpios is used to control
switching between them.
Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches).

This patch adds support for those other variants by not introducing
additional code redundancy.

Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-20 02:19:23 +00:00
Chris Ching 6a35fab272 soc/amd/stoneyridge: Use macros for PCI_DEVFN calls
* Change all calls to PCI_DEVFN to macros
 * Remove CBB and CDB Kconfig since these are static for stoneyridge

BUG=b:62200746
TEST=build

Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19 21:07:10 +00:00
Richard Spiegel c5ecd3e14d soc/amd/stoneyridge: Replace magic registers
Replace southbridge registers and register values from magic numbers to
literals, provided these registers are currently defined publicly or in
NDA datasheet.

Registers available only internally to AMD are left unchanged.

BUG=b:62199625

Change-Id: I9187ba1c41ebb1201ddc177e8184672c60cd5f5d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19 20:52:51 +00:00
Chris Ching 782b9a7b75 Makefile.inc: remove '--global' flag from config check for gitconfig rule
As long as user.name and user.email are set, gitconfig should pass. This
handles if values are only set for the local repo, or if values are
stored in ~/.config/git/config

BUG=none
TEST=make gitconfig

Change-Id: Ie01e7a155f9e6db35d5991e4303aad85fb277a06
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19 20:13:06 +00:00
Lijian Zhao 025e0ccc59 intel/fsp: Update cannonlake FSP header
Update cannonlake FSP header file to revision 7.x.15.46. The following
item had been updated:
1. Remove/Hide restricted structure.
2. Add EBR as extention of RMT features.
3. Add cpu wakeup timer UPD.
4. Remove XHCI access lock UPD.

TEST=NONE

Change-Id: I065edbeffdaf555ea7d54ec3fdce56d026789c52
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 19:56:06 +00:00
Lijian Zhao e7a1e7d3c4 soc/intel/cannonlake: Fix HECI error on reset
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.

TEST= Force global reset from FSP and read back HECI bar in debug print.

Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 19:48:43 +00:00
Subrata Banik ed1694157c soc/intel/cannonlake: Use EBDA structure to store soc reserve memory size
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().

This patch avoids one extra calculate_dram_base() call.

BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.

Change-Id: I2771ea55253ca7d16cd2e2951889ab092b47a9b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22099
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19 17:36:16 +00:00
Subrata Banik f506cf0b8d soc/intel/skylake: Use EBDA structure to store soc reserve memory size
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().

This patch avoids one extra calculate_dram_base() call.

BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.

Change-Id: I52f359db5a712179d7f2accb4d323d759f3b052b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 17:36:06 +00:00
Abhay Kumar b0c4cbb7af soc/intel/cannonlake: Add IGD Support and pre-OS display code
1. Add IGD opregion initialization.
2. Use frame buffer return by FSP for display.
3. Derived from "src/soc/intel/apollolake/graphics.c" with changes
   needed for CNL.

TEST=Pre-OS screen comes up and VBT is getting passed to kernel.

Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-19 15:19:36 +00:00
Werner Zeh 0e35eb2434 siemens/mc_bdx1: Initialize GPIOs
Add GPIO initialization for mc_bdx1 mainboard. Call init_gpios() as
early as possible as FSP will set up things (like hiding PCI devices)
rather early. If connections on the mainboard are dependent on GPIO
settings then FSP can screw things up (e.g. disabling not yet connected
PCI root ports).

Change-Id: I003277cfb871f861900b7fcdc5ec851d4c1c1e6a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 15:13:45 +00:00
Werner Zeh 4bf11ce2b5 soc/fsp_broadwell_de: Add support for GPIO handling
Add functionality to initialize, set and read back GPIOs on FSP based
Broadwell-DE implementation.

Change-Id: Ibbd86e2142bbf5772eb4a91ebb9166c31d52476e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 15:13:40 +00:00
John E. Kabat Jr e77d588ee4 cpu/x86: add AMD registers to SMM save state
In amd64_smm_state_save_area_t break out fields in reserved4 to allow access.

BUG=b:65485690

Change-Id: I592fbf18c166dc1890010dde29f76900a6849016
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Reviewed-on: https://review.coreboot.org/22092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19 15:13:18 +00:00
Vagiz Trakhanov 216ad2170c sb/intel/bd82x6x: Add new USB currents
These currents were found on Gigabyte GA-Z77-DS3H with vendor bios.

Change-Id: I547c4ab3a2ce507d013ed527ab81291a916ce9b5
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-19 15:07:16 +00:00
Vagiz Trakhanov 771be480a6 nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs
XMP profiles can have a restriction on max supported DIMMs per channel,
but many configurations work with more DIMMs.

This is relevant on mainboards with 2 DIMM slots per channel (usually 4
in total). Populating both slots with DIMMs that support XMP profiles only
with 1 DIMM per channel turns off said XMP profiles.

TEST=On a system with two DIMM slots per channel populate both slots on
one channel and ensure that DIMMs run with XMP profiles enabled.

Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-19 15:06:13 +00:00
Martin Roth 15cb5be5b0 src/vendorcode/amd: Use AR variable in Makefiles
Change-Id: I5158f1bcc18eb5b15f310d0cf50fb787c12317c8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19 14:03:51 +00:00
Kyösti Mälkki e097585fdf AGESA f14: Fix DDI maps in OemCustomize.c
Creates identical object files.

Change-Id: Ie8adb21a753cee6a72dae5eeb64a255e6ead2fe7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19 11:24:19 +00:00
Kyösti Mälkki 9fee35c6c4 AGESA: Split long lines in OemCustomize.c
Change-Id: I907f55622e6aaba401471239f706ab24cd26319f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19 11:24:09 +00:00
Kyösti Mälkki c700829cd3 AGESA f14: Drop PlatformGnbPcieComplex.h
These were OEM configurations hidden inside a header file, notation
was already dropped for f15tb and f16kb.

Change-Id: Id64fa861fd516e9f7cae9eba9b8145e033fe9bdd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19 11:23:53 +00:00
Michał Żygowski 57760e3cdf pcengines/apu2: Add timestamps to romstage
This change adds timestamps to romstage in order to keep
PC Engines apu2 platform in active codebase.

Change-Id: Ie0286d4982623da9d035c47df6077edaf51e5110
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/22071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19 11:23:29 +00:00
Paul Menzel 4e4a763703 Enable time stamp collection by default on x86
Collecting time stamps is useful, especially for board status uploads,
and doesn’t come with any downsides. So enable it by default on as many
boards as possible.

The boards below currently fail to build properly, so only enable it by
default on x86.

1.  board.CUBIETECH_CUBIEBOARD
2.  board.EMULATION_QEMU_POWER8
3.  board.EMULATION_QEMU_UCB_RISCV
4.  board.EMULATION_SPIKE_UCB_RISCV
5.  board.LOWRISC_NEXYS4DDR
6.  board.TI_BEAGLEBONE

Change-Id: Ib01176fc2a4dffe37827c136bb8214083ce61180
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/11864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-19 09:10:49 +00:00
Furquan Shaikh 1432cbc4da google/chromeec: Do not set wake mask before logging EC events
Earlier the EC expected the host to set appropriate masks before
reading host events. However, with recent change in EC, this is no
longer required. This change removes the setting of wake_mask before
and after reading the host events. However, in order to support older
versions of EC, a new feature flag is added on the EC side that
informs the host whether or not it is using the new way of reporting
host events without having to set wake mask.

CQ-DEPEND=CL:719578
TEST=Verified that EC wake events are correctly logged with both old
and new versions of EC.

Change-Id: Ib17e1296fb7d3bbc84fc7581fd0a9bd179ac87b9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22006
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19 00:44:31 +00:00
Furquan Shaikh 4854761ba4 mb/google/poppy: Log EC events during S0ix resume
This change adds support for logging EC events during S0ix resume.

BUG=b:67874513
TEST=Verified that EC events are correctly logged during S0ix resume:
284 | 2017-10-16 20:45:12 | S0ix Enter
285 | 2017-10-16 20:45:16 | S0ix Exit
286 | 2017-10-16 20:45:16 | Wake Source | Power Button | 0
287 | 2017-10-16 20:45:16 | EC Event | Power Button
288 | 2017-10-16 20:45:35 | S0ix Enter
289 | 2017-10-16 20:45:40 | S0ix Exit
290 | 2017-10-16 20:45:40 | Wake Source | GPIO | 112
291 | 2017-10-16 20:45:40 | EC Event | Lid Open
292 | 2017-10-16 20:50:51 | S0ix Enter
293 | 2017-10-16 20:50:59 | S0ix Exit
294 | 2017-10-16 20:50:59 | Wake Source | GPIO | 112
295 | 2017-10-16 20:50:59 | EC Event | Mode change

Change-Id: I9f6dcb8852d94ebf90bb5b63a17fde524d58d49f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:56 +00:00
Furquan Shaikh 70b257f1b4 ec/google/chromeec: Export google_chromeec_log_events in ec.h
This change makes google_chromeec_log_events available to callers
outside ec.c.

BUG=b:67874513

Change-Id: I36cc1e66e035eda707297d8153cd3fabeadfee45
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:51 +00:00
Furquan Shaikh dd825fe73e soc/intel/skylake: Probe XHCI for wake source for Internal PME
If GPE_STS indicates that the wake source is internal PME, but none of
the controllers have the PME_STS bit set, then try probing individual
XHCI ports to see if one of those was a wake source. In some cases
e.g. gsmi logging with S0ix, pci_pm_resume_noirq runs before gsmi
callback and clears PME_STS_BIT in controller register. In such cases,
xhci port status might provide a better idea about the wake source.

BUG=b:67874513

Change-Id: I841bb2abccfa9bd6553c1513e88a6306b40315e4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:45 +00:00
Furquan Shaikh 7284efe594 soc/intel/skylake: Prevent false logs in pch_xhci_port_wake_check
1. Ensure that port_status read is not all 1s to ensure that read from
mmio address returned valid data.
2. If device connect/disconnect shows that it was a wake source, there
is no need to check for usb activity.

BUG=b:67874513

Change-Id: Id8b4a1fec7bfe530fe435a0f52944b273cdd89ad
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:39 +00:00
Furquan Shaikh 8f2eadd8d0 soc/intel/skylake: Define mask for SMI handlers that can be run in SCI mode
This change adds a mask to allow SMI handlers to be run even in SCI
mode. This prevents any SMI handlers from accidentally taking
unnecessary action in SCI mode.

Add APM_STS and SMI_ON_SLP_EN_STS to this mask to allow gsmi and sleep
to work in SCI mode.

BUG=b:67874513

Change-Id: I298f8f6ce28c9746cbc1fb6fc96035b98a17a9e3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:34 +00:00
Furquan Shaikh c565bd44d1 soc/intel/skylake: Support logging wake source in SMM
This change adds support for logging wake source information in gsmi
callbacks. With this change, all the elog logging infrastructure can
be used for S0ix as well as S3 on skylake.

BUG=b:67874513

Change-Id: Ie1f81e956fe0bbe2e5e4c706f27997b7bd30d5e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:30 +00:00
Furquan Shaikh 3efeeb2c8f soc/intel/skylake: Move power_state functions to pmutil.c
This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.

BUG=b:67874513

Change-Id: I375ac029520c2cdd52926f3ab3c2d5559936dd8c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22085
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19 00:43:22 +00:00
Furquan Shaikh 2ce4ec0dcb soc/intel/skylake: Use PCH_DEV_* instead of PCH_DEVFN_*
This change allows the same functions to be used across ramstage and
smm without having to add checks for what stage is using it.

BUG=b:67874513

Change-Id: I3b10c9e8975e8622d8cb0f66d90d39a914ba7e1c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:17 +00:00
Furquan Shaikh a2480184e0 soc/intel/skylake: Use newly added pmc_read_pm1_control
BUG=b:67874513

Change-Id: I298065f30647ae9bba8f6a8481bd34eec64f1d8e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:11 +00:00
Furquan Shaikh 43810d9332 soc/intel/apollolake: Use newly added pmc_read_pm1_control
BUG=b:67874513

Change-Id: I6d5a76122b7d6e508e5ff3f4099e5d706fb48f9d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:05 +00:00
Furquan Shaikh ab6201835a soc/intel/common/block/pmc: Add helper routines to read/write PM1_CNT
This change adds and uses helper routines for reading and writing
PM1_CNT register.

BUG=b:67874513

Change-Id: I69b9347ab54a392b67ba733eb00922583dc1ee5f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19 00:42:58 +00:00
Furquan Shaikh e48fb54b16 soc/intel/common/block/pmc: Add new function pmc_fill_pm_reg_info
This change creates a new function pmc_fill_pm_reg_info that fills
chipset_power_state structure with all the PM register
information. On the other hand, already existing pmc_fill_power_state
calls into pmc_fill_pm_reg_info and then checks and returns previous
sleep state information. This allows caller to get all the PM register
information when previous sleep state is not relevant.

BUG=b:67874513

Change-Id: Idc91e4aef5379549355aceb685f7afafa6a220c5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22080
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19 00:42:53 +00:00
Furquan Shaikh 2dc5eadccc elog: Support logging S0ix sleep/wake info in elog
1. Add support for new GSMI commands to log S0ix entry/exit
information in elog.
2. In case of resume, provide callbacks to allow platform and
mainboard to log any wake source information.

BUG=b:67874513

Change-Id: I593e8a9e31cad720ac1f77aab447a0dbdbe9a28b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:42:49 +00:00
Vaibhav Shankar f36ed21c57 mainboard/intel/cannonlake_rvp: Enable hardware P state control
This patch provides configuration parameter to enable/disable
Intel Speed Shift Technology.

Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-18 20:07:45 +00:00
Aaron Durbin f46a9a0d3a arch/x86: restore forwarding table on resume for EARLY_EBDA_INIT
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path)
the BDA and EBDA are wiped in the resume path. However, the coreboot
table forwarding entry wasn't taken into account so that was wiped
which resulted in cbmem not working on the resume path. Fix this
by stashing the forwarding table in cbmem and restoring it on
the resume path.

Change-Id: I142503535a78635fbb1c698fc7d032c1a2921813
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-18 19:56:21 +00:00
Lijian Zhao c672043766 soc/intel/cannonlake: Set platform Debug Probe Type
Add option for user to select what kind of probe can be used for
platform debug.

TEST=Set to XDP and boot up system with XDP hooked, able to halt.

Change-Id: Ib6add93e3f1c8a646aa625a4cea9be0acecc0487
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21942
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18 19:56:09 +00:00
Lijian Zhao 584af87483 intel/cannonlake_rvp: Enable Audio DSP
Enable Audio DSP by default on cannonlake rvp platform.

TEST=Boot up into OS and check Audio driver debug print.

Change-Id: I6892c6d349019550c967ef30b84d385f396fc388
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 19:55:49 +00:00
Lijian Zhao 0b21ad9e80 intel/cannonlake_rvp: Declare PCIE clock usage
Define PCI express clock usage for cannonlake u and cannonlake y rvp
based on board design.

TEST=Bootable into OS.

Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 19:46:33 +00:00
Lijian Zhao 580bc412c7 soc/intel/cannonlake: Update PCIE CLKREQ programing
UPD of PCI express clock request was updated in FSP 7.0.14.11,
change that in coreboot accordingly.

TEST=NONE

Change-Id: I2261deccfb489c0de577d580997744a484f07a04
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18 19:46:10 +00:00