Add SPD support to gimble for LPDDR4 memory part K4UBE3D4AA-MGCR.
BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ida21fd50129412af59a341dea45232fd0f9931ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57253
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 98ec53bdf1 (mb/google/caroline:
Re-enable I2C2 / fix digitizer) enabled I2C #2 in the `SerialIoDevMode`
array, but left the device disabled in the devicetree. Enable it.
Change-Id: I67eec1c753bfd2a78ed0c1e0a78057cd4a3d4153
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy
boards only enable UART 0 because it's function 0 of PCI device 30, and
the PCI specification requires that function 0 of multifunction devices
be implemented if other functions are implemented as well.
Nautilus got remedied in commit 8a1f095e50
(mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by
using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the
SerialIO device. This way, it remains enabled and the GPIO settings will
not be overwritten by FSP.
However, not all variants do this, but use some UART 0 pads as GPIOs. To
prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the
variants.
Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55236
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change can make the code be more flexible. And later we will use
amd_cb_config to transfer parameters.
Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The issue is reported by Coverity. Using strcpy or strcat copying
string without checking length may cause overflow.
BUG=b:188769921
Reported-by: Coverity (CID:1438964)
Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure that the 48MHz clock output that is typically used as a clock
source for an I2S audio codec or a Super I/O chip.
TEST=On Guybrush before and after this patch the final state of
MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the SPI configuration has been moved into Kconfig, it is no
longer needed in devicetree.
BUG=b:194919326
TEST=Build & boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ifdcd3f33173194c4a25794137756b143751edd70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch adds code to print the current SPI speeds for each of the 4
different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays
the SPI mode and whether or not SPI100 mode is enabled.
BUG=b:194919326
TEST: Display the speed, change speeds, show that new speeds are the
expected values.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add the fch_spi_early_init call in fch_pre_init to perform early SPI
initialization which enables SPI ROM and setting the speed & read modes.
BUG=b:194919326
TEST=Build and boot to OS in Guybrush.
Change-Id: Ibfbe6e16bd6b0dd46c13cecf2a35f0c0b4576b88
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56684
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get the settings for fast-read and mode from EFS, and reprogram those.
Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings.
BUG=b:195943311
TEST=Boot and see that SPI was set to the correct speed & mode
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The common_i2c_save struct isn't specific to the I2C code and since it
contains the state of the GPIO control & status register and the state
of the GPIO MUX register, move it to include/amdblocks/gpio_banks.h and
rename it to soc_amd_gpio_register_save.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7cd47e5a32427d856948e319de8dfad8c928e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
No need to strip the quotes of the FSP-M file path in the size check and
it's always a good idea to not remove the quotes around file paths that
will get passed as parameters to shell programs so that spaces in the
path can't cause malfunction.
TEST=All cases still behave as expected for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ieeea84b5861f9d15b2472208432169dc8e3f0049
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs.
The BDF for this PCIe slot is pci is: 0000:00:1d.0
TEST = show device command:
$ lspci -s 00:19.0
expect this:
00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on latest schematic to update the gpio table.
BUG=b:197308586
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0d91199ffd2128a136ea0a33dfe7affa77ae61d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Based on latest shcematic to update the device tree.
BUG=b:197308586
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I59601571c5e4c2d19738cb333605fb22e1ea0d2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Power down the eMMC controller via the AOAC interface when it's not
enabled in the devicetree.
BUG=b:184978118
TEST=On guybrush the unused eMMC controller is disabled in AOAC after
applying this patch. Before this patch it was enabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18f4626a29fdc422218777058341b0eae401bcd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
NCT6776's data sheet does say that the virtual LDN of GPIO base should
be 0x308, and most mainboards using it usually correctly config it in
devicetree.cb under the path 2e.308, but in nct6776.h it used to be
defined as 8 from the beginning (an ancient commit 1e3a22649a, lately
revived in commit f95daa510d), identical to the LDN of WDT, which
eliminates the definition of value 2e.308, and makes related resource
allocations unable to take effect. (in log we can find "PNP: 002e.308
missing read_resources" if 2e.308 is enabled and assigned with
resources)
In this commit, NCT6776_GPIOBASE is set to a value consistent with the
data sheet.
With this commit, resources under 2e.308 of NCT6776 can be allocated
successfully.
Change-Id: I604bad7ab34a8f57262fdec508e5952cf8eabf1c
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change follows other Intel SoCs common way to support SKUs with
bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and
allowing its detection at boottime. It completes support for HCV/DNV
after base SoC patch: commit ba936ce5db
soc/intel/denverton_ns: Ensure CPU device has a valid link
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)."
Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11
Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size
call evaluates to an empty string, so the file-size call will run
"cat | wc -c" which will cause make to get stuck in there. Also print a
message when no FSP-M file is specified that the resulting image won't
boot successfully.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This documentation doesn't add any more value. Thus, remove it.
Change-Id: I0402bc736c6cc77d88a836bddce8eadae8ec5d7c
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:194356991
TEST=ALC5682-VD/ALC5682-VS audio codec can work
Change-Id: I71b824c42c13cc2a8bebe0072de4a65ce238f074
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add supported memory part in the mem_parts_used.txt and generate the
SPD ID for the part. The memory part being added is:
MT53E512M32D1NP-046 WT:B
BUG=b:194223174
BRANCH=dedede
TEST=Build the boten board.
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I36fcbf7333fd9e85b28baa64676f8435aca63889
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update the USB port configuration based on driblee schematic.
USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 1
USB2 [3]: None
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: None
USB2 [7]: None
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: None
BUG=b:195622487, b:191732473
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56997
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add two thermal sensors for fan and wwan for DPTF based thermal control.
BRANCH=None
BUG=b:181271666
TEST=None
Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
This will add ACPI information to enable WACOM touchscreen.
TEST=Boot DUT and issue command:
$ ls -al /sys/bus/i2c/devices
WACOM PWB-D893 device should be listed and touchscreen should be functional.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Add the support RAM parts for Corori.
Here is the ram part number list:
DRAM Part Name ID to assign
H9HCNNNBKMMLXR-NEE 0 (0000)
K4U6E3S4AA-MGCR 0 (0000)
lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR
BUG=b:196744958
BRANCH=keeby
TEST=emerge-keeby coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ia11b5db145deeea838a8f5949accdb11e13342f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56988
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow schematic to modify USB port settings.
USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 0
USB2 [3]: None
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: None
USB2 [7]: Integrated Bluetooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: None
BUG=b:196998272
BRANCH=keeby
TEST=FW_NAME="corori" emerge-keeby coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2045b2be9d79bfd394fa4520faa0fb552a704206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57010
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the anahera variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:197850509
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ANAHERA
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id7649d56a8d6f85d12208f7ddaf2f71a7fe98e8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Ensure braces are consistent on all branches of a conditional statement,
as per the coding style.
Tested with BUILD_TIMELESS=1, Google Butterfly remains identical.
Change-Id: I34f3b22486e0f0712bc248477acb43012b21c5ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100
case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to
Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config
for the EM100 emulator case that has limited SPI frequency support.
Tested on Majolica by Martin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define
this function accordingly.
Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the `mainboard_fill_spd_data` function out of romstage, in
preparation to confine `pei_data` usage to as few files as possible.
Change-Id: I6447da4d135d920f9145e817bfb7f9056e09df84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55805
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variants only need to provide the SPD index and whether said index
corresponds to a dual-channel configuration, which can be achieved
without using `pei_data`. Add two functions that return the values
and use them in `spd.c` at mainboard level.
Change-Id: I9bc4527057d4a771883c8cc60da2501516d6fb94
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This change calls `add_more_links()` in `denverton_init_cpus()` if
`dev->link_list` is NULL. This condition can occur if mainboard does
not add any APIC device in the device tree.
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the
same SKU and steping (Intel Atom C3538)."
Change-Id: I6f453901b17f7eff22beed8dbf6995cdc9f9b776
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57152
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mark Hsieh