2020-05-08 19:28:13 +02:00
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/* inteltool - dump all registers on an Intel CPU + chipset based system */
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util/: Replace GPLv2 boiler plate with SPDX header
Used commands:
perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist)
perl -i -p0e 's|This[\s*]*program[\s*]*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.*[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist)
perl -i -p0e 's|\/\*[\s*]*.*This[\s*#]*program[\s*#]*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.*[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
Change-Id: I1008a63b804f355a916221ac994701d7584f60ff
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08 20:48:04 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2008-08-20 15:41:24 +02:00
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2017-04-05 17:39:57 +02:00
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#ifndef INTELTOOL_H
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#define INTELTOOL_H 1
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2020-03-13 19:08:21 +01:00
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#include <arch/mmio.h>
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2017-04-05 17:30:20 +02:00
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#include <commonlib/helpers.h>
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2008-08-20 15:41:24 +02:00
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#include <stdint.h>
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2009-09-01 11:52:14 +02:00
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2023-03-10 18:14:11 +01:00
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#if defined(__linux__)
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2008-12-04 16:18:20 +01:00
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#include <sys/io.h>
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2009-09-01 11:52:14 +02:00
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#endif
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#if (defined(__MACH__) && defined(__APPLE__))
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2017-06-05 12:33:23 +02:00
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/* DirectHW is available here: https://www.coreboot.org/DirectHW */
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2009-09-01 11:52:14 +02:00
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#define __DARWIN__
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2011-03-18 23:08:39 +01:00
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#include <DirectHW/DirectHW.h>
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2008-12-04 16:18:20 +01:00
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#endif
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2016-01-05 17:59:06 +01:00
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#ifdef __NetBSD__
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#include <pciutils/pci.h>
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#else
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2008-08-20 15:41:24 +02:00
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#include <pci/pci.h>
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2016-01-05 17:59:06 +01:00
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#endif
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2008-08-20 15:41:24 +02:00
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2010-10-24 15:50:13 +02:00
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/* This #include is needed for freebsd_{rd,wr}msr. */
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#if defined(__FreeBSD__)
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#include <machine/cpufunc.h>
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#endif
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2016-01-05 17:59:06 +01:00
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#ifdef __NetBSD__
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static inline uint8_t inb(unsigned port)
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{
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uint8_t data;
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__asm volatile("inb %w1,%0" : "=a" (data) : "d" (port));
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return data;
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}
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static inline uint16_t inw(unsigned port)
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{
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2016-10-19 17:59:10 +02:00
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uint16_t data;
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__asm volatile("inw %w1,%0": "=a" (data) : "d" (port));
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return data;
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2016-01-05 17:59:06 +01:00
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}
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static inline uint32_t inl(unsigned port)
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{
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uint32_t data;
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__asm volatile("inl %w1,%0": "=a" (data) : "d" (port));
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return data;
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}
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#endif
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2008-08-20 15:41:24 +02:00
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#define INTELTOOL_VERSION "1.0"
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/* Tested chipsets: */
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2009-09-30 19:05:46 +02:00
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
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#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
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#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
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2010-12-17 23:34:58 +01:00
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#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0
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2010-04-21 08:23:19 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH6 0x2640
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
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#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
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#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
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#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
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2010-08-17 10:33:44 +02:00
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#define PCI_DEVICE_ID_INTEL_NM10 0x27bc
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#define PCI_DEVICE_ID_INTEL_ICH8 0x2810
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
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2015-03-01 10:14:15 +01:00
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#define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811
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2010-05-30 14:33:12 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912
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#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914
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#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916
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#define PCI_DEVICE_ID_INTEL_ICH9 0x2918
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#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919
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#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
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2020-07-09 14:16:39 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH10DO 0x3a14
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2009-09-30 19:05:46 +02:00
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#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
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2021-11-14 15:34:02 +01:00
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#define PCI_DEVICE_ID_INTEL_ICH10 0x3a18
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#define PCI_DEVICE_ID_INTEL_ICH10D 0x3a1a
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2013-05-28 11:30:25 +02:00
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#define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01
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#define PCI_DEVICE_ID_INTEL_P55 0x3b02
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#define PCI_DEVICE_ID_INTEL_PM55 0x3b03
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#define PCI_DEVICE_ID_INTEL_H55 0x3b06
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#define PCI_DEVICE_ID_INTEL_QM57 0x3b07
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#define PCI_DEVICE_ID_INTEL_H57 0x3b08
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#define PCI_DEVICE_ID_INTEL_HM55 0x3b09
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#define PCI_DEVICE_ID_INTEL_Q57 0x3b0a
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#define PCI_DEVICE_ID_INTEL_HM57 0x3b0b
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF 0x3b0d
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#define PCI_DEVICE_ID_INTEL_B55_A 0x3b0e
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#define PCI_DEVICE_ID_INTEL_QS57 0x3b0f
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#define PCI_DEVICE_ID_INTEL_3400 0x3b12
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#define PCI_DEVICE_ID_INTEL_3420 0x3b14
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#define PCI_DEVICE_ID_INTEL_3450 0x3b16
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#define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e
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2010-06-01 12:04:28 +02:00
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
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2019-12-29 14:31:01 +01:00
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#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_U 0x3482
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2013-03-29 17:57:15 +01:00
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#define PCI_DEVICE_ID_INTEL_Z68 0x1c44
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#define PCI_DEVICE_ID_INTEL_P67 0x1c46
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#define PCI_DEVICE_ID_INTEL_UM67 0x1c47
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#define PCI_DEVICE_ID_INTEL_HM65 0x1c49
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#define PCI_DEVICE_ID_INTEL_H67 0x1c4a
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#define PCI_DEVICE_ID_INTEL_HM67 0x1c4b
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#define PCI_DEVICE_ID_INTEL_Q65 0x1c4c
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#define PCI_DEVICE_ID_INTEL_QS67 0x1c4d
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#define PCI_DEVICE_ID_INTEL_Q67 0x1c4e
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#define PCI_DEVICE_ID_INTEL_QM67 0x1c4f
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#define PCI_DEVICE_ID_INTEL_B65 0x1c50
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#define PCI_DEVICE_ID_INTEL_C202 0x1c52
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#define PCI_DEVICE_ID_INTEL_C204 0x1c54
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#define PCI_DEVICE_ID_INTEL_C206 0x1c56
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#define PCI_DEVICE_ID_INTEL_H61 0x1c5c
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#define PCI_DEVICE_ID_INTEL_Z77 0x1e44
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#define PCI_DEVICE_ID_INTEL_Z75 0x1e46
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#define PCI_DEVICE_ID_INTEL_Q77 0x1e47
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#define PCI_DEVICE_ID_INTEL_Q75 0x1e48
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#define PCI_DEVICE_ID_INTEL_B75 0x1e49
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#define PCI_DEVICE_ID_INTEL_H77 0x1e4a
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#define PCI_DEVICE_ID_INTEL_C216 0x1e53
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#define PCI_DEVICE_ID_INTEL_QM77 0x1e55
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#define PCI_DEVICE_ID_INTEL_QS77 0x1e56
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#define PCI_DEVICE_ID_INTEL_HM77 0x1e57
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#define PCI_DEVICE_ID_INTEL_UM77 0x1e58
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#define PCI_DEVICE_ID_INTEL_HM76 0x1e59
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#define PCI_DEVICE_ID_INTEL_HM75 0x1e5d
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#define PCI_DEVICE_ID_INTEL_HM70 0x1e5e
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#define PCI_DEVICE_ID_INTEL_NM70 0x1e5f
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2014-10-30 10:30:40 +01:00
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
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2017-04-13 19:22:33 +02:00
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3
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2018-07-24 06:09:47 +02:00
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03
|
2019-02-19 23:49:11 +01:00
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE 0x9d41
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL 0x9d43
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL 0x9d46
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL 0x9d48
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL 0x9d53
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL 0x9d56
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL 0x9d58
|
2018-07-24 06:09:47 +02:00
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b
|
2019-06-12 06:23:46 +02:00
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#define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84
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2020-08-08 18:17:31 +02:00
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#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM 0x0284
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#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE 0x0285
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2021-07-09 16:00:16 +02:00
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#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER 0xa081
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#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM 0xa082
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#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE 0xa083
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#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER 0xa086
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#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM 0xa087
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2017-10-28 14:45:48 +02:00
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#define PCI_DEVICE_ID_INTEL_H110 0xa143
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#define PCI_DEVICE_ID_INTEL_H170 0xa144
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#define PCI_DEVICE_ID_INTEL_Z170 0xa145
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#define PCI_DEVICE_ID_INTEL_Q170 0xa146
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#define PCI_DEVICE_ID_INTEL_Q150 0xa147
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#define PCI_DEVICE_ID_INTEL_B150 0xa148
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#define PCI_DEVICE_ID_INTEL_C236 0xa149
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#define PCI_DEVICE_ID_INTEL_C232 0xa14a
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#define PCI_DEVICE_ID_INTEL_QM170 0xa14d
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#define PCI_DEVICE_ID_INTEL_HM170 0xa14e
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2017-03-30 17:45:36 +02:00
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#define PCI_DEVICE_ID_INTEL_CM236 0xa150
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2017-10-28 14:45:48 +02:00
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#define PCI_DEVICE_ID_INTEL_HM175 0xa152
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#define PCI_DEVICE_ID_INTEL_QM175 0xa153
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#define PCI_DEVICE_ID_INTEL_CM238 0xa154
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2019-02-19 11:51:34 +01:00
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2019-08-16 18:15:12 +02:00
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#define PCI_DEVICE_ID_INTEL_C621 0xa1c1
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#define PCI_DEVICE_ID_INTEL_C622 0xa1c2
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#define PCI_DEVICE_ID_INTEL_C624 0xa1c3
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#define PCI_DEVICE_ID_INTEL_C625 0xa1c4
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#define PCI_DEVICE_ID_INTEL_C626 0xa1c5
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#define PCI_DEVICE_ID_INTEL_C627 0xa1c6
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#define PCI_DEVICE_ID_INTEL_C628 0xa1c7
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#define PCI_DEVICE_ID_INTEL_C629 0xa1ca
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2020-07-16 23:19:41 +02:00
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#define PCI_DEVICE_ID_INTEL_C621A 0xa1cb
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#define PCI_DEVICE_ID_INTEL_C627A 0xa1cc
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#define PCI_DEVICE_ID_INTEL_C629A 0xa1cd
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2019-08-16 18:15:12 +02:00
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#define PCI_DEVICE_ID_INTEL_C624_SUPER 0xa242
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#define PCI_DEVICE_ID_INTEL_C627_SUPER_1 0xa243
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#define PCI_DEVICE_ID_INTEL_C621_SUPER 0xa244
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#define PCI_DEVICE_ID_INTEL_C627_SUPER_2 0xa245
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#define PCI_DEVICE_ID_INTEL_C628_SUPER 0xa246
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2020-07-16 23:19:41 +02:00
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#define PCI_DEVICE_ID_INTEL_C621A_SUPER 0xa24a
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#define PCI_DEVICE_ID_INTEL_C627A_SUPER 0xa24b
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#define PCI_DEVICE_ID_INTEL_C629A_SUPER 0xa24c
|
2019-08-16 18:15:12 +02:00
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2021-05-03 23:06:22 +02:00
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#define PCI_DEVICE_ID_INTEL_EBG 0x1b81
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2021-06-25 11:07:32 +02:00
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#define PCI_DEVICE_ID_INTEL_H270 0xa2c4
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#define PCI_DEVICE_ID_INTEL_Z270 0xa2c5
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#define PCI_DEVICE_ID_INTEL_Q270 0xa2c6
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#define PCI_DEVICE_ID_INTEL_Q250 0xa2c7
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#define PCI_DEVICE_ID_INTEL_B250 0xa2c8
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#define PCI_DEVICE_ID_INTEL_Z370 0xa2c9
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#define PCI_DEVICE_ID_INTEL_H310C 0xa2ca
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#define PCI_DEVICE_ID_INTEL_X299 0xa2d2
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|
2019-02-19 11:51:34 +01:00
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|
|
#define PCI_DEVICE_ID_INTEL_H310 0xa303
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#define PCI_DEVICE_ID_INTEL_H370 0xa304
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#define PCI_DEVICE_ID_INTEL_Z390 0xa305
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#define PCI_DEVICE_ID_INTEL_Q370 0xa306
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#define PCI_DEVICE_ID_INTEL_B360 0xa308
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#define PCI_DEVICE_ID_INTEL_C246 0xa309
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#define PCI_DEVICE_ID_INTEL_C242 0xa30a
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#define PCI_DEVICE_ID_INTEL_QM370 0xa30c
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#define PCI_DEVICE_ID_INTEL_HM370 0xa30d
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#define PCI_DEVICE_ID_INTEL_CM246 0xa30e
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|
2021-07-09 16:00:16 +02:00
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|
#define PCI_DEVICE_ID_INTEL_Q570 0x4384
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|
#define PCI_DEVICE_ID_INTEL_Z590 0x4385
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|
#define PCI_DEVICE_ID_INTEL_H570 0x4386
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#define PCI_DEVICE_ID_INTEL_B560 0x4387
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|
#define PCI_DEVICE_ID_INTEL_H510 0x4388
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#define PCI_DEVICE_ID_INTEL_WM590 0x4389
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|
#define PCI_DEVICE_ID_INTEL_QM580 0x438a
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|
#define PCI_DEVICE_ID_INTEL_HM570 0x438b
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|
#define PCI_DEVICE_ID_INTEL_C252 0x438c
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|
#define PCI_DEVICE_ID_INTEL_C256 0x438d
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|
|
#define PCI_DEVICE_ID_INTEL_W580 0x438f
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|
|
2022-04-05 10:40:03 +02:00
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|
#define PCI_DEVICE_ID_INTEL_H610 0x7a87
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|
#define PCI_DEVICE_ID_INTEL_B660 0x7a86
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|
|
#define PCI_DEVICE_ID_INTEL_H670 0x7a85
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|
|
#define PCI_DEVICE_ID_INTEL_Q670 0x7a83
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|
|
#define PCI_DEVICE_ID_INTEL_Z690 0x7a84
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|
|
#define PCI_DEVICE_ID_INTEL_W680 0x7a88
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|
|
#define PCI_DEVICE_ID_INTEL_W685 0x7a8a
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|
#define PCI_DEVICE_ID_INTEL_WM690 0x7a8d
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|
|
#define PCI_DEVICE_ID_INTEL_HM670 0x7a8c
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|
|
#define PCI_DEVICE_ID_INTEL_WM790 0x7a0d
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|
|
#define PCI_DEVICE_ID_INTEL_HM770 0x7a0c
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|
|
2009-09-30 19:05:46 +02:00
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|
|
#define PCI_DEVICE_ID_INTEL_82810 0x7120
|
2012-10-13 02:19:30 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
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|
|
#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
|
2010-02-22 12:26:06 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82830M 0x3575
|
2009-09-30 19:05:46 +02:00
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|
|
#define PCI_DEVICE_ID_INTEL_82845 0x1a30
|
2010-12-17 23:34:58 +01:00
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|
|
#define PCI_DEVICE_ID_INTEL_82865 0x2570
|
2010-04-21 08:23:19 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82915 0x2580
|
2009-09-30 19:05:46 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82945P 0x2770
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|
|
#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
|
2012-10-13 02:19:30 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac
|
2012-10-13 06:23:52 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82946 0x2970
|
2012-10-13 02:19:30 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82965PM 0x2a00
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82Q965 0x2990
|
2009-09-30 19:05:46 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82975X 0x277c
|
2009-11-02 16:01:49 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
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|
|
#define PCI_DEVICE_ID_INTEL_82G33 0x29c0
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|
|
|
#define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
|
2012-10-13 02:19:30 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82X38 0x29e0
|
2011-04-04 07:53:19 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_32X0 0x29f0
|
2015-08-17 13:04:41 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82XX4X 0x2a40
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|
|
#define PCI_DEVICE_ID_INTEL_82Q45 0x2e10
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|
|
#define PCI_DEVICE_ID_INTEL_82G45 0x2e20
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|
|
#define PCI_DEVICE_ID_INTEL_82G41 0x2e30
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|
|
#define PCI_DEVICE_ID_INTEL_82B43 0x2e40
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|
|
#define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90
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|
|
|
|
|
2018-06-20 01:52:19 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_C8_MOBILE 0x8c41
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|
|
#define PCI_DEVICE_ID_INTEL_C8_DESKTOP 0x8c42
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_Z87 0x8c44
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_Z85 0x8c46
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|
|
|
#define PCI_DEVICE_ID_INTEL_HM86 0x8c49
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|
|
|
#define PCI_DEVICE_ID_INTEL_H87 0x8c4a
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|
|
#define PCI_DEVICE_ID_INTEL_HM87 0x8c4b
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|
|
|
#define PCI_DEVICE_ID_INTEL_Q85 0x8c4c
|
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|
|
|
#define PCI_DEVICE_ID_INTEL_Q87 0x8c4e
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|
|
#define PCI_DEVICE_ID_INTEL_QM87 0x8c4f
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_B85 0x8c50
|
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|
|
|
#define PCI_DEVICE_ID_INTEL_C222 0x8c52
|
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|
|
#define PCI_DEVICE_ID_INTEL_C224 0x8c54
|
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|
|
#define PCI_DEVICE_ID_INTEL_C226 0x8c56
|
|
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|
|
#define PCI_DEVICE_ID_INTEL_H81 0x8c5c
|
|
|
|
|
|
2022-10-07 00:18:04 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_C9_MOBILE 0x8cc1
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|
|
#define PCI_DEVICE_ID_INTEL_C9_DESKTOP 0x8cc2
|
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|
|
|
#define PCI_DEVICE_ID_INTEL_HM97 0x8cc3
|
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|
|
#define PCI_DEVICE_ID_INTEL_Z97 0x8cc4
|
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|
|
#define PCI_DEVICE_ID_INTEL_H97 0x8cc6
|
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|
|
|
2012-10-13 02:19:30 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_82X58 0x3405
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
|
2011-10-30 13:30:36 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_I63XX 0x2670
|
2012-01-08 15:27:18 +01:00
|
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|
|
2012-07-05 22:53:57 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_I5000X 0x25c0
|
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|
|
|
#define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_I5000V 0x25d4
|
2012-01-08 15:27:18 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_I5000P 0x25d8
|
|
|
|
|
|
2022-08-17 10:28:20 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_ADL_P 0x5182
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_ADL_M 0x5187
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_RPL_P 0x519d
|
|
|
|
|
|
2022-10-17 14:30:24 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_EHL 0x4b00
|
2023-03-10 19:44:04 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_JSL 0x4d87
|
2022-10-17 14:30:24 +02:00
|
|
|
|
2010-07-29 21:25:31 +02:00
|
|
|
/* untested, but almost identical to D-series */
|
2012-10-13 02:19:30 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
|
2009-09-30 19:05:46 +02:00
|
|
|
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
|
|
|
|
|
/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82443BX 0x7190
|
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|
|
#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
|
|
|
|
|
|
|
|
|
|
/* 82371AB/EB/MB use the same device ID value. */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
|
2008-08-20 15:41:24 +02:00
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|
|
2014-12-08 06:11:54 +01:00
|
|
|
/* Bay Trail */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0f00 /* SOC Transaction Router */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC 0x0f1c
|
|
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|
|
#define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31
|
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|
|
#define CPUID_BAYTRAIL 0x30670
|
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|
|
|
|
2018-11-20 12:10:29 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
|
2019-01-12 19:20:50 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc
|
2021-10-22 10:31:22 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31E8
|
2018-11-20 12:10:29 +01:00
|
|
|
|
2012-10-13 02:19:30 +02:00
|
|
|
/* Intel starts counting these generations with the integration of the DRAM controller */
|
2013-06-20 18:05:06 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
|
2012-10-13 02:19:30 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
|
2014-11-05 03:18:44 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */
|
2014-11-09 00:11:28 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x0150 /* Ivy Bridge (Desktop) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M 0x0154 /* Ivy Bridge (Mobile) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3 0x0158 /* Ivy Bridge (Xeon E3 v2) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c 0x015c /* Ivy Bridge (?) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D 0x0c00 /* Haswell (Desktop) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */
|
2014-10-30 10:30:40 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
|
2015-05-15 04:58:33 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
|
2022-10-07 00:25:33 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D 0x1610 /* Broadwell (Desktop) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M 0x1614 /* Broadwell (Mobile) */
|
2017-10-03 16:03:07 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */
|
2020-03-14 22:39:30 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */
|
2017-10-28 14:45:48 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */
|
2018-01-01 01:48:21 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */
|
2019-08-27 17:20:08 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E 0x2020 /* Skylake-E (Server) */
|
2018-07-24 06:09:47 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */
|
2019-05-06 17:50:57 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */
|
2019-06-12 06:23:46 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1 0x3ed0 /* Coffeelake (Mobile) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2 0x3e34 /* Whiskeylake (Mobile) */
|
2019-12-29 14:31:01 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U 0x8a12 /* Icelake U */
|
2020-08-08 18:17:31 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */
|
2021-07-09 16:00:16 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */
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#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4 0x9a12 /* Tigerlake UP4 4 Cores */
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#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4 0x9a16 /* Tigerlake H 4 Cores */
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#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6 0x9a26 /* Tigerlake H 6 Cores */
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#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8 0x9a36 /* Tigerlake H 8 Cores */
|
2020-10-23 03:40:41 +02:00
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|
|
#define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */
|
2021-05-03 22:12:23 +02:00
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|
#define PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP 0x09a2 /* Sapphire Rapids SP */
|
2022-04-05 10:40:03 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_8 0x4660 /* Alderlake S LGA 8+8 */
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#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_4 0x4668 /* Alderlake S LGA 8+4 */
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#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_6_4 0x4648 /* Alderlake S LGA 6+4 */
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#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_0 0x4670 /* Alderlake S LGA 8+0 */
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#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_6_0 0x4650 /* Alderlake S LGA 6+0 */
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#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_8_8 0x4637 /* Alderlake HX 8+8 */
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|
#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_6_8 0x463B /* Alderlake HX 6+8 */
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#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_4_8 0x4623 /* Alderlake HX 4+8 */
|
2022-08-17 10:28:20 +02:00
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|
#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_6_8 0x4641 /* Alderlake P 6+8 */
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#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_4_8 0x4621 /* Alderlake P 4+8 */
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#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8 0x4601 /* Alderlake P 2+8 */
|
2012-07-21 04:36:47 +02:00
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|
2017-11-07 19:51:21 +01:00
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|
|
/* Intel GPUs */
|
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#define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982
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#define PCI_DEVICE_ID_INTEL_G35_EXPRESS_1 0x2983
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|
#define PCI_DEVICE_ID_INTEL_965_EXPRESS 0x2a02
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|
#define PCI_DEVICE_ID_INTEL_965_EXPRESS_1 0x2a03
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|
#define PCI_DEVICE_ID_INTEL_965_EXPRESS_2 0x2a12
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|
#define PCI_DEVICE_ID_INTEL_965_EXPRESS_3 0x2a13
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|
#define PCI_DEVICE_ID_INTEL_4_SERIES 0x2a42
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|
#define PCI_DEVICE_ID_INTEL_4_SERIES_1 0x2a43
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|
#define PCI_DEVICE_ID_INTEL_G45 0x2e22
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|
|
#define PCI_DEVICE_ID_INTEL_G45_1 0x2e23
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|
#define PCI_DEVICE_ID_INTEL_Q45 0x2e12
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|
#define PCI_DEVICE_ID_INTEL_Q45_1 0x2e13
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|
#define PCI_DEVICE_ID_INTEL_G41 0x2e32
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|
|
#define PCI_DEVICE_ID_INTEL_G41_1 0x2e33
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|
#define PCI_DEVICE_ID_INTEL_B43 0x2e42
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|
|
#define PCI_DEVICE_ID_INTEL_B43_1 0x2e43
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|
#define PCI_DEVICE_ID_INTEL_B43_2 0x2e92
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|
#define PCI_DEVICE_ID_INTEL_B43_3 0x2e93
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|
#define PCI_DEVICE_ID_INTEL_HD_GRAPHICS 0x0046
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|
|
#define PCI_DEVICE_ID_INTEL_HD_GRAPHICS_1 0x0042
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|
#define PCI_DEVICE_ID_INTEL_HD_GRAPHICS_2 0x0106
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|
#define PCI_DEVICE_ID_INTEL_HD_2000 0x0102
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|
|
#define PCI_DEVICE_ID_INTEL_HD_2000_1 0x0106
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|
|
#define PCI_DEVICE_ID_INTEL_HD_3000 0x0116
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|
#define PCI_DEVICE_ID_INTEL_HD_3000_1 0x0112
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|
#define PCI_DEVICE_ID_INTEL_HD_3000_2 0x0116
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|
#define PCI_DEVICE_ID_INTEL_HD_3000_3 0x0122
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|
#define PCI_DEVICE_ID_INTEL_HD_3000_4 0x0126
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|
#define PCI_DEVICE_ID_INTEL_HD_3000_5 0x0116
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|
#define PCI_DEVICE_ID_INTEL_HD_2500 0x0152
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|
|
#define PCI_DEVICE_ID_INTEL_HD_2500_1 0x0156
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|
#define PCI_DEVICE_ID_INTEL_HD_2500_2 0x015A
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|
#define PCI_DEVICE_ID_INTEL_HD_4000 0x0162
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|
|
#define PCI_DEVICE_ID_INTEL_HD_4000_1 0x0166
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|
#define PCI_DEVICE_ID_INTEL_HD_4000_2 0x016A
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|
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|
|
#define PCI_DEVICE_ID_INTEL_HD_4600 0x0412
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_HD_4600_1 0x0416
|
2019-07-26 15:09:18 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_HD_4400 0x041E
|
2022-05-20 08:50:21 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_HD_4400_1 0x0A16
|
2017-11-07 19:51:21 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_HD_5000 0x0422
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_HD_5000_1 0x0426
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|
|
|
#define PCI_DEVICE_ID_INTEL_HD_5000_2 0x042A
|
2019-01-02 14:44:54 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_HD_510 0x1902
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_HD_515 0x191E
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|
|
|
#define PCI_DEVICE_ID_INTEL_HD_520 0x1916
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_HD_530_1 0x191B
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|
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|
|
#define PCI_DEVICE_ID_INTEL_HD_530_2 0x1912
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|
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|
|
#define PCI_DEVICE_ID_INTEL_UHD_615_1 0x591C
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_615_2 0x591E
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_617 0x87C0
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_620_1 0x5917
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_620_2 0x3EA0
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_620_3 0x5916
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_630_1 0x3E92
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_630_2 0x3E9B
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|
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|
|
#define PCI_DEVICE_ID_INTEL_UHD_630_3 0x3E91
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_630_4 0x5912
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_630_5 0x591B
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|
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|
|
#define PCI_DEVICE_ID_INTEL_UHD_630_6 0x5902
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|
#define PCI_DEVICE_ID_INTEL_UHD_630_7 0x3E98
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|
#define PCI_DEVICE_ID_INTEL_UHD_640 0x5926
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|
|
#define PCI_DEVICE_ID_INTEL_IRIS_540 0x1926
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_IRIS_550 0x1927
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|
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|
|
#define PCI_DEVICE_ID_INTEL_IRIS_PRO_580 0x193B
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_650 0x5927
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5
|
2019-12-29 14:31:01 +01:00
|
|
|
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52
|
2020-08-08 18:17:31 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_UHD_GRAPHICS 0x9b41
|
2021-07-09 16:00:16 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0x9A40
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0x9A49
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_TGL_GT1 0x9A60
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70
|
2022-04-05 10:40:03 +02:00
|
|
|
#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_ADL_S_GT1_2 0x4682
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|
|
|
|
#define PCI_DEVICE_ID_INTEL_ADL_S_GT1_3 0x4690
|
|
|
|
|
#define PCI_DEVICE_ID_INTEL_ADL_S_GT1_4 0x4692
|
2017-11-07 19:51:21 +01:00
|
|
|
|
2010-10-24 15:50:13 +02:00
|
|
|
#if !defined(__DARWIN__) && !defined(__FreeBSD__)
|
2008-08-20 15:41:24 +02:00
|
|
|
typedef struct { uint32_t hi, lo; } msr_t;
|
2008-12-04 16:18:20 +01:00
|
|
|
#endif
|
2010-10-24 15:50:13 +02:00
|
|
|
#if defined (__FreeBSD__)
|
|
|
|
|
/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */
|
|
|
|
|
#undef rdmsr
|
|
|
|
|
#undef wrmsr
|
|
|
|
|
#define rdmsr freebsd_rdmsr
|
|
|
|
|
#define wrmsr freebsd_wrmsr
|
|
|
|
|
typedef struct { uint32_t hi, lo; } msr_t;
|
|
|
|
|
#endif
|
2008-08-20 15:41:24 +02:00
|
|
|
typedef struct { uint16_t addr; int size; char *name; } io_register_t;
|
2017-07-24 22:53:26 +02:00
|
|
|
typedef struct {
|
|
|
|
|
uint32_t eax;
|
|
|
|
|
uint32_t ebx;
|
|
|
|
|
uint32_t ecx;
|
|
|
|
|
uint32_t edx;
|
|
|
|
|
} cpuid_result_t;
|
2008-08-20 15:41:24 +02:00
|
|
|
|
2011-03-18 23:08:39 +01:00
|
|
|
void *map_physical(uint64_t phys_addr, size_t len);
|
2009-09-01 11:52:14 +02:00
|
|
|
void unmap_physical(void *virt_addr, size_t len);
|
2008-08-20 15:41:24 +02:00
|
|
|
|
|
|
|
|
unsigned int cpuid(unsigned int op);
|
2019-10-09 17:35:23 +02:00
|
|
|
int print_intel_msrs(unsigned int range_start, unsigned int range_end);
|
2015-10-10 13:20:32 +02:00
|
|
|
int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file);
|
2010-11-27 15:44:19 +01:00
|
|
|
int print_pmbase(struct pci_dev *sb, struct pci_access *pacc);
|
2020-03-13 22:22:26 +01:00
|
|
|
int print_lpc(struct pci_dev *sb, struct pci_access *pacc);
|
2008-08-20 15:41:24 +02:00
|
|
|
int print_rcba(struct pci_dev *sb);
|
2019-07-14 17:04:05 +02:00
|
|
|
void print_iobp(struct pci_dev *sb, volatile uint8_t *rcba);
|
inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.
Here's a preview:
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 15:08:04 +02:00
|
|
|
int print_gpios(struct pci_dev *sb, int show_all, int show_diffs);
|
2020-01-29 10:08:17 +01:00
|
|
|
const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb,
|
|
|
|
|
size_t* community_count,
|
|
|
|
|
size_t* pad_stepping);
|
2017-04-07 12:26:07 +02:00
|
|
|
void print_gpio_groups(struct pci_dev *sb);
|
2008-08-20 15:41:24 +02:00
|
|
|
int print_epbar(struct pci_dev *nb);
|
|
|
|
|
int print_dmibar(struct pci_dev *nb);
|
|
|
|
|
int print_pciexbar(struct pci_dev *nb);
|
2012-01-08 15:27:18 +01:00
|
|
|
int print_ambs(struct pci_dev *nb, struct pci_access *pacc);
|
2015-01-03 02:52:10 +01:00
|
|
|
int print_spi(struct pci_dev *sb);
|
2015-05-20 14:04:41 +02:00
|
|
|
int print_gfx(struct pci_dev *gfx);
|
2016-06-08 16:39:22 +02:00
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int print_ahci(struct pci_dev *ahci);
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2017-07-24 22:53:26 +02:00
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int print_sgx(void);
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2020-09-03 20:28:19 +02:00
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void print_tme(void);
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2022-12-19 18:52:34 +01:00
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void print_keylocker(void);
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2015-10-10 13:20:32 +02:00
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void ivybridge_dump_timings(const char *dump_spd_file);
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2017-04-05 17:39:57 +02:00
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#endif
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