Add support for automatic extraction of the Second Logical Boot
Partition from the supplied IFWI binary.
Change-Id: Ia2a9ca233bddb8e9fb4e980f0ae5e6fcf3fc757c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37681
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The base address of the 16 MB flash range was reported as 0xFFF00000
this causes the range to extend above the 4GB boundary.
Change the base to 0xFF000000 as is the case with e.g. Skylake.
BUG=N/A
TEST=build
Change-Id: Ia8de01769ced00c5ae13f255760401933230b88c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not
enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized),
which indicates the TEVT method is empty.
The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses
this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT.
The TEVT method will be removed from the ASL code when the EC does not support TEVT.
BUG=N/A
TEST=Tested on facebook monolith.
Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This impacts boards:
hatch (&variants) and drallion.
Some variants like Puff can have up to 12 cores. coreboot should take
the min() where MAX_CPU is the upper bound.
Further to that, boards themseleves shouldn't be setting the MAX_CPUS,
the chipset should be and so do that.
BRANCH=none
BUG=b:146255011
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I284d027886f662ebb8414ea92540916ed19bc797
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
We had to role the `fsp` submodule back for a minute due to a regression
with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into
the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and
heap usage partitioned for FSP using coreboot's stack (config FSP_USES_
CB_STACK), it works again.
To make this even messier: We already selected this Kconfig option for
Whiskey Lake, which is supposed to use the very same FSP binary. So with
either submodule pointer, something was always broken :-/
Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Update PMC shadow register base address for Jasperlake
Correct PCH detection logic based on PCH ids and return correct base
address based on PCH detected since our code supports both tgl and jsl.
Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This reverts commit 0178760867.
AMD: Dropping the _HID of PCI root bus doesn't work well and people
started to notice the breakage.
Intel: These platforms have a devicetree switch to choose between PCI
and ACPI modes. In the former case we need _ADR, but in the latter _HID
as the PCI devices are hidden.
The conflicting use of _ADR and _HID still needs to be fixed before
we can bump our IASL version.
Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The split of bootblock initialisation to cpu, northbridge and
southbridge is not specific to intel at all, create new header
<arch/bootblock.h> as AMD will want some of these too.
Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
gpe0_en_* seem to have been copied over from previous generations but
recent SoCs don't use it. This change gets rid of these unused
members.
Change-Id: I165e66aeefde4efea4484f588c774795987ca461
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to the POSIX standard, %p is supposed to print a pointer "as
if by %#x", meaning the "0x" prefix should automatically be prepended.
All other implementations out there (glibc, Linux, even libpayload) do
this, so we should make coreboot match. This patch changes vtxprintf()
accordingly and removes any explicit instances of "0x%p" from existing
format strings.
How to handle zero padding is less clear: the official POSIX definition
above technically says there should be no automatic zero padding, but in
practice most other implementations seem to do it and I assume most
programmers would prefer it. The way chosen here is to always zero-pad
to 32 bits, even on a 64-bit system. The rationale for this is that even
on 64-bit systems, coreboot always avoids using any memory above 4GB for
itself, so in practice all pointers should fit in that range and padding
everything to 64 bits would just hurt readability. Padding it this way
also helps pointers that do exceed 4GB (e.g. prints from MMU config on
some arm64 systems) stand out better from the others.
Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Include soc common lpss header file to resolve build error due to
missing soc_lpss_controllers_list declaration.
Also remove console header since it is unused.
Change-Id: I2b2c82fc7592120993bc483d3061803cf75c7335
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37556
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The name for the CoffeeLake FSP.fd was changed to Fsp.fd.
Therefore the CoffeLake / WhiskeyLake default path was
changed.
Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37564
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On embedded boards the cpu mounted on the board is known. So it is not
required to include microcode for all possible Sky Lake and Kaby Lake
cpus. This patch provides the possibility to only support the versions
required.
By default all microcode updates will be included and the versions not
required can be removed using Kconfig.
BUG=N/A
TEST=build
Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This patch performs below operations:
1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration
2. Move soc_gpio_pm_configuration() to gpio_common.c
3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration
is updated with devicetree.cb value even with platform reset.
BUG=b:144002424
TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb
Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add gfx.asl file for cannonlake SOCs to allow for graphics-related ACPI
devices and methods on cannonlake devices.
BUG=b:142237145
TEST=gfx.asl added to drallion dsdt.asl
Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This change allows for Intel graphics devices to use drivers/generic/gfx
driver to populate ACPI SSDT table for common graphics related devices
and methods.
BUG=b:142237145
TEST=On sarien_cml add generic/gfx to the devicetree and device is
enumerated and correct SSDT ASL is observed.
Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
since we support JSL and TGL soc under tigerlake folder, we need to make
sure all soc related files get compiled based on
CONFIG_SOC_INTEL_TIGERLAKE_BASE and not only for Tigerlake.
We can control soc specific file compilation through Kconfig of
individual soc.
Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
These were often used to distinguish CAR_GLOBAL variables that weren't
directly usable. Since we're getting rid of this special case, also get
rid of the marker.
This change was created using coccinelle and the following script:
@match@
type T;
identifier old =~ "^(g_.*|.*_g)$";
@@
old
@script:python global_marker@
old << match.old;
new;
@@
new = old
if old[0:2] == "g_":
new = new[2:]
if new[-2:] == "_g":
new = new[:-2]
coccinelle.new = new
@@
identifier match.old, global_marker.new;
@@
- old
+ new
@@
type T;
identifier match.old, global_marker.new;
@@
- T old;
+ T new;
@@
type T;
identifier match.old, global_marker.new;
@@
- T old
+ T new
= ...;
There were some manual fixups: Some code still uses the global/local
variable naming scheme, so keep g_* there, and some variable names
weren't completely rewritten.
Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: Ifb777c09aeef09a6a4cbee254b081519f5b6c457
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This moves programming BAR's and setting up console in the bootblock.
Change-Id: I062461cb7bfba2c4df4c20707ecda32f9857b164
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36873
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the common southbridge SPI code reinitialization after lockdown
is not necessary, hence the SMM finalize call becomes a no-op.
Change-Id: I9fae28185470f4d25ef1818627eb76ac38cf100b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36006
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This common implementation is compatible.
Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since we accomodate both Tigerlake and Jasperlake soc in single folder,
we need to select IFD chipset correctly based on soc.
Change-Id: I73cfe4f583da3a28c3b29d29a93ff62097130e27
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Change PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS to PCI_DEVICE_ID_INTEL_LWB_SMBUS.
Ideally the abbreviation for Lewisburg should be LBG instead of LWB.
However, LWB is used for consistency.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Anjaneya (Reddy) Chagam <anjaneya.chagam@intel.com>
Change-Id: Ibc0cb6f2f7eb337180c2ae89015953a9aeaed68b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37215
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP-T support was abandoned long ago for Skylake. With FSP1.1 support
also dropped now, it's more visible that this code is unused.
Change-Id: I83a9130ef403b498e2beea01749c178e547b0f08
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37251
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes below clean-up for report_cpu_info()
function.
1. Remove unused variables.
2. Make fill_processor_name function available in bootblock.
3. Reuse fill_processor_name.
TEST= Succesfully able to boot soraka and verify the
cpu_name "CPU: Intel(R) Pentium(R) CPU 4415Y @ 1.60GHz"
Change-Id: Idf7b04edc3fce147f7856591ce7e5a0cd05f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36840
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Workaround to disable USB2 PHY power gating to fix issue seen when
Apple 87W USB-C charger is connected in S0ix state on WHL platforms
(based on Intel's recommendation). Issue is seen on CML platforms also.
So, disable power gating for Drallion too.
Add devicetree entry to set the flag to disable USB2 PHY power gating
for different CNL PCH based platforms
BUG=b:133775942
TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if
the system wakes up after that
Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com>
Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Platform is not yet build-tested, this should have gone in
with commit f5c0d61 intel/smm: Provide common smm_relocation_params.
Change-Id: Iba667972e361d3ed463258357ab6bbde26ef1e06
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With the common southbridge SPI code reinitialization after lockdown
is not necessary, hence the SMM finalize call becomes a no-op.
Change-Id: Ie73a0adc120731d541a772e09f3482902771b9eb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36008
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do it in coreboot code instead of letting FSP do it.
Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.
FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.
Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.
Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and
CONFIG_CPU_MICROCODE_CBFS_LEN
Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides options to override descriptor default CPU flex
ratio from coreboot code. cpu_ratio_override to provide the required CPU
ratio.
Note: Don't override the flex ratio if cpu_ratio is 0.
BUG=b:142264107
TEST=Without override flex_ratio is 0 and verified booting to
OS after overriding with flex_ratio value 5.
Change-Id: Ib01650f52f3d402f669e7e7f5b28a648b86f08ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The mechanism for getting the SPIBAR is little different.
Tested on Intel Minnowboard Turbot.
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add Kconfig option for Jasperlake soc and make tigerlake as a base soc.
This will allow us to differentiate between soc features.
Change-Id: Id5001dc498a7d7d5c7903dc3a3762da740fc9c8e
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
The romcc bootblock will be deprecated soon and most platforms use
C_ENVIRONMENT_BOOTBLOCK already. This patch drops the
CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK
where needed.
Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
