Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.
Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x.
Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/618
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If both FSBs on i5000 are equipped with CPU packages, one CPU
from each package is elected as BSP. To prevent races between
both BSPs, hlt the second BSP.
Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/615
Tested-by: build bot (Jenkins)
If serial uart (8250/16x50) takes abnormally long to respond, give
up on logging to serial console and instead let the system boot.
Also reference bit in LSR register with correct name.
Change-Id: I3796efc3e8690425f04a130af4bc99541b64d335
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/611
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Driver components are conditionally included in the build using the
Kconfig options.
Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/610
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If multiple VGA-compatible legacy graphic cards decode the IO range
3B0-3BB, 3C0-3DF and MEM range A00000-BFFFF.
Windows 7 complain a resource conflict, so only one VGA card can
works at the same time.
There is a discussion in coreboot mail list before,
please reference thread: "how to prevent legacy resource conflictwith multipleVGA cards"
http://www.coreboot.org/pipermail/coreboot/2010-October/061508.html
Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict,
Please see the following linux dmesg log, more information can be found in
Linux source dir Documentation/vgaarbiter.txt.
But it seems that windows don't dealwith this conflict.
~# dmesg | grep -i vgaarb
[ 0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem
[ 0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l
[ 0.780051] vgaarb: loaded
[ 0.784049] vgaarb: bridge control possible 0000:01:00.0
[ 0.788050] vgaarb: bridge control possible 0000:00:01.0
For the second legacy graphic device, coreboot already disabled the
IO and MEM decode in function set_vga_bridge_bits().
But it will be enabled again in function pci_set_resource(),
if the second legacy vga-compatible graphic device take any IO/MEM resources.
Following log printed by enable_resources() shows the problem:
...snip...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 subsystem <- 1022/1410
PCI: 00:01.0 cmd <- 07 <== The first graphic device
PCI: 00:01.1 subsystem <- 1022/1410
PCI: 00:01.1 cmd <- 02
PCI: 00:02.0 bridge ctrl <- 0003
PCI: 00:02.0 cmd <- 07
...snip...
PCI: 01:00.0 cmd <- 03 <== The second graphic device
PCI: 01:00.1 cmd <- 02
PCI: 02:00.0 cmd <- 02
PCI: 03:00.0 cmd <- 03
done.
...snip...
The IO & MEM decoding on the second vga graphic device should be disabled.
Please reference PCI spec. section 3.10 in detail.
set_vga_bridge_bits() would do this work for us, it did the right thing,
but was put to the wrong place, the setting would be overwritten by
assign_resources() later.
In order to make sure the set_vga_bridge_bits() setting not be
overwritten by others, moving the call of set_vga_bridge_bits()
to the end of dev_configure(), instead of at the beginning.
This patch resolved the dual graphic cards resource conflict in windows7,
multiple vga-compatible graphic cards can work together in windows7.
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d
Reviewed-on: http://review.coreboot.org/489
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Pcie device connected to Hudson/sb800 southbridge GPP training can works,
by applying this mainbaind specific GPIO PCIE De-Assert setting.
Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/543
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Make sure SeaBIOS build files live under $(OUT) instead of
in the source tree.
Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/552
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This allows to add a PCI ID mapping function for option roms so that the same
option rom can be used for a series of devices / PCI IDs. Intel and AMD often
use the same option rom for a number of PCI devices with differend IDs.
A function to implement such a mapping could look like this (or anything else
appropriate):
/* some vga option roms are used for several chipsets but they only have one
* PCI ID in their header. If we encounter such an option rom, we need to do
* the mapping ourselfes
*/
u32 map_oprom_vendev(u32 vendev)
{
u32 new_vendev=vendev;
switch(vendev) {
case 0xa0118086:
new_vendev=0xa0018086;
break;
}
return new_vendev;
}
Change-Id: I1be7fe113b895075d43ea48fe706b039cef136d2
Reviewed-on: http://review.coreboot.org/573
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
Persimmom update a lot in the last few month, sync these modification to inagua.
Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/542
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
without it, you can't boot from PCI devices like scsi controllers
which require an interrupt set. So preconfigure all pci devices.
Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/603
Tested-by: build bot (Jenkins)
BIOS needs to set the bit mask which ports are iplemented on the
board. Without setting this option, seabios fails to boot from
SATA.
Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/601
Tested-by: build bot (Jenkins)
i3100 misses the magic SATA init sequence, which makes all
requests fail. Captured from the vendor BIOS, which writes
those bits on all configurations.
Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/600
Tested-by: build bot (Jenkins)
CPUs with CPUID level >= 0x80000008 can return
the number of physical address bits.
Change-Id: I1c0523b6a091c476af838d173ed9030280360d7f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/599
Tested-by: build bot (Jenkins)
Fix ordering of power/reset/undock procedure to prevent
crashes seen with the old code. Also call dlpc_init()
only once.
Change-Id: I27d1f42e845fcccde40e6ca5af4a7762edab5d36
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/597
Tested-by: build bot (Jenkins)
This makes resume from S3 work.
Change-Id: I472baf2fbde46bfac223ce39fc81b8e09849fb7f
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/591
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Originally brought up by Sven Schnelle in March 2011
http://patchwork.coreboot.org/patch/2801/http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html
On some mainboards it may be neccessary to reset early during resume
from S3 if the SLFRCS register indicates that a memory channel is not
guaranteed to be in self-refresh.
On other mainboards, such as Lenovo X60 and T60, the check always
creates false positives, effectively making it impossible to resume.
The SLFRCS register is documented on page 197 of
Mobile Intel® 945 Express Chipset Family Datasheet
Document Number: 309219-006
which is publically available, and the register indicates if a memory
channel is guaranteed to be in self-refresh mode (if bit = 1), or that
a memory channel *may or may not be* in self-refresh mode (if bit = 0).
The register can thus only be used to positively learn that memory is
in self-refresh. It is not known for sure that memory is *not* in
self-refresh. The register is reset by the PWROK signal, which *should*
go low during S3, and go high again when resuming, so it is unsurprising
that SLFRCS has already been cleared when we read the register.
Sven's measurements of the CKE signal on a ThinkPad shows that memory
remains in self-refresh indefinitely, until coreboot re-initializes the
memory controller, even when SLFRCS bits were = 0.
Boards which require a warm reset when SLFRCS bits are cleared must now
explicitly enable the check in the mainboard Kconfig file.
This commit selects the new option in all existing i945 mainboards.
A follow-up commit will remove the option for ThinkPads.
Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/590
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Value required to get 115200 is actually 0, not 5.
Change-Id: Id1385822bf2213c035c4f378a72168ed6676ad03
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/592
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Coming changes to abuild require that VENDOR_ and BOARD_ names have
common suffixes.
Change-Id: I44cf759dd3b2d02c525eb325dc9c5c989f172ac5
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/548
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Moved the conditional compilation out of the source file
Change-Id: Ic4045006f39d70f4a0bc37d1bd5e073ed8477c68
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/578
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Make changes MPtable to match ACPI tables.
Change-Id: I387f301370582fcb5e0d348d793333a919d2f373
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/575
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix the ACPI IRQ routing. Also. fix the SSDT generations and TOM2 fixup.
Change-Id: I03e6de7bb58440058306c9c9888eb2961748c385
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/574
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Added a macro in the post code list, which replaces hard coded
value in cpu/x86/cache/cache.c
Change-Id: I27cb27827272584a8a17a41c111e2dc155196a97
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/572
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to use SSE+MMX optimized payloads we don't want to disable SSE+MMX
instructions in the CPU after romstage.
Change-Id: I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/553
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This cleans up the strings in romstage.c, removing the ugly "got past".
Also, cleaned up comments and some spacing.
Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/539
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Id34615f0c229d276d72cdf984cf82ea8cc1a85bb
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/523
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This line was unnecessary and was duplicated on several mainboards.
Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/541
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The #define REQUIRED_CALLOUTS is no longer used on these platforms.
Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/540
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There was no good way to extract the build version from an image.
This change will be mostly backward compatible: The only assumption
that could break is that the board name string ends directly before
the 3 dwords that represent .id's "header".
Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/537
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
We used to put the id section at -0x10, with some boards overriding
this to avoid collisions with romstraps.
Hardcode the location at -0x80, at the possible expense of some space
(0x70 bytes).
This also makes the section easier to find in a binary image.
At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
is moved to src/Kconfig.deprecated_options.
Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/549
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The current implementation calls die() if memory checking fails.
This isn't always what we want: one might want to print error registers,
or do some other error handling. Introduce ram_check_nodie() for that
reason. It returns 0 if ram check succeeded, otherwise 1.
Change-Id: Ib9a9279120755cf63b5b3ba5e0646492c3c29ac2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/532
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
When CONFIG_EXPERT is set, compilation fails with:
src/superio/winbond/w83627hf/superio.c:61:13: error: ‘w83627hf_16_bit_addr_qual’ defined but not used [-Werror=unused-function]
cc1: all warnings being treated as errors
This function isn't used in the code, so just remove it.
Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/533
Tested-by: build bot (Jenkins)
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.
Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The comparision is the wrong way round: as long as tsc
is below tsc1, the timeout is not reached
Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/530
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Change-Id: If681a33deb7df752b37c6a8a20482d3c374af936
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Philip Prindeville <philipp@redfish-solutions.com>
This function prevents the linker from choosing the right
get_cst_entries(), preventing writing the _CST tables.
Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/496
Tested-by: build bot (Jenkins)
Adds a missing return statment which will stop misleading the users
Change-Id: I53741f1136b396e9493ce959b54efc00c9b09764
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/522
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Fixed indentation using indent tool in the src/drivers/i2c tree
Change-Id: I5b396e5753544aff13ac5d16afc59e193a6b1da1
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/506
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The AGESA wrapper init late call generates the SSDT and other ACPI tables. The
call was failing without heap space allocated causing the ASSERT messages in
the output. I think are there may still be other issues in integrating the
SSDT table with the DSDT, but now it is there to debug.
The changes were made in Persimmon and copied to the other Fam14 mainboards.
Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/517
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
fixes some ACPI errors in Linux and Windows bluescreens.
The Persimmon acpi_tables.c is where the main changes were made and then
replicated in the other Fam14 boards. Please test the other mainbords if you
have one.
Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/516
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
changes
Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/515
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add interrupt routing for APU GNB internal Graphic and HD audio device, and
other pcie bridge device in GNB.
south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.
Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/452
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
I misunderstood how kconfig select works. It needs to be selected with a config option. Moved the select to the correct location.
Change-Id: If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/487
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
CMOS accesses are not safe for multi-processor and only the BSP CPU
should count reboots and test CMOS sanity.
A questionable single byte CMOS read access from AP CPUs remains.
AP CPUs should always select the same romstage prefix as BSP CPU.
Change-Id: I29118e33c07c0080c94abb90f703e38312c72432
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/446
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Enable HD audio over HDMI.
Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed.
Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/450
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Added the default ID to the mainboard Kconfig.
Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/488
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Some keyboards take pretty long to respond to a reset command, some even
delay the ACK to the command. To make the keyboard driver more robust,
increase the timeout for this special command. Also do an interface test
after the self-test to ensure the keyboard is functioning properly.
Another point is to reenable the keyboard *after* the scancode was set,
not before. We also set the system bit when enabling the keyboard
because this seems to be what older operating systems do expect.
One of the problematic keyboards, which will work with this patch
applied, is the DELL RT7D20. Without the patch an overly optimistic
operating system, read Linux 2.4, will not recognise the keyboard
because coreboot didn't fully initialize it.
Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/486
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
data is not required for mainboards that use G-Series HDMI. It is also a setting
the may be boards specific. This fixes issues with Windows audio on Persimmon.
Change-Id: I067506871e92078d122cf79872363d8937d47e50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/490
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EC allows to select the order in which batteries are (dis)charged.
Make this setting available to the user.
Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/475
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Checking RBIL, int10 AH=0x10 does never output a character.
The two output functions are AH=0x09 and AH=0x0e.
Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/483
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols,
which fail without an option table (as no option_table.h defines them).
Discard them by using a macro instead of a static inline function.
Change-Id: I8d001f971681277a344b6788725746491546b607
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/442
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This fixes problems in AP init when multiple APs are trying to access
PCI config space. All Fam10 CPUs setup and support MMCONF.
Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/455
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change the DSDT Table ID for M4A785T-M
from M4A785-M to M4A785T-M.
This fixes a small copypasta.
This is an updated patch set.
Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Allocation size for the section was miscalculated, so the section
did not honour its upper-bound address.
Also align the section start to 4 bytes, so it starts with code
instead of pad bytes.
Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/453
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Untested, changes ramstage build for boards:
supermicro/h8qme_fam10
amd/serengeti_cheetah
amd/serengeti_cheetah_fam10
AMD 8132 was not built for any mainboard due to a typo.
AMD Serengeti Cheetah:
Chip 8151 is referenced in devicetree.cb but was not built.
AMD Serengeti Cheetah Family10:
There are indications the board has 8151, but it is not listed
in the devicetree.cb. The 8151 chip is not added in the build.
Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/471
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Detection of a CPU being a BSP CPU is not dependent of the existence
of northbridge and/or southbridge init code in the bootblock.
Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
CPU of a hyper-threading CPU and needs to return actual BSP bit from
MSR.
Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/447
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This pulls it all together and adds the real board-specific code.
Confirmed to be working:
- IDE
- SATA
- floppy
- USB1.1
- USB2.0
- PS/2 keyboard
- PS/2 mouse
- serial
- parport
- sound
- ethernet
- PCI slots
- AGP
- powernow
- fan speed monitoring
- flashrom write
Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/390
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
Fix the DIMM mappings, channel 0 is "B" on board,
and secondary channel is on 0x51,0x53
Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/449
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kerry Sheh