update telemetry value with the SDLE test result.
BUG=b:158964769
BRANCH=none
TEST=emerge-zork coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ic419ca5ca00e4e8602dbc12212a8a63ed3657e02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move interrupt status and wake status clearing to after GPIO config so
that configuration does not incorrectly set interrupt or wake status.
i.e. when PULL_UP is configured on a pad, it incorrectly sets in the
interrupt status bit. Thus, the interrupt status bit must be cleared
after initial pad configuration is complete.
BUG=b:164892883, b:165342107
TEST=None
BRANCH=None
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: If4a5db4bfa6a2ee9827f38e9595f487a4dcfac2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Each variant WiFi SAR CBFS will be added with the default name
"wifi_sar_defaults.hex".
so we just need to look up the default CBFS file as the WiFi SAR
source.
BUG=b:159304570
BRANCH=zork
TEST=1. cros-workon-zork start coreboot-private-files-zork
2. emerge-zork chromeos-config coreboot-private-files-zork \
coreboot chromeos-bootimage
Change-Id: Idf859c7bdeb1f41b5144663ba1762e560dcfc789
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Jasper Lake SoC had PCI root port mapping swap, thats why we were
using swapped mapping earlier for all the boards
Recently, patch was pushed to handle this swap in PCI enumeration code
for Jasper Lake and we need to correct this mapping. Now this mapping
aligns with actual port mapping in the schematics
BUG=None
BRANCH=None
TEST=NVMe and WLAN are getting detected after this changes
Change-Id: Ide5f8419a15f559cefeb6039f155fabf97c279f8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
pmc_set_acpi_mode will set EC SMI mask to 1 in the end.
However google_chromeec_events_init will clear EC SMI mask.
If google_chromeec_events_init is ran after pmc_set_acpi_mode, the EC SMI mask
will be 0 in depthcharge and causes lidclose function not working.
So, pmc_set_acpi_mode() should run after google_chromeec_events_init.
This code is mainly from CB:42677
BUG=b:16338215
TEST=Close lid in depthcharge and the dut can be shutdown on waddledoo.
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I0f06e8b5da00eb05a34a6ce1de6d713005211c08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Configure gpio settings for FPMCU on Halvor.
BUG=b:153680359
TEST=After flash FP MCU FW, during bootup we see spi id spi-PRP0001:01 in dmesg.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5503cfe0fb9933e98ed01afeef8cad1345593ac6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44575
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Halvor uses TBT 0/1/2 for USB type C. We doesn't use PCIE/USB3 port
therefore disable PCIE/USB3 ports and enable TBT 2.
Follow volteer to set USB2 OC_SKIP.
BUG=b:165175296
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifb844ce475f3d58f0c95be0f172fc49edb4cd5fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Create areas for console & timestamp data in psp_verstage and pass it to
the x86 to save for use later.
BUG=b:159220781
TEST=Build & Boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I41c8d7a1565e761187e941d7d6021805a9744d06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
- FSP enables IPU (Imaging Processing Unit) by default even if its
disabled in devicetree. We need to fill FSP upd based on the device
enablement in devicetree.
- Enable Vtd IPU and IGD settings only if respective IPs are enabled.
BUG=165340186
BRANCH=None
TEST=IPU is disabled and doesn't show in lspci.
Change-Id: Ieff57fb0ebc8522546d6b34da6ca2f2f845bf61d
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44627
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_D16 is routed to the main power enable pin on several PCIe SD card
controllers on SD daughterboards. We should enable the power to these
chips as early as possible so they can participate in PCIe
enumeration.
BUG=b:162722965
TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and
can read SD cards.
Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
JSL FSP support FSP 2.2. FSP 2.2 introduces Multiphase SI init
support through the FSP-S arch UPD. The FSP-S arch UPD structure
is added in edk2 stable 2020 branch. Switching the support for
JSL to edk2-stable202005 to intercept the FSP2.2 related support.
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: Ieed1b58e491d5a89043c418f0f44f2ee9af111f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44576
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move a size of DDR3 SPD memory (always 256 bytes) to a common define.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events
and multi-phase silicon initialization.
For backward compatibility the original structures are kept and
new ARCH_UPD structures will be included only when UPD header
revision equal or greater than 2.
ref:
- https://bugzilla.tianocore.org/show_bug.cgi?id=2781
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I728aff1df3d361e21e4617647c4ec0e2d345a8c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Add charger input current throttling for drawcia system
BUG=None
BRANCH=None
TEST=Built and tested on drawcia system
Change-Id: I34fdc23fcd84b5c27c2bada769f7a9049c2a56a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This field eventually gets interpreted as MT/s by SMBIOS instead of MHz. Translate from Mhz to MT/s by multiplying by 2.
BUG=b:154654737
TEST=dmidecode -t 17 matches expected speed
Change-Id: I51b58cb0380f2a2bf000347395ac918ac0717060
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add downgrade support for CSE RW firmware.
When CSE FW is downgraded, CSE may get into data compatibility issues.
To avoid such issues, coreboot sends DATA CLEAR HECI command to CSE to
clear CSE run time data on proactive basis during a downgrade and
when CSE indicates a data mismatch error through GET_BOOT_PARTITION_INFO.
BUG=b:144894771
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I0a3a3036e448e5a743398f6b27e8e62965dbff3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40561
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix compilation under x86_64.
Tested on HP Z220:
* Still boots on x86_32.
Change-Id: I2a3ac3e44a77792eabb6843673fc6d2e14fda846
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The code can only be compiled as x86_32. Mark it as such to fix errors
in the x86_64 assembler. The caller has to make sure to call this code
in protected mode only.
Tested on HP Z220:
* Still boots on x86_32.
Change-Id: I4c0221fb3886b586c22fe05e36109fcdc20b7eed
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enter long mode on secondary APs.
Tested on Lenovo T410 with additional x86_64 patches.
Tested on HP Z220 with additional x86_64 patches.
Still boots on x86_32.
Change-Id: I916dd8482d56c7509af9ad0d3b9c28bdc48fd0b1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The zork devices use the ACP (audio co-processor) and the I2S interface
for audio and not the HDA (HD audio) device and interface.
BUG=b:158535201,b:162302028
BRANCH=zork
TEST=Equivalent change on Mandolin disabled the non-GPU HDA device with
the corresponding FSP change applied.
Change-Id: I6c7de881cff8398fe416151fab219142d4fc904a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP has recently added support for a UPD switch to disable the non-GPU
HD Audio controller. This change adds the coreboot side of the feature.
To avoid having two HD Audio enable options, the value of the
hd_audio_enable UPD is determined by the enable state of the non-GPU HD
Audio controller in the platform devicetree.
BUG=b:158535201,b:162302028
BRANCH=zork
TEST=With the corresponding FSP change applied the non-GPU HD Audio
device is hidden when switched off in devicetree and remains present and
functional when switched on in devicetree.
Change-Id: Ib2965e0742f4148e42a44ddad8ee05f0c4c7237e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44680
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 65605276a4.
This patch shouldn't have been merged yet, since the issues on the FSP
side aren't sorted out yet, so the FSP-side changes haven't landed yet.
This byte will be used for an audio-related setting instead to have the
audio settings grouped together.
BRANCH=zork
Change-Id: If79900f3a92fd949d7653001e1ca2faac7061e3c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44678
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Puff uses CSE Lite SKU that supports in-field CSME
updates an additional reset is triggered when jmp from RO
to RW during boot. However this reset is not detected by
the cr50 running older firmware because the strapping
configuration for EFS2 uses PLT_RST_L to assert to cr50
that a AP reset occured. The older cr50 firmware
version of 0.0.22 only monitors AP resets via SYS_RESET_L
and hence never detects the reset.
To mitigate the issue above a modified reset sequence is
required to be performed to signal the reset occured and
hence a board-specific cse_board_reset() strong symbol is
provided to modify the flow accordingly.
V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common
implementation instead of a local variant in mainboard.c
BUG=b:162290856
BRANCH=puff
TEST=none
Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44454
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will ensure that the cold reset is performed when CSE Lite jumps
from RO to RW.
BUG=b:162386991
TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is
triggered when cr50 is running firmware versions newer than 0.0.22. On
cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I46a390c71e380328cd7fe70214df09553b2db75c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When CSE Lite jumps from RO to RW, certain boards need to request
Embedded Controller (EC) to trigger cold reset of SoC. This change
introduces a helper to override the default global reset.
BUG=None
TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is
triggered when cr50 is running firmware versions newer than 0.0.22. On
cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Introduce a helper to get the cached cr50 firmware version. This
information is in turn used to identify the strap configuration
supported by Cr50.
BUG=None
TEST=Ensure that Drawcia board boots to OS. Ensure that the version
cached cr50 firmware version is returned.
Change-Id: Id84b152993f253878a6c133cc433a0da2c990cf2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44653
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make GPIO_4 and GPIO_5 PAD_NC in ezkinil/gpio.c. None of the Ezkinil SKUs
use internal stylus and hence pen pads are configured as NC.
BUG=b:164892883, b:165342107
TEST=Verified taht pen detect GPIO does not cause spurious wakes.
BRANCH=None
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I7557575cf8b8e0f849e05bda1d69acf61e91a157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44629
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the IT8728F datasheet it is possible to add an extra delay
between 3VSBSW# being set and PWRGD3 being set during resume from
Suspend-to-RAM. This is enabled in the special function selection
register, the default being 0.
This is also useful for the IT8720F although this chip does not have the
PWRGD3 output. On the corresponding pin it has PWROK2, which the setting
then seems to apply to.
The datasheet for the IT8720F marks the corresponding bit as reserved,
but the vendor BIOS of an Acer Aspire M3800 sets it anyway. Without
setting the bit, coreboot fails to resume from S3. Oscilloscope
measurements have shown that setting the bit increases the delay between
3VSBSW# being set and PWROK2 being set from around 1 us to 140 ms. The
actual use of PWROK2 on the board design is unclear - the only
destination it seems to reach is a pin header near the SuperIO marked as
"GPIO1".
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I51cbf2470dc2b840a647a20090acb5a0cf4f4025
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The assumption was that the fmap cache would be initialized in
bootblock, otherwise an error is shown. This error is showing
up in psp_verstage when the fmap cache is initialized there, so
create a new ENV value for ENV_INITIAL_STAGE.
BUG=None
TEST=Boot, see that error message is gone from psp_verstage
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I142f2092ade7b4327780d423d121728bfbdab247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43488
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When booting from the RO region of a VBOOT enabled ROM, there shouldn't
be a reliance on anything outside of the RO section. This includes the
APOB_NV region (similar to the MRC cache region). By skipping the
region when setting up the BIOS Directory table, the PSP won't try to
use the region when booting.
The APOB_NV region is still used for the VBOOT RW sections.
BUG=b:158363448
TEST=Build RO with no APOB_NV region. Dump the BDT and verify that
it's not in RO, but is in RW_A & RW_B. Boot into recovery.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I13c35ba8a2331492744d2acf257db15e4a53102a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide
full range backlight settings to the kernel.
BUG=b:163583825
Change-Id: I3c337fad38e668488800f4d6bc583a82a93659d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Linux kenerl driver for AMD gpu currently has a floor
value of 12 for brightness settings (AMDGPU_DM_DEFAULT_MIN_BACKLIGHT).
AMD indicates they did this because they were concerned with certain
panels flickering at lower backlight values. However, for unaffected
panels it's desirable to be able to have the panel "turn off" at
the lowest backlight setting. The only way to do that is to provide
ATIF bindings that indicate backlight range.
Option SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF is added to provide a full
range for the backlight setting. If needed, this path can be built upon
for fuller support, but for the time being this is the only thing
necessary to make the backlight be full range.
BUG=b:163583825
Change-Id: If76801a8daf6a5e56ba7d118956f3ebce74e567a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GDT loading did work fine on x86_64 a few months ago, but today it
only works in QEMU, but not on real hardware or KVM-enabled QEMU. This
might be related to toolchain changes.
Use 64bit GDT loading on x86_64 and force the assembler to generate a
64bit address load on the GDT. This will make sure no 32bit (signed)
displacement op is being generated, which points to the wrong address
in longmode.
Verified using readelf and made sure no R_X86_64_32S relocation symbol
is emitted. Disassembled the romstage ELF and made sure the GDT address
is 64bit in size.
Tested on QEMU and KVM-enabled QEMU: Doesn't crash any more on KVM.
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Change-Id: Ia824f90d9611e6e8db09bd62a05e6f990581f09a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Convert raw GPIOs to coreboot macros using newly-added support
for Cannon/Whiskey/Coffee/Cometlake SoCs to intelp2m
Test: build/boot Librem Mini, no smoke released.
Change-Id: I6ac747ad4e650c24d2b7e34228ff74140c51a0c1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
IPU is required to be enabled for platform supporting MIPI camera.
IPU is by default disabled in devicetree for all variants. Enable
IPU for Waddledoo and Waddledee supporting MIPI camera.
BUG=None
BRANCH=None
TEST=IPU is enabled for platforms and enumerates in lspci.
Change-Id: Ia3cf06d78be4301c68bfa8b1118ddff231d24a66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44271
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mitigate issues presented in "Digging Into The Core of Boot" found by
"Yuriy Bulygin" and "Oleksandr Bazhaniuk" at RECON-MTL-2017.
Validate user-provided pointers using the newly-added functions.
This protects SMM from ring0 attacks.
Change-Id: I8a347ccdd20816924bf1bceb3b24bf7b22309312
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code
running in verstage, which will program a new Cr50 register, to
have Cr50 generate longer than default interrupt pulses.
This needs to be selected on all Tiger Lake systems, since Tiger Lake
(and likely future Intel SoCs) require at least 100us interrupt pulses.
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137
Change-Id: I20100d72ce426203943c1788d538bb2cd9d82e11
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Compiler's instrumentation cannot insert asan memory checks in
case of memory functions like memset, memcpy and memmove as they
are written in assembly.
So, we need to manually check the memory state before performing
each of these operations to ensure that ASan is triggered in case
of bad access.
Change-Id: I2030437636c77aea7cccda8efe050df4b77c15c7
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable ASan in romstage as it has been tested.
Change-Id: I3b5263f5342a78968d9a1ecf72996fff0946b204
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable ASan in romstage for apollolake as it has been tested on
Siemens MC-APL3.
Change-Id: I2f2f965151a4ef4672f2f16979a6ad8492879aeb
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable ASan in romstage for haswell as it has been tested on
Lenovo ThinkPad T440P.
Change-Id: I6eae242c71f41c9159658ae68d61b4036ad42d42
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable ASan in ramstage if ASAN is selected in menuconfig for an
x86 platform.
Change-Id: Id5b3dc18368a5da6bdc70c84527b95d1688dc19f
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44259
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of enabling ASAN_IN_ROMSTAGE from Kconfig file in a
platform's dedicated directory, let's introduce a new config
option HAVE_ASAN_IN_ROMSTAGE to denote if a given platform
supports ASan in romstage.
Similary, use HAVE_ASAN_IN_RAMSTAGE to indicate
if a given platform supports ASan in ramstage. Consequently, we
no longer have to make ASan x86 specific.
Change-Id: I36b144305465052718f245cacf61d3ca44dfb4b4
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch adds ASan support to romstage on x86 architecture.
A Kconfig option is added to enable ASan in romstage. Compiler
flags are updated. A memory space representing the shadow region
is reserved in linker section. And a function call to asan_init()
is added to initialize shadow region when romstage loads.
Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch adds address sanitizer module to the library and reserves
a linker section representing the shadow region for ramstage. Also,
it adds an instruction to initialize shadow region on x86
architecture when ramstage is loaded.
Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
An additional compiler flag is added to make use of the shadow
offset callback feature we introduced in our GCC patch. Also,
a comment is added to tell user that this GCC patch needs to be
applied in order to use ASan.
Change-Id: Ia187e4991bf808f4ae137eff0ffdb9baea0085e9
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add a Kconfig option to enable address sanitizer on x86 architecture.
Create ASan dummy functions. And add relevant gcc flags to compile
ramstage with ASan.
Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On MT8192 the SPI flash is actually using a SPI-NOR controller with
its own bus. The number here should be a virtual value as
(SPI_BUS_NUMBER + 1).
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ibc269201a34968c8400d2235e8da2ecd88114975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
With CSE-lite enabled, we were going through the lengthy memory
training procedure twice on the first power-on boot or after full BIOS
SPI flash update. This moves the global reset performed to achieve the
CSE-lite RO to RW reboot to a later boot phase so that it happens
after the memory training data has been written to the MRC cache. Now,
the 2nd (and subsequent) reboot can utilize the memory training data
established during the 1st boot.
This reduces the first boot time by about 20s on a 16GB system.
Looking at the timing stats form cbmem, the normal boot penalty is
about 300ms - mostly attributed to running FspSiliconInit a 2nd
time. We will get this time back when the mrc_cache refactoring effort
lands (cb:44196, et. al).
BUG=b:162021048
TEST=Booted on volteer, confirmed 20s faster boot time.
Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add code for IVRS generation to coreboot. Publish coreboot generated
structure rather than IVRS generated by FSP binary.
Reference Doc: 48882_IOMMU_3.05_PUB.pdf
BUG=b:155307433
TEST=Boot trembyle to shell and extract and compare IVRS tables and make
sure they cover the same devices.
Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4
only if we know that the Cr50 is generating 100us interrupt pulses.
We have to do so, because the SoC is not guaranteed to detect pulses
shorter than 100us in S0i3.4 substate.
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code
running in verstage, which will program a new Cr50 register, provided that
Cr50 firmware is new enough to support the register.
BUG=b:154333137
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Change-Id: If83188fd09fe69c2cda4ce1a8bf5b2efe1ca86da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Kconfig 5.8 interprets $(...) itself using environment variables, which
generally means that they expand to the empty string. \$(...) works
with both our current and new Kconfig with the desired behavior
(to pass it through unmodified).
Change-Id: I726567eeb61d2035560152677d2b4548c1472be9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44584
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the Super I/O to know how hot the CPU is.
Change-Id: I9c91136c3bb5aae541bb7ac64bb62be36c3c0b5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Not selecting `ME_MBP_CLEAR_LATE` results in a build failure. Since both
traditional and ULT platforms are known to be working, drop the option.
Change-Id: I09ce27f812966800e36f6c0624c93759089faf45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Together with the "AMD_XMP" changes, now this board with Crucial
BLT8G3D1869DT1TX0 sticks could run at 1600 MT/s CL8 (8-8-9-23) speeds.
Earlier only 1333 MT/s CL9 (9-9-10-27) has been possible with coreboot.
1866 MT/s CL9 is impossible on f16kb without northbridge overclocking.
tRP in "CL-tRCD-tRP-tRAS" gets set 1 point higher by AGESA because of
Errata 638. See more info in a BKDG for AMD Family 16h Models 00h-0Fh.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I7e9f5120421221043f9f9dfe143b51bfa61936be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44462
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD f16kb boards are perfectly capable of working at 1600MT/s RAM speeds
even with two DDR3 UDIMM modules per channel. AM1I-A only supports a
single-channel operation, with at most two DIMMs per channel, so raising
these limit values is required to let it and similar boards run faster.
Successfully tested on AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs,
together with related AMD_XMP changes - also required to get a 1600MT/s
with this set of modules which have only 1333MT/s at JEDEC part of SPD.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will remove the warning:
"src/soc/intel/xeon_sp/cpx/Kconfig:79:warning: config symbol 'CPU_BCLK_MHZ' uses select, but is not boolean or tristate"
Change-Id: I2cfaf347b638e3847caa167e7efda89e9202960a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Remove references to clk_pm_support which is currently ignored
by Picasso AGESA FSP.
BUG=b:161218965,b:162423378
TEST=Build test Trembyle and Dali, boot to ChromeOS 5 times each
Change-Id: Ic5d6abc56821863b68e45c11763f00d2b6410983
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44556
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update fsp_dxio_descriptor comments to be more comprehensive
of the currently available data fields. Most of these are not
currently utilized with Zork but may be in future projects.
BUG=b:161218965
TEST=Build test Trembyle
Change-Id: I8eb79fa7807dcf5b28b7b0ec60953ef857d51972
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Volteer also uses the CSE Lite SKU and the cr50, it is subject
to a problem where old cr50 FW will not be able to properly detect an
SoC reset, so the reset on cold boots caused by the CSE Lite RO->RW
jump should instead get an assist from the EC, which can perform a
full cold reset.
BUG=b:162977697
TEST=Verify EC performs the cold reset
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie8ae21c203da218459d5fd30a23be23520ed0598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* Enable optional x86_64 romstage, postcar and ramstage
* Add Kconfig for x86_64 compilation
* Add documentation for x86 qemu mainboards
* Increase CAR stack as x86_64 uses more than 0x4000 bytes
Working:
* Boots to Linux
* Boots to SeaBIOS
* Drops to protected mode at end of ramstage
* Enumerates PCI devices
* Relocateable ramstage
* SMM
Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29667
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When compiled in RAMSTAGE use the segments for ramstage.
Allows to call this assembly code in ramstage to exit long mode.
The next commit makes use of this.
Tested on qemu:
Still boots on x86_64.
Change-Id: I8beb31866bd15afc206b480b1ba05df995adc402
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode.
* Add a helper function to jump to arbitrary code in protected mode,
similar to the real mode call handler.
* Doesn't affect existing x86_32 code.
* Add a macro to cast pointer to uint32_t that dies if it would overflow
on conversion
Tested on QEMU Q35 using SeaBIOS as payload.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The AM335X is a SoC, so should be in the soc tree.
This moves all the existing am335x code to soc/ and updates any
references. It also adds a soc.c file as required for the ramstage.
Change-Id: Ic1ccb0e9b9c24a8b211b723b5f4cc26cdd0eaaab
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Implements fit_payload_arch for the arm (aarch32) architecture, so that
FIT images can be used. The implementation is very similar to the
existing implementations for arm64 and riscv, and has mostly been
lifted from these other ports.
TEST: Booted Beaglebone Black (in progress port, to be submitted soon!)
with a FIT image containing a 5.4 kernel, dtb and initramfs.
Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Capture the GPIO subsystem wake state and add events to
the eventlog.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7f10bf4599ea7928cc87b6b10ac11a7c30e58406
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to log gpio events for wake purposes the state
of the gpio subsystem should be snapshotted. Add the ability
to capture state of gpio subystem as well as saving up to 16
gpios that indicate their wake status.
Likewise, provide the eventlog additions based on state.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I49fca56c87543aa8aad0eb7da5c5cb570c4349d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44534
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch from locating the AMD firmware in the RW_A &
RW_B regions with their hardcoded locations to using CBFS to find
them. They still need to be at the hardcoded locations so that we
can set the location inside the binary, but instead of just setting
the pointer directly to them, we now search for them with cbfs.
BUG=b:154441227
TEST=Boot & verify that binaries are located in both RW-A & RW-B
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42831
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This #define wasn't removed when the tests were removed, so get rid
of it now.
BUG=None
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ie0005b6ee97037bf3dfb80f0c2408d8bd9ee9633
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There are only headers for the SoC's UART 0 and 1 on the board.
BUG=b:165020060
TEST=Linux only detects UART 0 and 1.
Change-Id: I45929f65a5f844ae5cef792b11176f487c80766f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44530
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order for Linux to find and use the SoC's integrated UARTs, they need
to be exposed in ACPI.
BUG=b:165020060
TEST=Linux detects the SoC's integrated UARTs.
Change-Id: Iaa66657b88f62b2067c865c3e1945b7bdbf9be23
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Using the SOC's UART 0 as console requires moving a few resistors on the
Mandolin board.
BUG=b:165020060
TEST=coreboot console works on SoC UART 0 when AMD_LPC_DEBUG_CARD isn't
selected.
Change-Id: Idaf73ae84f54028da2182ce42035f9ecd63f4776
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In CB:44488 the cbmem addition was re-filling the object
when it should be memcpy()ing from static object. Correct
that oversight. The side effect from the previous implementation
would be if FSP-M modified the GPE state.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I158a89ae28431896fa9b5789292000fcbf0b066d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44533
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
DP_HPD had been removed for EVT design as those events are through eSPI.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=b:162566436
TEST=Booted to kernel and verified no kernel HPD pins assertion message
on Volteer EVT board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44501
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The wake source macro for GPE events was using 'GPIO'. However,
current usage is really all GPEs. Therefore, provide clarity
in the naming in order to allow for proper GPIO wake events
that are separate from the ACPI GPE block.
BUG=b:159947207
Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Configure TRACKPAD_INT_ODL pad reset config to DEEP and
map PMC_GPE_DW to PMC_GPP values.
TEST=System should wake from S3 via trackpad
Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
PMC_GPE_DW mapping was not configured correctly and hence
coreboot skipped programming Tier 1 GPIOs resulting in failure of
S3 wake from Trackpad.
TEST=System should wake from S3 via trackpad
Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Similar to commit b45ed65, the HOB structure is actually a 8 byte
address pointing to the HOB data.
Tested=Verified the values of the hob fields are the same printed by
soc_display_memmap_hob().
Change-Id: I348d3cd80a56e86d22f20fcadf0316b462b86829
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable long mode in SMM handler.
x86_32 isn't affected by this change.
* Enter long mode
* Add 64bit entry to GDT
* Use x86_64 SysV ABI calling conventions for C code entry
* Change smm_module_params' cpu to size_t as 'push' is native integer
* Drop to protected mode after c handler
NOTE: This commit does NOT introduce a new security model. It uses the
same page tables as the remaining firmware does.
This can be a security risk if someone is able to manipulate the
page tables stored in ROM at runtime. USE FOR TESTING ONLY!
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Add new librem_whl baseboard and Librem Mini variant.
Tested with SeaBIOS, Tianocore, and Heads payloads.
All functions working normally except SATA, which is limited
via a FSP UPD to 3Gbps until the correct HSIO PHY settings
can be determined.
https://puri.sm/products/librem-mini/
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
FSP enables IPU (Imaging Processing Unit) by default even if its
disabled in devicetree. We need to fill FSP upd based on the device
enablement in devicetree.
BUG=None
BRANCH=None
TEST=IPU is disabled and doesn't show in lspci.
Change-Id: I0f9a40e85427fd88bb12a40770ecf7b939b1d8cd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Enable the introduced LPSS ACPI uart driver.
Tested on Hermes using Linux 5.6:
The UART2 appears as /dev/ttyS2.
Change-Id: Ic15be4a807012216e52c848120de7e39522f57b7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Emit ACPI code for LPSS UARTs operating in ACPI mode. In this mode the
device vendor ID reads as 0xffff, the PCI devices is still operate.
Add ACPI device IDs for APL, GLK, SPT, SPT_H and CNP_H.
The mainboard's devicetree needs to be adapted to include the chip
driver and the PCI ID when it wouldn't have been hidden.
Example:
chip soc/intel/common/block/uart
device pci 19.2 hidden
register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
end # UART #2
end
Tested on Linux 5.6 with Sunrise Point ACPI ID for UART2.
Tested on Windows for all other UARTs.
Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPE events were not be recorded in the eventlog. Add those
to the eventlog when the status register indicates those events.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifb3167fd24f2171b2baf1a65eb81a318eb3e7a86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Previously the chipset state was snapshotted very late in the boot
(ramstage). Instead start gathering the state early in romstage
prior to calling any FSP routines so there's a clean snapshot.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that no one is consuming this object, remove its definition.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib5aeec1733b6c9fa49569e30c4c369f70af0939c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that no one is consuming this object, remove its definition.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I60e4a9bfdf2752923f46a35aaab7034f9fa9b309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that all users of the functions manipulating global state
and using soc-specific objects are removed remove those functions.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I18c4c8b0c7852dde8cf0b6b3f11e43e15c3ce155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Transition the current call sequence to using the newly added common
ACPI helper functions. Semantically, the expectations are that this
sequence is the equivalent of previous acpi_clear_pm1_status(). However,
in subsequent patches picasso will be snapshotting state way sooner than
ramstage.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I34e2ba7c5cd123b98c39291537e74175ec043e85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Transition the current call sequence to using the newly added common
ACPI helper functions. Semantically, the expectations are that this
sequence is the equivalent of previous acpi_clear_pm1_status().
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id3ae19013c68d2c97b084046f600596ecc462374
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to reduce code duplication provide an acpi_fill_gnvs()
helper function. Intent is to move stoneyridge and picasso over
to using this common implementation instead of duplicating it.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I21c6e2c24eaf42f31ae57c05df7f633d7dc266d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The existing code in common/block/acpi is mixing multiple operations:
saving things to cbmem in common code but then soc code uses that
information, reliant upon soc-specific struct soc_power_reg object,
and only saving/snapshotting ACPI registers very deep in ramstage.
To unwind the above provide some functions that are more targeted:
- Add struct acpi_pm_gpe_state object
- Add acpi_fill_pm_gpe_state()
- Add acpi_pm_gpe_add_events_print_events()
- Add acpi_clear_pm_gpe_status()
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia7afed2861343802b3c78728784f7cfaf6f53f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This fix is required to avoid the division-by-zero error described at
https://mail.coreboot.org/pipermail/coreboot/2014-March/077418.html
while trying to run the DDR3 memory at 1866 MT/s (933 MHz).
With this fix in place, ASUS A88XM-E boots fine with RAM at 1866 MT/s.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I8e7d00e362879b1247ecf2ab828936268bf9075f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Required for adding the XMP profiles support. SPD buffer is
already 256 bytes at AMD AGESA vendorcode, so this is fine.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I7340b110477a4cc1ecb1c239181436e51952568f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Naming a device allows an ACPI _ROM method to be written for it. GPUs
may require this to make the configuration data contained within
available to an OS driver. This may be required for GPUs that do not
contain their vBIOS, or perhaps the drivers require it in this form/fashion.
Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully
obtains the vBIOS via ACPI (kernel 5.7.11).
Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
With new board designs being introduced it does not make sense for the default
devicetree setting to be retimer disabled on port 0 for Aux Orientation.
Change the default to be Aux Orintation retimer controlled on all ports and
move the SOC controlled overrides to the corresponding overridetree files.
BUG=NONE
BRANCH=NONE
TEST=Built image for delbin and verified that port 0 flip is working.
Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This change sets the EFS config for SPI read mode to normal read mode
when using em100. With this, the boot is stable again without any
random hangs in PSP.
BUG=b:164429022
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4cd3673dcc44a61905719a57f734df2fb9f4e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
David Wu