Commit Graph

16866 Commits

Author SHA1 Message Date
Martin Roth 24ae84d260 vendorcode/intel/Kconfig: Add broadwell_de symbol to fix lint
The Kconfig lint tool is complaining because this symbol doesn't
exist.  Create a temporary definition that can be removed when
the chipset is added.

Change-Id: I6a8abffcc91773aae16721ee1f48c4c64bd6b486
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14091
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-15 15:23:40 +01:00
Martin Roth 8ba235e2ac genbuild_h: Fix numeric comparison to remove error
Change the comparison of build_timeless from -eq to =

This was generating an error if BUILD_TIMELESS wasn't set:
util/genbuild_h/genbuild_h.sh: line 27: [: : integer expression expected

This wasn't causing the script to fail, and won't even if 'set -e' is
added to the script because the error happens inside an 'if' clause,
which is specifically excluded from failue on 'set -e'.

Change-Id: I6a4e147ece23e83ee682d72db35be9e5d4088c78
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14080
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-14 23:37:12 +01:00
Aaron Durbin 08e920e50d util/cbmem: Scale time stamp values correctly
Commit c49014e (timestamp: add tick frequency to exported table)
refactors the code, but forgets to correctly scale the frequency to
megahertz, where the value is read from sysfs, so that printing time
stamp information shows milliseconds instead of microseconds, as can be
seen on the output `cbmem -t` for the ASRock E350M1 below.

```
   0:1st timestamp                                     515
  10:start of ramstage                                 515 (0)
  30:device enumeration                                515 (0)
  40:device configuration                              610 (94)
  50:device enable                                     614 (4)
  60:device initialization                             624 (9)
  70:device setup done                                 639 (14)
  75:cbmem post                                        844 (205)
  80:write tables                                      844 (0)
  90:load payload                                      849 (4)
  15:starting LZMA decompress (ignore for x86)         849 (0)
  16:finished LZMA decompress (ignore for x86)         869 (20)
  99:selfboot jump                                     869 (0)

Total Time: 350
```

So scale the return value correctly to megahertz, by dividing it with
1000.

```
   0:1st timestamp                                     515,655
  10:start of ramstage                                 515,655 (0)
  30:device enumeration                                515,663 (7)
  40:device configuration                              610,620 (94,957)
  50:device enable                                     614,680 (4,059)
  60:device initialization                             624,618 (9,938)
  70:device setup done                                 639,553 (14,934)
  75:cbmem post                                        844,707 (205,154)
  80:write tables                                      844,710 (2)
  90:load payload                                      849,532 (4,821)
  15:starting LZMA decompress (ignore for x86)         849,655 (123)
  16:finished LZMA decompress (ignore for x86)         869,903 (20,247)
  99:selfboot jump                                     869,922 (19)

Total Time: 354,261
```

Change-Id: Iea032c62487c7946b6194a90268755034c6350df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/14086
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-03-14 21:30:01 +01:00
York Yang 15fca66bf0 vendorcode/intel/fsp1_0: Add Broadwell-DE SoC vendor code
Initial vendor codes to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.

Change-Id: I9262c9d70a58f0c7427f0658948adf080f2f6d8f
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14030
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-14 18:24:43 +01:00
Ben Gardner 08bfba4f02 intel/fsp_baytrail: Enable LPSS in ACPI mode
This change fixes LPSS ACPI mode. Previously, enabling ACPI mode would
result in unusable devices, as the resources were set to 0 and the devices
were disabled.
lpss.c was copied from intel/baytrail with a few minor adjustment for the
different config structure.

ACPI mode requires setting PcdLpssSioEnablePciMode==LPSS_PCI_MODE_DISABLE
and applying the patch that disables clearing gnvs.
https://review.coreboot.org/#/c/14040/

This doesn't handle the case where the FSP has PcdLpssSioEnablePciMode
set to disable and the devicetree set to default.

Change-Id: I12fffea3820ed948defe7a4f11af6b6363402560
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-14 18:24:10 +01:00
Duncan Laurie 59be62480e intel/fsp1.1: Mark graphics init done after SiliconInit phase
If the VBT was provided to the FSP GOP driver then graphics init
will be done as part of SiliconInit step and we can mark that
when it is completed.

This will result in the "oprom" flag being set properly in the
coreboot gpio table and the netboot firmware will have video.

[pg: avoided conflict with Quark that comes without
     silicon_init_params.GraphicsConfigPtr]

BUG=chrome-os-partner:50864
BRANCH=glados
TEST=boot image.net.bin on chell and get working graphics
without being setuck in a reboot loop thinking graphics needs
to be started when it already has been.

Change-Id: I0e481b4be57096ed5c60d78e3fa00f3bb2a4eae1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 089d93c712431d1b5923e844137c558994555e95
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331301
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-(cherry picked from commit eeb9d470d8118422feb39ca71106972f2882e240)
Original-Change-Id: Ic59bad27eb9f184ca3eba24643851bfadfe23ab5
Original-Reviewed-on: https://chromium-review.googlesource.com/331355
Reviewed-on: https://review.coreboot.org/13986
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-03-14 10:53:19 +01:00
Timothy Pearson bc5ad1087b nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training
Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a
did not take into account the default UI setting introduced in
change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM
instability and occassional failure to boot.

Use the correct 1UI value for the modified function semantics.

Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14073
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 23:42:41 +01:00
Jonathan Neuschäfer d43186418a coreinfo: Remove the LAR module
Since libpayload's LAR support was dropped in If6e36569cd, this module
doesn't compile anymore.

Change-Id: I98f25613a1728e94704d9e9ccb65fd6ba33968b9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14037
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-13 08:24:49 +01:00
Jan Tatje fa31751fc7 util/ifdtool: add option to change chip density
Adds -D / --density option to change the chip density. This is only
implemented for IFD version 1 as I do not have an IFD version 2 to
test this. Density of both chips is changed by default, but a chip
can be selected using -C / --chip.

Change-Id: Iba7affbf6cbefa3147b7b0e019298d905e694716
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/14032
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 04:42:40 +01:00
Ben Gardner cbfec89037 intel/fsp_baytrail: Fix LPE initialization and enable ACPI mode
This change properly assigns resources to the LPE (Low Power Engine for
Audio) and enables ACPI mode.
lpe.c was copied from intel/baytrail with a few minor adjustment for the
different config structure.

ACPI mode requires setting LpeAcpiModeEnable=LPE_ACPI_MODE_ENABLED and
applying the patch that disables clearing gnvs.
https://review.coreboot.org/#/c/14040/

Change-Id: I3fff9aa158bde88e571082642d4f985a5ae1976e
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 03:07:16 +01:00
Ben Gardner 983608daa5 intel/fsp_baytrail: Don't clear gnvs in acpi_init_gnvs()
That wipes out all previously stored settings and breaks running devices
in ACPI mode.
This more closely matches what is done in intel/baytrail.

Change-Id: Ie993c9f9e1eceb73d016d2df72770a27abb26ec1
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14040
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 03:06:37 +01:00
Martin Roth 10008107b7 abuild: Add option of starting with an existing defconfig file
We want to start testing builds with additional Kconfig options to try
to get more coverage.  This will allow us to enable various options to
test without having to add each individual option to the abuild script.

Change-Id: I9bb2bb6f38589e3bcc1282dc4cad51cf6f5149aa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-13 03:05:43 +01:00
Stefan Reinauer 2510e2aa44 northbridge/intel/i3100: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i3100 boards in the chipset.

Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13786
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 02:22:39 +01:00
Stefan Reinauer e3fd63f264 northbridge/intel/i82810: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i810 boards in the chipset.

Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 00:46:55 +01:00
Stefan Reinauer 63db6142b6 northbridge/intel/i82830: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i830 boards in the chipset.

Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 22:03:42 +01:00
Timothy Pearson 2d987fe0fb nb/amd/mct_ddr3: Consolidate duplicated code
read_dqs_read_data_timing_registers() and
read_read_dqs_timing_control_registers() served essentially
the same function but had slightly different semantics,
causing confusion and needlessly complex Family15h code.

Consolidate both into read_dqs_read_data_timing_registers()
and adjust surrounding code to match new semantics.

Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13994
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 20:27:48 +01:00
Antonello Dettori 3aa91dc7be payloads/seabios: Add "git revision" to the SeaBIOS version menu
Add an option to specify a git revision from which to build SeaBIOS.

Change-Id: Ifbf3b82e784f79395ab7cd07c5804f72928d7640
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13937
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins)
2016-03-12 20:23:50 +01:00
Duncan Laurie d68e0476e9 intel/skylake: Do not log wake source on reset
Skip logging a wake source when just resetting without coming from
S3 or S5 state.  This will prevent the occasional spurious event
like PCI PME from showing up in the event log.

BUG=chrome-os-partner:40635
BRANCH=glados
TEST=run warm reboot teset on chell and ensure no wake source is logged

Change-Id: If739034dc9022b37c90b9cc849a00c604383e70f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7b5cc91adc3ed10df7cebd758cf8144216b9890
Original-Change-Id: I16f4f98df8c70fd25986a8b3644334c7209fd083
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329846
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331173
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13991
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 09:23:15 +01:00
mgarima d47d77692a intel/kunimitsu: Add SD card detect GPIO for SDHCI runtime PM
Enable SDHCI runtime PM since the display flicker due to
SCC Power Gatingis addressed by 0x82 microcode

BRANCH=glados
BUG=chrome-os-partner:44663
TEST=Check if display flicker is gone when SCC is power-gated

Change-Id: I7d1ac6e77a0d2e0a25414df6130862efcdae2c82
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b552120cfeff09d16cb79652b7de7296121858ba
Original-Change-Id: Id82df475b262e8a91f0a93f8ddf80002b05c52f3
Original-Signed-off-by: Medha Garima <medha.garima@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329651
Original-Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Original-Tested-by: Jenny Tc <jenny.tc@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331172
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13990
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 09:22:51 +01:00
Aaron Durbin fe4d62708a soc/intel/skylake: add option to statically clock gate 8254 timer
In order to save more power by shutting down clocks add the
ability to optionally clock gate the 8254 programmable interrupt
timer.  When doing this the platforms lose their "PC"-ness which
certain payloads and OSes rely on such as SeaBIOS.

BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Enabled option on chell. Noted the bit is set upon booting.

Change-Id: I01f9d177bbde417d1efec2e16656a07dcebccbde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 662575aa6a63656dedfa0ce1f202f5fac0205477
Original-Change-Id: Ib4a613cf1c28fc96c36fa2987c4b58a05beab178
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329411
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331171
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 09:21:56 +01:00
Rizwan Qureshi 898e965abb glados/chell: send an extra VR mailbox command
MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode
has been updated since v76, and it requires an an extra VR mailbox
command should be sent from coreboot to pcode.

BUG=chrome-os-partner:48511
BRANCH=None
TEST=Verified on glados, clean S0ix entry and exit.
	IMVP8 power is also pretty low

CQ-DEPEND=CL:329393

Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2
Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329480
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13983
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 09:21:20 +01:00
Rizwan Qureshi af31a998c9 soc/intel/skylake: add option to enable VR specific mailbox cmd
Adding an option to enable VR specific mailbox command.
When set, an extra VR mailbox command specifically for
the MPS IMPV8 VR will be sent.

BUG=chrome-os-partner:48511
BRANCH=None
TEST=Verified on glados, clean S0ix entry and exit.
        IMVP8 power is also pretty low

Change-Id: Ia5a23cbb1eca8b463eb7c7c279b74635f1d6b9f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c90a799b51fe35bf184dca6ffce59c89a60f9917
Original-Change-Id: Iffd3fbcb9a15611eefc942529e6cdafba859fb2e
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329393
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13982
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 09:20:59 +01:00
Aaron Durbin d2077af1af vendorcode/intel/fsp/fsp1_1/skylake: update FspUpdVpd.h 1.9.0
The previous copy of FspUpdVpd.h was not up to date w.r.t. the
FSP release being used for skylake boards. Fix that.

BUG=chrome-os-partner:50863
BRANCH=None
TEST=Built and booted on chell.

Change-Id: I39896c04d35189b0fb2c903eefda4e5b7c57084a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fd647f354b8d9946b2217751cf1af845f29191b7
Original-Change-Id: I4ad131af6c563c9c33eb2b9207b13617ff24385d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331290
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13984
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 09:20:04 +01:00
Yidi Lin 0bdfec8578 mediatek/mt8173: memlayout: Create DRAM DMA region for NOR flash DMA read.
NOR flash has a hardware limitation that it can't access SRAM region
after 4GB mode is enabled. We add a DRAM DMA region after 0x40000000
for NOR flash driver. So that the NOR flash driver can use this region
after 4GB mode is enabled.

BRANCH=none
BUG=chormoe-os-partner:49229
TEST=Boot to kernel on rev4 w/ 2GB ram and rev3 w/ 4GB ram.
     And check /proc/meminfo.

Change-Id: I4a86f0028b26509589ec8d09e2d077920446ece1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dc61ec55187959101a9e891fe5e93928e9b8176e
Original-Change-Id: Ifedc9e2dfba5d294297b3a28134997ac1dd38f94
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327962
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331177
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13989
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:14:58 +01:00
Yidi Lin c6d7dcc832 mediatek/mt8173: detect sdram size at runtime
Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect
the DRAM size at runtime.

BUG=chrome-os-partner:49427
BRANCH=none
TEST=Boot to kernel

Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223
Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327961
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331176
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:14:33 +01:00
Yidi Lin 9a64ec4dd2 mediatek/mt8173: mmu: update mmu range before DRAM is initialized.
The DRAM size can not be determined before DRAM is initialized. Since
mt8173 only support 2GB and 4GB DRAM models. We map 0x0 to the end of
2GB DRAM address before DRAM is initialized.

BRANCH=none
BUG=none
TEST=boot to kernel

Change-Id: I27a00106b0aa91c3dacfcd2bcd9208f08b108dc5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9720e67c86f0d37a08f7c32e900996c75d60288a
Original-Change-Id: I87d9c6ac11486decde102b7821f550c2f1a51f1c
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327960
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331175
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13987
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:14:18 +01:00
Jitao Shi fd99eca800 Add a driver for the parade ps8640
BRANCH=none
BUG=none
TEST=none

Change-Id: Icf397ce2ffdaed5048367daf2086c067984fea0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b5a88793ccfc46af196300791a300be67b70f5b1
Original-Change-Id: I75adf2688c9c8b9a2338f7dee5d0ac10e7181529
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321056
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13981
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:12:20 +01:00
Yidi Lin a622f28cb2 mediatek/mt8173: pll: raising the CPU core frequency
Runs the LITTLE core at highest freqency to speed up the boot time.
Set Vproc to 1.125V and set the freqency to 1.6Ghz for backward
compatibility. (The highest frequency for the IC before E3 is 1.6Ghz.)

BRANCH=none
BUG=chrome-os-partner:47422
TEST=flash the bootloader and measure the boottime by cbmem result

Change-Id: Id0b906bf34ac534667eb6e8f576e30942ceb923e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5fc38548d158158f07cded8cfc8ea5a0a7952161
Original-Change-Id: I62af26c13d98211974243100c581abcb5408fd63
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/324685
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13980
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:12:13 +01:00
Bayi Cheng d8bb51eb4e mediatek/mt8173: add NOR DMA read
BRANCH=none
BUG=none
TEST=boot oak to kernel on rev2

Change-Id: I368fcac1cf5e2261d00a34882a7341733ebd0732
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ea0407f7273bc88613bc23a6fc4c41f9cca1adb
Original-Change-Id: Ic422e7265fdd35c573d8cd44280a1f7dc163a6db
Original-Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/323932
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13979
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:11:52 +01:00
Jitao Shi 5ffb6887c2 device/i2c: Add i2c_read_bytes() API
Add multi-bytes read support.

BRANCH=none
BUG=none
TEST=saw edid log and dev screen

Change-Id: I106be98e751e2a3b998ccaedb28f71f3c6e18994
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94ee0b834947e8d971943aa24e61a9353c7b7306
Original-Change-Id: Iac5fe497da92b7d09383e0d6a04d98709aea5b20
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/325211
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13978
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:11:43 +01:00
Yidi Lin 358f66a442 google/oak: Configure USB OC pins
BRANCH=none
BUG=none
TEST=none

Change-Id: If7244d0050833c676de72106d1c8473dd8f290a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 89356785e66eb6d5b52fdf09933d2d28d9f67a90
Original-Change-Id: I94dda9834da6553795e7f3f65ff267fdcb6b7d47
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321055
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13977
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:11:19 +01:00
Ben Lok 7d7dc20e9e google/oak: Config USB Hub for rev5
Reset pin of USB Hub is connected to GPIO118, it is low active.
Config GPIO118 as GPO and output high.

BRANCH=none
BUG=none
TEST=emerge-oak coreboot

Change-Id: I630cfd1c1019447736e7e5b286790fead4bdcfb6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4b5cd98d0b3c5d2bab408ecebebc924d1f2b7df
Original-Change-Id: I1ea0e1baac3da4d13301307f01bbe51e108298dd
Original-Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321054
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:11:10 +01:00
Koro Chen a9f6529924 google/oak: Config audio for rev5
BRANCH=none
BUG=none
TEST=emerge-oak coreboot

Change-Id: Ibdafa4ffe0baf5231654e67612b7ca59d835b602
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 63fedfec26ba1444934e348ce59609fa88e12de5
Original-Change-Id: Ifbbf8d2b3b6e163481843308c2e3edc4a55f90c6
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319988
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:11:01 +01:00
Koro Chen 603cb8511f google/oak: Remove obsolete Rev0 setting
BRANCH=none
BUG=none
TEST=emerge-oak coreboot

Change-Id: I65aa87e88cf812fdb490933de1a3b121866a2694
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8f703f7e71ae6ffc0f1ac0e70486d087a28da5ba
Original-Change-Id: I8d794464d45ea69f9a46f7ebc505f6ec2127f204
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319987
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13974
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:10:49 +01:00
Yidi Lin cd6aac1524 google/oak: Enable TP_SHIFT_EN for the revisons before 5 only
BRANCH=none
BUG=none
TEST=emerge coreboot

Change-Id: Ic46490a56a6a8146b91a055b9ce5d5bb23bc7a49
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 082ce1848bf37bba369fd0dccc4cf3fc83a8a018
Original-Change-Id: I58f009d2fc03cf5a52b4dbd042a92973cde4d035
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320029
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13973
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:09:19 +01:00
henryc.chen 70b3044e45 google/oak: da9212 gpio configuration for rev5
BRANCH=none
BUG=none
TEST=none

Change-Id: Ib44a9e8ca94727809e47831228f4742c25a53977
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: da9185c22264440da822aa252c0c5d2aef78b455
Original-Change-Id: I98c2ad757d0cd0e3234e49392091784b43a106e7
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320028
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13972
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:08:45 +01:00
Yidi Lin 0443ecc5b2 google/oak: Config PANEL_LCD_POWER_EN for rev5
BRANCH=none
BUG=none
TEST=emerge-oak coreboot

Change-Id: Ic2019a1d61cbc5949c1f42346b279ef05f725dfb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf13606f01438bc2ea27ecccc6359a7320dc34cc
Original-Change-Id: I3fcc403cb7a3429b9673be0e727fc7d8c9d4f556
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320027
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13971
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:08:09 +01:00
Yidi Lin 22d94ba8a2 google/oak: Configure SPI_LEVEL_ENABLE pin for rev5
Oak introduces a 1.8V to 3.3V level shifter for EC SPI bus after rev5.

BRANCH=none
BUG=none
TEST=emerge-oak coreboot

Change-Id: I71868b003fc71dee0532033299afc155a9fbec9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 030b478fedf046a7b818696779299c591415fcbd
Original-Change-Id: Ibff9705832700867279cb1b39b752b8f5f27cf33
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320026
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13970
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:07:21 +01:00
Milton Chiang e2979df3df mediatek/mt8173: Update infracfg register map
BRANCH=none
BUG=none
TEST=emerge-oak coreboot

Change-Id: Ifdeb686f7695fbefadc15d47e9b0c49b6b35c37d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2404a31dac8c84580424fc01816669b27ddf8617
Original-Change-Id: I831d34b1bce2675caa3da8da7a214f392e561000
Original-Signed-off-by: Milton Chiang <milton.chiange@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320025
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13969
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:06:54 +01:00
jun.gao f059e97cc8 google/oak: Initialize i2c bus timing register for TPM and external buck
BRANCH=none
BUG=none
TEST=build pass and boot to oak kernel

Change-Id: Id2c3bbb70a1de54a56ee04ecda76178b1bdf1a4d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9
Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9
Original-Signed-off-by: jun.gao <jun.gao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319031
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:05:35 +01:00
CC Ma 72980b15de google/oak: add event log
BRANCH=none
BUG=none
TEST=boot to shell on Rev3

Change-Id: Ifca80705e392ce171ef33bf98ef787e3cd5ffd6b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d511df7f527ae96c2da01804c62fe98a13fed56
Original-Change-Id: I68ab8be50f210fa17bd731b400a087b150566e3b
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303207
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13104
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:04:58 +01:00
Jimmy Huang 27eba676e0 google/oak: Add soc ARM Trusted Firmware support
We define a mechanism to pass board specific parameters to BL31. The
idea is BL31 doesn't need to have the board revision knowledge, it
only needs to process the board specific parameters to initialize and
control specific hardware. In this way, we can support different boards
with same BL31 binary.

BRANCH=none
BUG=none
TEST=booted on oak-rev2 and oak-rev3 boards, and confirmed they got
     different board arguments in ARM TF

Change-Id: I0df2c6d7d1ffac7d443511c3317c142efeb5701e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f9a4a2776110c5ddc113f0d605d4337d5773ace
Original-Change-Id: I985d9555238f5ac5385e126479140b772b36bac8
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292678
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13101
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:04:10 +01:00
Jimmy Huang f3570d2479 mediatek/mt8173: Add soc ARM Trusted Firmware support
We define a mechanism to pass board specific parameters to BL31. The
idea is BL31 doesn't need to have the board revision knowledge, it
only needs to process the board specific parameters to initialize and
control specific hardware. In this way, we can support different boards
with same BL31 binary.

[pg: add the code, but don't actually enable the support yet, because it
relies on code that still needs to be merged to arm-trusted-firmware.]

BRANCH=none
BUG=none
TEST=booted on oak-rev2 and oak-rev3 boards, and confirmed they got
     different board arguments in ARM TF

Change-Id: I9ea3ce6c8f79dd427be67f30bc940d2038173b81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f9a4a2776110c5ddc113f0d605d4337d5773ace
Original-Change-Id: I985d9555238f5ac5385e126479140b772b36bac8
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292678
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13100
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:03:33 +01:00
jun.gao fa2ed276c3 mediatek/mt8173: Provide I2C bus initialization API
BRANCH=none
BUG=none
TEST=build pass and boot to oak kernel

Change-Id: I8aa9ca0fce804cc1682947b7e184781dd5d437f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9
Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9
Original-Signed-off-by: jun.gao <jun.gao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319031
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:03:05 +01:00
Peter Kao dac533725c google/oak: Initialize DRAM
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I3ed8bad1bdc7d17e334e0136f92a51c8e7ba4e67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e
Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6
Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292692
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13106
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:01:27 +01:00
Peter Kao da1e02a3a0 mediatek/mt8173: Add EMI driver, DRAM initialization
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I6b05898de2d0022e0de7b18f1db3c3e9c06d8135
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e
Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6
Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292692
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13105
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 09:00:21 +01:00
CC Ma b74a2eca80 mediatek/mt8173: enable RTC in ramstage
BRANCH=none
BUG=none
TEST=boot to shell on Rev3

Change-Id: I77c5a8aa31ab10d82115a60bdfee1da35707619f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d511df7f527ae96c2da01804c62fe98a13fed56
Original-Change-Id: I68ab8be50f210fa17bd731b400a087b150566e3b
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303207
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13103
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12 08:59:32 +01:00
mtk05962 a3f7fe8219 mt8173: add SPI NOR support
BRANCH=none
BUG=none
TEST=boot oak to kernel on rev1

Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae
Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18
Original-Signed-off-by: mtk05962 <bayi.cheng@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292693
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 08:59:20 +01:00
Jonathan Neuschäfer f14f640168 crossgcc/buildgcc: Add missing quotation mark
Change-Id: I5c20fd7057751a912aa2b2118dc5610c1ef647dc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14039
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-03-11 22:00:04 +01:00
Alexander Couzens 92fc072c2f northbridge/intel: move mrccache.c of sandybridge + haswell to common
The sourcecode is 99% the same. Only two lines differ, but not
in functionality.
Also rename mrccache.c -> mrc_cache.c

Tested-on: boot + suspend/resume on x220

Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14007
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 19:00:14 +01:00