The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
This patch was merged too early, and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20581
Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20687
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize postcar frame once finish FSP memoryinit
This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534
Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It was added with the words "Update the device header files" and we
maintained it for nearly 13 years :)
These functions are part of the SMBus spec but they are rarely used
and keeping them just in case increases the maintenance burden.
Change-Id: I69a1ea155a21463fc09b7b2c5b7302515a0030b2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The PMIO region was moved, but not updated in the ASL. Change to
generate \_PR table runtime and to report the correct PMIO region
and length.
Fix on Kahlee, where the EC overlaps the region:
[ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0
[ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16
BUG=b:63902389
BRANCH=none
TEST=Cros_ec_lps can reserve the region. ACPI tables are correct.
Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Our current struct for I2C segments `i2c_seg` was close to being compa-
tible to the Linux version `i2c_msg`, close to being compatible to SMBus
and close to being readable (e.g. what was `chip` supposed to mean?) but
turned out to be hard to fix.
Instead of extending it in a backwards compatible way (and not touching
current controller drivers), replace it with a Linux source compatible
`struct i2c_msg` and patch all the drivers and users with Coccinelle.
The new `struct i2c_msg` should ease porting drivers from Linux and help
to write SMBus compatible controller drivers.
Beside integer type changes, the field `read` is replaced with a generic
field `flags` and `chip` is renamed to `slave`.
Patched with Coccinelle using the clumsy spatch below and some manual
changes:
* Nested struct initializers and one field access skipped by Coccinelle.
* Removed assumption in the code that I2C_M_RD is 1.
* In `i2c.h`, changed all occurences of `chip` to `slave`.
@@ @@
-struct i2c_seg
+struct i2c_msg
@@ identifier msg; expression e; @@
(
struct i2c_msg msg = {
- .read = 0,
+ .flags = 0,
};
|
struct i2c_msg msg = {
- .read = 1,
+ .flags = I2C_M_RD,
};
|
struct i2c_msg msg = {
- .chip = e,
+ .slave = e,
};
)
@@ struct i2c_msg msg; statement S1, S2; @@
(
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1 else S2
|
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1
)
@@ struct i2c_msg *msg; statement S1, S2; @@
(
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1 else S2
|
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1
)
@@ struct i2c_msg msg; expression e; @@
(
-msg.read = 0;
+msg.flags = 0;
|
-msg.read = 1;
+msg.flags = I2C_M_RD;
|
-msg.read = e;
+msg.flags = e ? I2C_M_RD : 0;
|
-!!(msg.read)
+(msg.flags & I2C_M_RD)
|
-(msg.read)
+(msg.flags & I2C_M_RD)
)
@@ struct i2c_msg *msg; expression e; @@
(
-msg->read = 0;
+msg->flags = 0;
|
-msg->read = 1;
+msg->flags = I2C_M_RD;
|
-msg->read = e;
+msg->flags = e ? I2C_M_RD : 0;
|
-!!(msg->read)
+(msg->flags & I2C_M_RD)
|
-(msg->read)
+(msg->flags & I2C_M_RD)
)
@@ struct i2c_msg msg; @@
-msg.chip
+msg.slave
@@ struct i2c_msg *msg; expression e; @@
-msg[e].chip
+msg[e].slave
@ slave disable ptr_to_array @ struct i2c_msg *msg; @@
-msg->chip
+msg->slave
Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The S3 resume path is broken on current Linux (4.11.3) and maybe
on older kernel, too.
Don't run the native graphics init when on S3 resume to fix it.
Tested on Lenovo T430.
Change-Id: Ifad145c86c2e8f019c507f97c889b70b7aa49882
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch add new API to read LPSS CLK register. Also combine multiple
LPSS_CLOCK_CTL_REG writes into a single write inside lpss_clk_update function.
Change-Id: I420919ad9154c4cf426bc232c5eb59d95fd698d2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Call weak method die_notify.
The method should be overwritten in mainboard directory to signal that
a fatal error had occurred. On boards that do share the same EC and where
the EC is capable of controlling LEDs or a buzzer the method can be
overwritten in EC directory instead.
Tested on Lenovo T500.
Change-Id: I71f8ddfc96047e8a0d39f084588db1fe2f251612
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19696
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This allows the use of the native VGA init on boards featuring DVI-I
ports. Digital output is not supported.
Change-Id: I11a4dd68746e06c7e27ecf3e765bdd0d8cf40515
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These Kconfig options can be reused for the same purpose of selecting
the correct i2c pins for probing the analog output EDID in C native
graphic init. For this purpose this patch makes those options
independent of GFX_GMA and MAINBOARD_HAS_LIBGFXINIT.
Change-Id: If29c541d414e12b95d96ae9c249a7a20e863fe06
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Copy from chrome-ec codebase, except for keeping the long-form license
header.
BUG=b:64468585
BRANCH=none
TEST=with the other sku-id related patches applied, coreboot obtains the
right SKU ID from EC
Change-Id: I513123547f3854945e827d2f7f6c0df6591886eb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20945
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate opregion code from northbridge/intel/common to
drivers/intel/gma in preparation for consolidation with
soc/intel/common opregion code. Rename init_igd_opregion()
for clarity and disambiguation with other implementations.
Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
- let the coreboot build system insert the two blobs to the coreboot image
- EC and Super I/O initialization
- ACPI support
Tested on 2760p, 8460p, 2570p, 8470p.
Issue:
Kernel gives the following error:
ACPI Error: No handler for Region [ECRM] (...) [EmbeddedControl]
ACPI Error: Region EmbeddedControl (ID=3) has no handler
TODO:
- consider moving the Super I/O initialization code to ramstage, or
reuse the existing sio/smsc/kbc1100 code (if so, how to add the
additional kbc1126 specific functions to sio/kbc1100)
- sort out the ACPI code which is mostly from the ACPI dump of vendor
firmware
- find out why the digitizer in hp/2760p doesn't work
- GRUB payload freezing on all HP Elitebooks may be related to EC
Change-Id: I6b16eb7e26303eda740f52d667dedb7cc04b4ef0
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/19072
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The minimum needed defines are included here and pm.h
will be updated when the PMC code for cannonlake is uploaded.
Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helper functions required by intel/common UARRT driver for
enabling controller on S3 resume.
BUG=b:64030366
Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20888
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug port controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helpers functions required by intel/common UART driver for
enabling controller on S3 resume.
BUG=b:64030366
TEST=Verified behavior with different combinations:
1. Serial console enabled in coreboot: No change in behavior.
2. Serial console enabled only in kernel: coreboot initializes debug
controller on S3 resume.
3. Serial console not enabled in coreboot and kernel: coreboot skips
initialization of debug controller on S3 resume.
Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It has been observed on a number of platforms (baytrail, kaby lake)
that if serial console is not enabled in coreboot, but is enabled in
kernel (v4.4), then on resume kernel hangs. In order to fix this, add
support for enabling UART debug port controller on resume.
In order to decide whether UART debug port controller should be
enabled in ramstage, following things are checked in given order:
1. If coreboot has serial console enabled, there is no need to
re-initialize the controller.
2. This special action is taken only for UART debug port controller.
3. If boot is not S3 resume, then initialization is skipped.
4. Callback into SoC to check if it wants to initialize the
controller.
If all the above conditions are met, then UART debug port controller
is initialized and taken out of reset.
BUG=b:64030366
TEST=Verified with the entire patchset series that:
1. If coreboot does not have serial console enabled, but Linux kernel
has console enabled, then on resume, coreboot initializes UART debug
port controller.
2. If coreboot and Linux do not have serial console enabled, then
coreboot does not initialize UART debug port controller.
3. If coreboot has serial console enabled, there is no change in
behavior.
Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20835
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add new API function lpss_is_controller_in_reset that returns whether
the LPSS controller is in reset. Also, add lpss.c to smm stage so that
lpss_is_controller_in_reset can be used in smihandler.
BUG=b:64030366
Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Create a new function uart_lpss_init which takes the UART LPSS
controller out of reset and initializes and enables clock.
2. Instead of passing in m/n clock divider values as parameters to
uart_common_init, introduce Kconfig variables so that uart_lpss_init
can use the values directly without having to query the SoC.
BUG=b:64030366
TEST=Verified that UART still works on APL and KBL boards.
Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
EvLoader is FSP module which loads and runs MMA tests.
With Change-Id Id31ddd4595e36c91ba7c888688114c4dbe4db86a, EvLoader
needs to be enabled with UPD param from coreboot.
Change-Id: Ifb860b98d6e6f21c116473a962f647e491e8546f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new Kconfig option to ignore memory fuses that limit the
maximum DRAM frequency to be used. The option is disabled by
default and should only enabled by experienced users as it
might decrease system stability or prevent a successful RAM
training.
Remove conflicting devicetree settings.
Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nicola Corna <nicola@corna.info>
Get rid of old hybrid graphics driver and use the new one.
1. Disable IGD and PEG in early romstage.
The PEG port will get disabled on devices that do not have a
discrete GPU. The power savings are around ~1Watt.
The disabled IGD does no longer waste GFX stolen memory.
2. Get rid of PCI driver
The Nvidia GPU can be handled by the generic PCI driver and allows
to use the ACPI _ROM generator for Switchable graphics.
3. Settings are stored in devicetree.
One driver for all Lenovo hybrid graphics capable devices.
4. Add support for Thinker1 GPU power handling.
Only boards that do use reference design 2012 are known to be
supported. Needs test on boards that do you use reference design 2013.
Should reduce idle power consumption when using IGD by ~5Watt.
Tested on Lenovo T430 without DGPU. PEG port is disabled.
Needs test on all devices.
Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Introduce a chip_driver that uses devicetree instead of Kconfig.
The new driver has the following advantages:
* No more wasted IGD GFX stolen memory
* Can be used by T500 series
* Is even run on devices that do not have a dGPU installed
* Can disable unused PEG port on devices without dGPU (and save power)
* Use devicetree instead of Kconfig options
* Support for multiple hybrid GPIO active levels
* Support for backlight control GPIO
* Support for _ROM on Optimus capable devices
The driver is split into romstage part and ramstage part.
Every mainboard has to call the driver in romstage to get the requested
GPU state. The mainboard code then has to toggle GPU power or disable
the IGD or PEG port.
The ramstage part does handle the hygrid graphics GPIO, including
optional backlight mux GPIO. Every GPIO can have it's own active level,
as defined in devicetree. Devices are no longer disabled in ramstage.
The existing hybrid graphics driver does the same configuration and
should not interfere with this commit until it has been removed.
Change-Id: Ie467f9a18b35ab3b8a523dbf51c5575db5b374a5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Setting up default BARs and DMI init code is done in northbridge
code.
Change-Id: I6cfa3018ca7f5ef351415c4ec6e178ade353f7a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This mainboard features is an G43 northbridge, ICH10 southbridge and
Winbond W83627dhg SuperI/O. This board is impossible to flash
internally with vendor bios (BIOS region is WP and other regions like
IFD and ME are read only and inaccessible respectively). Due to either
ICH10 or board layout it is also impossible to do ISP, which requires
desoldering flash chip. To make hacking more easy there is an empty
SPI header next to spi flash pads which can be hooked up to a SPI
flash.
What works:
* 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1);
* SATA with AHCI
* Integrated GPU with option rom (extracted from a Gigabyte vendor
bios)
* VGA (on DVI) with NGI if patched to use DVI gmbus port for output
* PCI
* Reboot and S3 resume
* Descriptor mode with ME disable straps and ME region absent (no
working gbe in this configuration though)
* USB.
What does not work:
* GBE (probably requires working ME);
* Analog on DVI port out is shaking, which is not the case with vendor
BIOS (setting clockgen on smbus 0x69 like vendor fixes it).
* Booting with ME enabled (needs raminit patches for that)
Not tested:
* Sound;
* All the rest.
Not coreboot related problems:
* Flashing this board with vendor bios is a PITA and requires
desoldering flash chip;
* In situ programming is not possible.
TESTED with SeaBIOS and Linux 4.10.8
Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add Cannon lake, Apollo Lake and GLK CPU device IDs in
common Mp Init code.
BUG=none
BRANCH=none
TEST=Build and boot reef
Change-Id: I22694ced0cf900a55a28d1ecaa177cab2ea9a90c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20896
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If all strings in SMBIOS table are empty, smbios_string_table_len
function should return 2, cause every table must end with "\0\0".
Also replace "eos" field type in smbios structures
from char to u8.
Change-Id: Ia3178b0030aa71e1ff11a3fd3d102942f0027eb1
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I730a8a150134cc1ef8fb3872728bb0586ac7b210
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19732
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The device_t type is used in smihandler.h, but the header
is not including a header which provides that type. Fix
that by #includeing <device/device.h>
Change-Id: I89af949b088bf569d330f2ea74b1b8ae97e1ed52
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20933
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each line of spd config overwriting the slot 0 instead
of appending it.
Change-Id: I0124aa34f1d4fcb30810fb7eef03d4828a7ac430
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Tested-on: lenovo x1 carbon gen 1 with elpida 8GB
Fixes: e9787ff61f ("mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2")
Reviewed-on: https://review.coreboot.org/20918
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add smm common code for io trap handling. This feature is
mainly used by big core intel platforms. Commonizing io trap
handling will make bring up of big core platforms more
seamless.
Change-Id: I83bcf22107291ea181b347fac40d57d7ea138de1
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20848
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses struct device explicitly for the ramstage functions
as that's the actual type it's working on. Additionally, the
declarations for types and functions are fully exposed so that
compliation units don't have to guard certain functions from use
because it's being compiled for multiple stages.
Change-Id: I8db23ed400a59073e1e66522d020a5928f71f3a6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In _FSL ACPI notification 0x83 was incorrectly being sent to DPTF.
When there should be no notification on fan speed change.
Change-Id: I66efa7a7feb911a458829a54dbd0afefabd42394
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/20875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
the __must_check function attribute is pretty much straight from the
linux kernel - used to encourage callers to consume function return
values.
Change-Id: I1812d957b745d6bebe2a8d34a9c4862316aa8530
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/20881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With this patch apollolake uses the common PMC util
code.No regression observed on a APL platform.
Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/19375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PMC util code is very similar accross different intel SOC's.
This patch is an effort to move those code in common place
so that it can be shared accross different intel platforms
instead of duplicating for each platform. This patch adds
pmclib.c file which contains the pmc utility functions
common accross SOC's. The config for common PMC is
SOC_INTEL_COMMON_BLOCK_PMC which can be defined in SOC's
Kconfig file in order to use the common PMC util code.
Change-Id: Ic3d96fc23a98c30e8ea0969a7be09d217eeaa889
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/19349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Internal PME is detected when bit PME_B0_STS is set. Following devices
causes internal PME.
- Integrated LAN
- HD Audio/Audio DSP
- SATA
- XHCI ('USB3')
- ME Maskable Host Wake
In SPT, PCIEXPWAK_STS bit isn't getting set due to known bug.
So scan all PCIe RP for PME status bit & update event log accordingly.
BUG=b:36992859
TEST=Build for Soraka, Verify resume due to PME on root port is logged
in elog.
Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Ensure that the VLF bit will be cleared after a power loss event even if
the stopwatch has expired before the code to clear the bit is reached.
Change-Id: Ib2cfdabf4cd4df834395d6a102c6ae70568e71db
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The schematics isn't available for the board, but other L*00 series boards
seem to use a different, compared to T*00 series, GPIO layout.
As it has never been tested, remove the broken driver.
Change-Id: I4bfa02fdbc5da5b556010c2f300faaf6dc845b80
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Configuring the clockgen like vendor bios fixes the issue where the
display wobbles from left to right on the analog VGA output.
Note: This seems to be common issue/requirement on Intel devices from
that generation (also happens on dg43gt).
TESTED on Intel D510MO.
Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19595
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The SPI controller initialization in finalize_chipset was failing
because FSP was setting FLOCKDN before finalize_chipset was called.
Hence move finalize_chipset to get called from BS_POST_DEVICE so that it is
called before FSP notify function-Ready To Boot state.
TEST: run flashrom with -VVV and observe supported opcodes and SPI
flash chip are reported correctly, and write/erase operations succeeed.
Original-Change-Id: I3c0297f3f2258cf77cf00db367f11ff4d1d9dc77
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I690fb4bf9e78bb58811c704179ba8b8f25ce95cc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When resuming from ACPI S3 suspend, EHCI controller
may be in D3 power-management state. Bring it to D0
early so it is functional for console.
NOTE: D3hot->D0 transition was observed to reset
previous programming of PCI_COMMAND register.
Change-Id: Id177ce61926beb057fe67ba42a306d8e565d2657
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Always sanity check for EHCI class device and move
PCI function power enablement up.
Change-Id: I1eebe813fbb420738af2d572178213fc660f392a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There is assumption of static EHCI_BAR_INDEX, try to
clean it up by bringing BAR programming at one spot.
Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Uses common hardware access functions to make smbus block read and
write available in romstage.
Those are needed to reconfigure the clockgen on smbus offset 0x69,
which is sometimes needed for things like CPU C-states or analog
display out to work properly.
Change-Id: I0a06178d2474ce65972de157cb437b42f3354da0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.
This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.
Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This fixes indentation and whitespaces before opening parentheses.
Change-Id: I8940f712c0161419ee0c383b7bc9eb581967366e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Starting with RK3399, PMUGPIO pull registers use the same write mask
format as normal GRF registers, so they need to use RK_CLRSETBITS()
rather than clrsetbits_le32().
BRANCH=None
BUG=None
TEST=boot from scarlet
Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
some gpio irq need to set input pull initialization status
to guarantee to get the right irq trigger. let's add this argument
in gpio_input_irq() function
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
If TTYS0_BAUD is not configured, then by default use baudrate of 115200.
BUG=b:64030366
Change-Id: Ida4c7ae77aba5dfd4ec331e22a54ce43a91bde00
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make DMI data calculation fail-safe to incorrect SPD data.
Change-Id: Ica92850cc77e1f7cbf3e7e44717de42a03b93bbe
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20839
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Decrease the link-frequencies as recommended by Omnivision for OV13858
and OV5670 camera sensors.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
GPP_B8 acts as input to the inverter whose output controls PERST#
signal to wifi module. Out of reset, GPP_B8 is configured as
input by default. Since there is no external pull-down on it, this
line is floating and results in PERST# being asserted until ramstage
where the GPIO was originally configured. Because of this the wifi
chip is not ready during the PCIe initialization step. Move the
configuration of GPP_B8 to bootblock so that wifi device is taken out
of reset as early as possible.
BUG=b:64181150,b:62726961
TEST=Verified with warm reboot and suspend-resume stress test that
wifi is still functional.
Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add gpio.c to bootblock so that the variant early_gpio_table can be
used for configuration in bootblock.
BUG=b:64181150,b:62726961
Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add Cannonlake pci device ids for all the merged intel common code. As
of now only have CNL-U and CNL-Y pci ids.
Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Use the genric GPIO library. Add the required functions.
Also, update the Kahlee mainboard dependency to match.
Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20543
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a hook to allow an optional one-time cbmem_top() initialization.
The new function, cbmem_top_init(), is called on the first expected
initialization of cbmem based on the Kconfig options LATE_CBMEM_INIT
and EARLY_CBMEM_INIT.
Change-Id: I89edd2d11f226217c8e2aaca829b4f375a2cff28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For CAR platforms which don't migrate globals real globals can
be directly used. This alleviates the need to peform partial
recovery on every cbmem access which in turn acts like all non-CAR
platforms or any stages which execute entirely out of RAM.
Change-Id: I31c08dd6473324424d5d42fe6b56d42fe635929e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.
Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.
Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.
Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.
Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Without RELOCATABLE_RAMSTAGE selected, S3 resume will hang under
Linux and Windows. All other Intel SoCs have this selected by
default, so this change simply corrects an omission on Braswell.
TEST: boot Linux on google/cyan with and without RELOCATABLE_RAMSTAGE
selected; observe that S3 resume fails without and succeeds with.
Change-Id: I9071d9b4e3e3a156281d95fae059947c4c26f744
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
IOBP (I/O Buffer Programming) is an interface (indirect addresses space)
in the RCBA that is used to configure the high speed serial lanes on the
PCH, that are used for PCIe, USB3 and SATA.
This patch replaces the offsets in RCBA with the defines from pch.h, gives
the access functions and their parameters useful names and replaces two
magic addresses in IOBP space with their defines.
Change-Id: I91a828ed076ca10733b47db876fabf5adaa63638
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/16214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The cbmem_fail_recovery() function was no longer used. I'm not sure
why the compiler never complained. Regardless, delete it.
Change-Id: I7d94118068064c61252d1b5ca9d8e92658a699e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The code doesn't include much, but when compiled outside the coreboot
build (what the shipped Makefile is made for), we want to make sure that
the few files it includes are controlled by us.
TEST=`cd src/soc/nvidia/tegra124/lp0; make CC=arm-eabi-gcc` works
Change-Id: Ic2f1e4aa4047617b048ef7ef98d71f9d540ccd74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20860
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCI function number takes only 3 bits, therefore
correct bitmask for it is 0x7.
Change-Id: Id41700be0474eecc4d5b5173c4d5686c421735e3
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add support of DMI tables for AMD Opteron 6300 Series Processors.
Correct value for CPU family is taken from SMBIOS reference
specification.
Change-Id: I8c5d487c0f45f61deb081be50c6701a42fbf9111
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This FCH_OEM_CALLOUT bypasses API and uses structures
that are private to AGESA. Attempt to clean it up by
first clarifying when it is used.
Change-Id: I63aa0f586f73e97d615b8596d73728edbaeb0a2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Experiments on f14 f15tn and 16kb suggest that TSC
counter value shifts at end of raminit. To account
for this all previously stored values in timestamp
table are also divided by 4.
Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Boards without AGESA_LEGACY_WRAPPER gain EARLY_CBMEM_INIT.
This does not apply to family12 and family14 just yet, as
they do invalidate without write-back on CAR teardown.
Change-Id: I008356efa2bc3df0ed1f0720e225ecc7e9995127
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In AGESA specification AmdInitEnv() is to be called once
host memory allocator has started. In coreboot context this
could mean either availability of CBMEM or malloc heap.
As for AmdS3LateRestore(), there is no requirement to have
it run as part of the romstage either.
Change-Id: Icc8d97b82df89e2480e601d5c2e094de0365b0a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix over 80 character line warnings, unncessary braces for single
statement blocks warnings, include space before and after =, <, >
warnings, spaces after open parantheses warnings
Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/19987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix remaining space prohibited between function name and open
parenthesis, line over 80 characters, unnecessary braces for single
statement blocks, space required before open brace errors and warnings
in subdirectories of src/cpu/amd/pi
Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In Scarlet pwm regulatoror minimum value and maximum value differs from
other board variants, Correct it so we can get the right voltage.
Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
in Scarlet the Sdcard control gpio differs from other
board variants, So set the GPIO to high on Scarlet.
Change-Id: I5fa19b212a716213462eea58b6242392d32a2c5c
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Scarlet gpio4cd use 1.8V powerdomain, let's make a
correct register setting, otherwise even the uart
does not work.
Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The array of CMOS values that was passed into the read routine was
never getting updated. GCC 7.1 gives a warning on this:
error: may be used uninitialized in this function
Change-Id: I2f7c9b6455761a38598467b001efb0603fd14c32
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add the Google mainboard GPIOs to the ACPI table.
Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC KBC controller was not initialized, so the EC wouldn't put
keys in the output buffer. With nothing in the buffer, vboot didn't
try to boot the USB stick. Add the driver to setup the KBC called by
EC init.
BUG=b:62066405
BRANCH=none
TEST=Boot Kahlee with USB stick and CTRL+U boots the stick.
Change-Id: If9346fda558e802536c7de38da5b21fd25320e40
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20480
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard_ec_init out of mainboard enable to the more
appropriate mainboard init phase.
Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A mainboard may access GPIO in romstage.
Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add ACPI support for the Google EC, which requires GNVS support
for passing information from the EC to firmware and OS.
Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add ACPI asl for global non-volatile storage (GNVS).
Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set up the TPM decode to SPI prior to verstage.
Enable LPC TPM and remove the mock data.
Note, Kahlee TPM is on SPI, but decoded by the LPC block.
BRANCH=none
BUG=b:62103024
TEST=coreboot and Depthcharge reports TPM found.
Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data
to be used in multiple stages and depthcharge. Fixes developer mode
USB boot.
Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set DDI port 2 type to Display Port.
Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Inform AGESA to setup an I2S codec instead of an Azalia codec.
This is step one for audio to work. ASL to connect the
driver and the hardware is in a follow-on patch.
Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/19841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The save_timestamp_to_cmos code was used at Sage before the early
cbmem was available. Update it to use the standard timestamp calls,
based on the rangeley implementation.
Change-Id: I9a3a6609bdc8d03c4b86951daa1cafddd9c1332e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Sync map_oprom_vendev() and autoport with the list of PCI ids in the
`gma.c` driver, remove one obsolete Kconfig default override.
Change-Id: I12f24f415b695c516fbb947114e09c873af2e439
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
For x86, we place the .id section at 4GiB - CONFIG_ID_SECTION_OFFSET.
To take effect, we have to guard the conflicting default placement in
`program.ld`. Also, as we only include the .id section into the boot-
block, guard it by ENV_BOOTBLOCK too.
Change-Id: Idc7cbd670ce4f75b7790ff8d95578683e355ba7e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20810
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
In S3 resume, wifi is one of the wake sources.
If elog is enabled in config, then log wifi wakes in elog.
BUG=b:36992859
TEST= Build for Soraka. Do WoWlan during S3. Verify elog having update
on wake due to Wifi.
Change-Id: I7d42c5c81e0a3f7a3f94c3f6b7d2ebdf029d1aff
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This excludes files which are mostly spaces, which I felt should be
handled separately.
Change-Id: I33043a3090e2fc6e9d2fd81e8a5e46fb6cb0aa35
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
As per discussion with CSME team, ME is NOT using PCI Config
Space register HFSTS2 Bit 10 to update ME power-gated status.
ME goes to CM0-PG state after ME device becomes idle after
Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C)
is being set.
And to retrieve the PG status of ME, one should read from the
PWRMBASE+offset 0x590 (which should give the value 0xF9) and
PWRMBASE+offset 0x594 (which should give the value 0xFF).
But, also it needs some time for the ME FW to go to idle state
and reflect these values in PWRMBASE registers after D0i3 bit
is being set. This does not happen instantly.
So, in coreboot, if we read the ME PG state in finalize.c, which
happens just after FSP Notify phase, where actually ME D0i3 bit
is set, we do not read the correct PG state values (i.e, 0xF9
and 0xFF).
But, once it boots to Kernel, if we read those same registers
through iotool mmio_read32 command, we get correct values.
So, removing the ME PG state prints from coreboot, since it is
actually showing wrong information, although ME Power Gating is
successful.
Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The functionality of the FAN controller is extended to provide a
lowest startup speed of the FAN. Add the parameter "fanmin" to
the fan_ctrl_t structure and initialize the value.
Change-Id: Ib2e093ed6f5fc29bbea879779eb4777eb371b937
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The parameter shall be FANStartSpeed instead of FANStartpeed.
Change-Id: I977da687ba8d9d0bad4c184cd0945ecaa52286ad
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Add ASL for the Elan touchpad driver connection in ChromeOS.
This is based on the Auron and Rambi ASL. The AMD ACPI code
doesn't have the auto table generation the newer Intel
Chrome SOC use.
Device visible to OS: /sys/bus/acpi/devices/ELAN0000
Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clean up the ASL whitespace and formatting to match the iasl -d
style as other parts of coreboot.
Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AMD internal A-link (AAHB device) doesn't support an IRQ,
so remove it. This solves a conflict with the GPIO IRQ required
for touchpad operation.
Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8.
Configure GPP_B8 to drive low.
TEST=Wifi card is detected and connect to an AP.
Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet.
Set continuous mode until the quiet mode feature is available. This
allows keyboard and other EC based interrupts through.
Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19840
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Lijian Zhao