The src/lib/timestamp.c already has an implementation using
timer_monotonic_get() for timestamp_get(). Use that instead
of duplicating the logic.
BUG=chrome-os-partner:44669
BRANCH=None
TEST=None
Change-Id: If17be86143f217445bd64d67ceee4355fa482d39
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: Ieaed5cf76c6f0a6a121e6add731d5c1e1528dfc7
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11375
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Without this change, if one USB3 device is attached when
the board is power up, the USB3 port can not be used.
Change-Id: I98628975000c7d56b1540c2b321d580ace1ef70e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11377
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: Idf28faa26a7ea5e94495af5ff027309df444766e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11376
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This option was removed in the following commit:
* 80f5d5b fsp1_1: remove duplicate mrc caching mechanism
Change-Id: I08ef4fc6029cc066e4f7b9c82b6b187a9794afdb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11462
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The #error messages only say that "CONFIG_* must be defined", which
conveys no more information that the compiler or assembler failing
when it encounters an undefined CONFIG_* symbol.
Change-Id: I6058474d4cd454cfc20290650425d379f388abd9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11461
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
After much consideration, and many years of an EXPERT mode sitting
almost completely unused, we've seen that it doesn't work for us.
There is no standard on what constitutes EXPERT, and most of
coreboot's options Kconfig are expert-level.
We even joked that not selecting "EXPERT" should prevent coreboot
from compiling:
@echo $(shell whoami) is not permitted to compile coreboot
Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11365
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether
or not the payload will actually be SeaBIOS:
1. PAYLOAD_SEABIOS, but payload changed with cbfstool
2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS
et. cetera.
Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11293
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
mainboard_ec_init() wasn't getting run due to an invalid
Kconfig symbol. This check isn't required as the Kconfig
option for the EC is forced to be enabled, and the function
should always be run.
BRANCH=none
BUG=none
TEST=Rebuilt glados mainboard.
Change-Id: I2c4a33d80533a19b02b83b3aaa6a3386e927f1c7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: edd8c7a0666208b35ee81f57ec2626390958dfb7
Original-Change-Id: I2a92fd28347455c09ecf2119788ca9b6a97a11de
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295143
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11435
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the ASL files with the DPTF related settings and the
thermal devices enabled in the SOC. It also enables the DPTF setting
at the global NVS level.
BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.
Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7
Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293391
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11430
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch includes the DPTF specific ASL files in the main
DSDT definition and enables the CPU thermal participant device
in the device tree. It also enables the DPTF flag in the global
NVS table.It also adds the ASL settings specfic to the mainboard.
BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.
Change-Id: I5fb28e4480648eab39cc9b13ed55eae1d3db4d42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 54f7f33a12eb5744d6108e362fa1d078fe838b3c
Original-Change-Id: I82527989919bd4f3c49fb58dfc9463f1c1bd3353
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284821
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294650
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11429
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the macro for GPP_E22_IRQ instead of the ACPI code so it
can be removed.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-sklrvp coreboot
Change-Id: I09bea748fea34072d4f8ad7470d37e423b7f63de
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 89069f5f318329182390cad679511547b7d2a6d5
Original-Change-Id: Iad181b4ce1c557ce8d17645431d8ba6f558bb837
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295171
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11427
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Early(romstage) SPI write protected status read(wpsr) functionality
was broken causing 2 sec timeout issue.Implementing HW Seq based rd
status operation in romstage.
BRANCH=NONE
BUG=chrome-os-partner:42115
TEST=Built for sklrvp and kunimitsu and tested using below command
flashrom -p host --wp-enable [this should enable WP on flash chip]
Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked)
flashrom -p host --wp-disable [this should disable WP on flash chip]
Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked)
Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488
Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677
Original-Signed-off-by: Subrata <subrata.banik@intel.com>
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294445
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11423
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is needed to fix error in depthcharge:
src/vboot/util/flag.c:38 flag_fetch(): Don't have a gpio set up
for flag 3.
BUG=chrome-os-partner:44214
TEST=Verify depthcharge prints EC ID on boot up
BRANCH=None
Change-Id: Ia2d88b8427e54e2dc9e6c9abecc95fd7656abb66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 142b156c72ceedfbd4bf3f54c0cb1128c0fad5a3
Original-Change-Id: I7e7a7d1b92bc1ee2c5ebac8de6946550ddd68a68
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294715
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11421
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the gpio pad configuration prior to SiliconInit()
in case there are dependencies of the pads being configured
in prior to SiliconInit().
BUG=chrome-os-partner:43522
BUG=chrome-os-partner:43492
BRANCH=None
TEST=Built and booted glados.
Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9
Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294642
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11420
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On proto2 boards the kepler device has its reset line pulled up
to one of its IO rails with a zener in between. This results in the
device not being visible at MemoryInit() time because for some
reason FSP is doing PCIE configuration/probing in that path. Hack
around the broken FSP logic by configuring the pads for kepler's
power and clkreq.
BUG=chrome-os-partner:44326
BRANCH=None
TEST=Built and booted glados. lscpi shows the device on bus 2.
Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2
Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294810
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11419
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Export the proper GPIO for EC_IN_RW so it can be picked up and
used by depthcharge/vboot.
BUG=chrome-os-partner:43072
BRANCH=none
TEST=build and boot on glados P2
Change-Id: I32d338ef424086ec9701900e976bd0dffe4637a0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: dd983c84de0c3b896b20d38438a3285cfcaf7e56
Original-Change-Id: I77f7d3a0c0d733302b81273d96026d39b001ed19
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294712
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11418
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The RMT flag that was attempting to disable saved training to
force a full memory train was happening too late. In testing
I was actually hitting a case where FSP was training every time
but it was not because it was properly being told to.
This moves the check of the RMT flag from devicetree to happen
ealier, before it is actually consumed by romstage_common().
BUG=chrome-os-partner:40635
BRANCH=none
TEST=do both power off+on and warm resets to ensure that FSP
is doing a full memory train every time with RMT enabled.
Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7
Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294177
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11417
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The previously driven TX state of the buffer was not
being cleared before or'ing in the new value. Fix this
oversight.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados. Also dumped assembly and saw the
masking happen.
Change-Id: I74ea469564d37d6b29e9481b0ea704f04f54ac30
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: d399e8b32b30b8b2275bb6ff8dd24f7d5cfeadda
Original-Change-Id: I341b396af5de20ffeeb2e42066b224dd54251793
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294541
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11416
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
RMT is useless if the memory does not do a full training pass,
and since FSP does not seem to handle that case itself have
coreboot not pass in a valid set of saved training data so FSP
will do a full memory train.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot twice on glados with p2 and RMT enabled
and see it do a full memory train on each boot.
Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6
Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294067
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SOC handler for memory init params is only taking UPD
as an input which does not allow it to use romstage_params.
In addition the UPD input is called params which is confusing
so rename it to upd so romstage_params can be passed properly.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2
Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a
Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294066
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11413
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The BUNIT controls the policy for read/write access to physical
memory. For the SMRAM range the policy was not allowing dirty
evictions to the SMRAM when the core causing the eviction was not
in SMM mode. This could happen when the SMM handler dirtied a line
and then RSM'd back into non-SMM mode. The cache line was dirtied
while in SMM mode, but when that particular cache line was evicted
it would be silently dropped. Fix this by allowing the BUNIT to honor
writes to the SMRAM range while the evicting core is not in SMM mode.
The core SMRR msr provides the mechanism for disallowing general access
to the SMRAM region while it is not in SMM mode.
BUG=chrome-os-partner:43091
BRANCH=None
TEST=Run suspend_stress_test and ensure there is no hang SMI handler
on suspend-path.
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Change-Id: Ie794aa3afd54b5e21d0d59a2a7388d507f233537
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 9c481ab339b4e5ab063e2c32b1f0a48b521142b2
Original-Change-Id: I3e7d41c794c6168eb2ad4eb047675bdb1728f72f
Original-Reviewed-on: https://chromium-review.googlesource.com/292890
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: http://review.coreboot.org/11412
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CBFS_SIZE is living as a mainboard attribute. Because
of the Kconfig include ordering the SoC *cannot* set
the default.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=None
Change-Id: If34e8fd965573fdc7f57b63201dbcb5256e132d6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a820b11a0aa3b820c79b1f76b15370d969153175
Original-Change-Id: I7ba637e66878f5ae9caedb63fdd37ed7e375224e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289832
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11410
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We don't need the code in romstage, and it saves us a few #ifdefs.
Change-Id: I26d867566f07c7d80890cd01bf055be7497130d3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11457
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It doesn't make sense to die() when printing information. In fact the
die() are protected by DISPLAY_HOBS config option. This can get
confusing, so replace die() calls with printk().
Also since these messages are designed to be informational, keep them
at BIOS_INFO log level.
Change-Id: Id75b9a54f4aea23074a7489d12809cc2da05f1cd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11456
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For some reason fsp 1.1 has a duplicate mechanism for saving
mrc data as soc/intel/common. Defer to the common code as all
the existing users were already using the common code.
BUG=chrome-os-partner:44620
BRANCH=None
TEST=Built and booted glados. Suspended and resumed.
Change-Id: I951d47deb85445a5f010d23dfd11abb0b6f65e5e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Original-Commit-Id: 2138b6ff1517c440d24f72a5f399bd6cb6097274
Original-Change-Id: I06609c1435b06b1365b1762f83cfcba532eb8c7a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295236
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11454
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The code in mrc_cache.c doesn't check for the presence of 'mrc.cache',
and just returns hardcoded value for he location of he MRC cache. This
becomes a problem when there is a CBFS file at the same location,
which can get overwritten. A CBFS file is created to cover this region
so that nothing can be added there.
This has the advantage of creating a build time error if another cbfs
file is hardcoded over the same region.
The default location of the MRC cache is also moved to 4G - 128K to
ensure that it defaults to something within CBFS.
Change-Id: Ic029c182f5a2180cb680e09b25165ee303a448a3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11440
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Aaron Durbin found that soc/common is already included as a subdir via
the wildcard in Makefile.inc:
subdirs-y += $(wildcard src/soc/*/*)
Since the entire file is protected by CONFIG_SOC_INTEL_COMMON, there
is no problem with including it for every platform. On the other hand,
when it is included by the skylake and braswell makefiles, any rule is
duplicated. As a result fix the braswell and skylake makefiles.
Change-Id: If5bad903c78dbce418852935ee55cdc7162b3b2d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11439
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This patch adds support to enable a linker workaround to a hardware
erratum on some early Cortex-A53 revisions. Since the linker option was
added very recently, we use xcompile to test whether the toolchain
supports it first. It is also guarded by a Kconfig since only a few
ARM64 SoCs will need this and it incurs a performance penalty.
BRANCH=none
BUG=none
TEST=Turned it on or off for Smaug and confirmed that it (dis)appeared
in verbose make output accordingly.
Change-Id: I01c9642d3cf489134645f0db6f79f1c788ddb00d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 57128785760c4dfa32d6e6d764756443a9323cb7
Original-Change-Id: Ia5dd124f484e38460d75fb864304e7e8b18d16b7
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294745
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11403
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Fix following compilation error.
LINK cbfs/fallback/verstage.debug
/bin/sh: verstage-objs: command not found
/usr/x86_64-pc-linux-gnu/aarch64-cros-linux-gnu/binutils-bin/2.24/ld.bfd.real: warning: cannot find entry symbol stage_entry; defaulting to 00000000000d7000
BRANCH=chromeos-2015.07
BUG=none
TEST=emerge-oak coreboot
Change-Id: I30e4c43625b2d1d076f24e8c2639ce951839661b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 2a8936cdf34d315f580819df682335b2998f044f
Original-Change-Id: I9afd57a5a868a348dff2c66cad0a8a09cdb2e911
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292557
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11402
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Need to save EmcBctSpare2 field to scratch register. Without it,
system may not resume from LP0 suspend.
BUG=chrome-os-partner:43797
BRANCH=none
TEST=able to suspend/resume >30 times on a known failed board
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 6d1623c4c791f79e097193dfbc4bc894ef63e230
Original-Change-Id: I53ebf8c4d4c7cd19827128a84fbd97a377d78ff7
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294765
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-(cherry picked from commit ce38d902e889068d0068150c9352c2ecdb2f8815)
Original-Reviewed-on: https://chromium-review.googlesource.com/294864
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Change-Id: I2ff21afbe9278413033101877c2581df51913709
Reviewed-on: http://review.coreboot.org/11401
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
GPIO(0, B, 3) and GPIO(7, C, 5) are not actually connected,
GPIO(0, B, 4) is named differently.
BUG=chrome-os-partner:43031
TEST=Rialto should still boot just fine, USB should still work
BRANCH=master
Change-Id: I11879385de6e9b57ac28bcae699333beb5a0d64c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a66bf1fd73ff8d15d4ec1a8f3602465941285c32
Original-Change-Id: Ib7d2baa6ed1ab38db786eb4d5e77316ad72cbfd4
Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294713
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11400
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Without this, the leds would be stuck to whatever the pullup/down states the
pins come with on rk3288.
Ready2_LED, an orange led, is one of the leds in this state.
This might confuse some users thinking there's an error.
Turn all of them on instead.
Later on depthcharge will use the same LEDs to indicate dev mode status.
BUG=chrome-os-partner:44274
BRANCH=master
TEST=Boot firmware without anything else, note all leds on
Change-Id: I5cf19aabd2a59a61699ef491ae11424cf5a0c874
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 2e1a332a5653fb76bbf8fe624274ec64d2b443a5
Original-Change-Id: I4c4e8940dd9cf1ac0301ac00bfc5992ba16e1589
Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294065
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11398
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
only modify the MR3 value, there will always be some mickey not working properly.
After enable ODT, we use many mickey do tests, now functioning properly.
BRANCH=None
BUG=chrome-os-partner:43626
TEST=My mickey now boots up
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 681c169d59f5638d35b777eb2b7543e3b0dd90c8
Original-Change-Id: Ieb2b8a56054f91b6be81260e4c574425fb72fed3
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293324
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Commit-Queue: Douglas Anderson <dianders@chromium.org>
Original-Trybot-Ready: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-(cherry picked from commit 5397c2f32f5851b9f514b0bd2ae68999a77cabbf)
Original-Reviewed-on: https://chromium-review.googlesource.com/294126
Change-Id: Icb3c839bebebfcae54fc6e96e9958c7020d49eff
Reviewed-on: http://review.coreboot.org/11396
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
do_dcsw_op is coded as a label, it's possible that linker will place
do_dcsw_op on unaligned address. To avoid this situation, we declare
do_dcsw_op as a function. Also explicitly set the 2nd argument of
ENTRY_WITH_ALIGN(name, bits) to 2.
do_dcsw_op:
cbz x3, exit
c103d: b40003e3 cbz x3, c10b9 <exit>
mov x10, xzr
c1041: aa1f03ea mov x10, xzr
adr x14, dcsw_loop_table // compute inner loop address
BRANCH=none
BUG=none
TEST=build and check do_dcsw_op in elf file
Change-Id: Ieb5f4188d6126ac9f6ddb0bfcc67452f79de94ad
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 4ee26b76089fab82cf4fb9b21c9f15b29e57b453
Original-Change-Id: Id331e8ecab7ea8782e97c10b13e8810955747a51
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293660
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: http://review.coreboot.org/11395
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When power is cut/restored to audio block, mbist workaround must be reapplied
or I2S will not function. Handle this in lp0 resume firmware with the rest of
the mbist WAR. This sequence for audio is also present in boot block code for
T210.
BUG=chrome-os-partner:41249
BRANCH=None
TEST=lp0 suspend/resume with audio playback
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 84933da8188f8263c19f38ba37e88e32ca46cb3d
Original-Change-Id: Ia6432e8556ee64f528d94f2dc3279b152294e132
Original-Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293618
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Anatol Pomazau <anatol@google.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Anatol Pomazau <anatol@google.com>
Original-Tested-by: Anatol Pomazau <anatol@google.com>
Original-(cherry picked from commit 1e529c3e2ff929975fd654ef75396bc98d3b785c)
Original-Reviewed-on: https://chromium-review.googlesource.com/293886
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Change-Id: I3e72bc10f7e2bea2fa5f946e25803a7928ce9276
Reviewed-on: http://review.coreboot.org/11394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Due to HDMI need to set dclk_rate to 27Mhz, and we can't
caclu a suitable config paramters for this rate, so we
need to multiple rate unless the vco larger then VCO_MAX.
When NPLL rate multiple to 54MHz, pll_para_config could
caclu a right paramters, and I have verify the clock jitter
is okay to HDMI output.
Jitter Reports:
Dclk Rate NPLL Rate nr/no/nf jitter Margin
27MHz 54MHz 2/10/45 449.0ps +51.0%
BRANCH=None
BUG=chrome-os-partner:42946
TEST=Mickey board, show right recovery picture on TV,
and 480p clock jitter test passed
Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c
Original-Reviewed-on: https://chromium-review.googlesource.com/288416
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290331
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If an HDMI display is detected (EDID can be read), set the
display mode to 480p. If for some reason 480p is not supported
then we'll fall back to the automatically detected display mode.
BUG=chrome-os-partner:42946
BRANCH=firmware-veyron
TEST=dev mode screen shows up on Mickey at 480p resolution
Change-Id: I2c431eff6673392d3c09e1b66c66ba12ecc6eeb0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 76203a683c4501f368c50fe24101f68746ddb7f0
Original-Change-Id: I90dea37daa2d78628230d7d47f7ef0e917cbd7bb
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290554
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11392
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Assume that HDMI implies usage of an external display, and that we
want to try bringing up display if we can read an EDID.
BUG=chrome-os-partner:42946
BRANCH=firmware-veyron
TEST=none; need a display with corrupt EDID to test with
Change-Id: I11cc61140d905d70798a7b46db7847f3a1b3c886
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: ace7773623eac57f068ecd50baa9108ce028cf1b
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I9e22984a98b1a5f8cd9645b92dc9b87e8d968f01
Original-Reviewed-on: https://chromium-review.googlesource.com/293548
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11391
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch will let you to choose a favourite mode to
display, while not just taking the edid detail timing.
But not all modes are able to set, only modes that
are in established or standard timing, and we only
support a few common common resolutions for now.
BUG=chrome-os-partner:42946
BRANCH=firmware-veyron
TEST=tested dev mode on Mickey at 640x480@60Hz
Change-Id: I8a9dedfe08057d42d85b8ca129935a258cb26762
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 090583f90ff720d88e5cfe69fcb2d541c716f0e6
Original-Change-Id: Iaa8c9a6fad106ee792f7cd1a0ac77e3dcbadf481
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289671
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This ensures the output buffer is initialized before exiting
decode_edid() so that if the return value is ignored in higher-level
logic (like when dealing with external displays) we don't leave
the struct filled with garbage.
BUG=chrome-os-partner:42946
BRANCH=firmware-veyron
TEST=none
Change-Id: I557e2495157458342db6d8b0b1ecb39f7267f61f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: bb12dca133576543efa4d3bcc9aadf85d37c8b71
Original-Change-Id: I697436fffadc7dd3af239436061975165a97ec8c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293547
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11389
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This replaces various timing mode parameters parameters with
an edid_mode struct within the edid struct.
BUG=none
BRANCH=firmware-veyron
TEST=built and booted on Mickey, saw display come up, also
compiled for link,falco,peppy,rambi,nyan_big,rush,smaug
[pg: extended to also cover peach_pit, daisy and lenovo/t530]
Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9
Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289964
Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11388
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There are serveral members of the edid struct which are never used
outside of the EDID parsing code itself. This patch moves them to a
struct in edid.c. They might be useful some day but until then we can
just pretty print them and not pollute the more general API.
BUG=none
BRANCH=firmware-veyron
TEST=compiled for veyron_mickey, peppy, link, nyan_big, rush, smaug
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I660f28c850163e89fe1f59d6c5cfd6e63a56dda0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: ee8ea314a0d8f5993508f560fc24ab17604049df
Original-Change-Id: I7fb8674619c0b780cc64f3ab786286225a3fe0e2
Original-Reviewed-on: https://chromium-review.googlesource.com/290333
Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11387
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The value of 0x4 (60 Ohm) apperas to be causing lots of problems.
Since 0x1 (34.3 Ohm) was _almost_ right, let's try 0x2 (40 Ohm) and
hope it's the sweet spot.
BRANCH=None
BUG=chrome-os-partner:43626
TEST=My mickey now boots up
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 06db96e00d39972edbaf8429cbe88bbc66804e15
Original-Change-Id: If8b7d51d058ae000c0af189a648c62fa38a872ac
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291121
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-(cherry picked from commit 0dabadca1ab3bb310f85646d020bdcf672014071)
Original-Reviewed-on: https://chromium-review.googlesource.com/291291
Change-Id: Id32790c894c09616e32503aa790fa294093eca8a
Reviewed-on: http://review.coreboot.org/11386
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This basically does the same thing for firmware what CL:290631
did in the kernel. We want to keep the modem off until it needs
to be used to avoid enumeration/detection issues.
BUG=chrome-os-partner:43271
BRANCH=none
TEST=needs testing
Change-Id: I3b63a77c732dc4895b728b30f1dd71210a9c0e90
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a90ccd7fbffe44abe05e96341cc77067442c85e4
Original-Change-Id: I3516de1ea9160f7186ad7f5fb3b5d29ac73143b5
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290890
Original-Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-on: http://review.coreboot.org/11385
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The NV security team requested that coreboot allocate a 128MB
region in SDRAM for VPR (Video Protection Region). We had
previously just disabled the VPR by setting BOM/SIZE to 0.
Once allocated, the VPR will be locked from further access.
The ALLOW_TZ_WRITE_ACCESS bit is _not_ set, as dynamic VPR config
is not supported at this time (i.e. trusted code can _not_ remap
or resize the VPR).
BUG=None
BRANCH=None
TEST=Built and booted on my P5 A44. Saw the VPR region in the
boot spew (ID:3 [f6800000 - fe800000]). Dumped the MC VideoProtect
registers and verified their values.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a7481dba31dc39f482f8a7bfdaba1d1f4fc3cb81
Original-Change-Id: Ia19af485430bc09dbba28fcef5de16de851f81aa
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/290475
Original-Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Hridya Valsaraju <hvalsaraju@nvidia.com>
Original-(cherry picked from commit 9629b318eb17b145315531509f950da02483114f)
Original-Reviewed-on: https://chromium-review.googlesource.com/291095
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Change-Id: I19a93c915990644177c491c8212f2cf356d4d17d
Reviewed-on: http://review.coreboot.org/11384
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BL31 makes an assumption that TZDRAM always starts at its base. This
was not true in our case since coreboot page tables were located
towards the start of TZDRAM. Instead move page tables to the end, thus
satisfying the assumption that BL31 base is the base of TZDRAM as
well.
BUG=chrome-os-partner:42989
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: aabed336da6e9aea426650c5ca5977ccfc83a21b
Original-Change-Id: Ic4d155525dbb4baab95c971f77848e47d5d54dba
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291020
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-(cherry picked from commit a57127f1655ef311b82c41ce33ffc71db5f9db35)
Original-Reviewed-on: https://chromium-review.googlesource.com/290987
Change-Id: Ie7166fd0301b46eb32f44107f7f782c6d79a278c
Reviewed-on: http://review.coreboot.org/11383
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The NV security team requested that coreboot allocate the NVDEC
and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB)
and TSEC (2 regions, splitting 2MB), and set their lock bits.
Kernel/trusted code should be able to use the regions now.
Note that this change sets the UNLOCKED bit in Carveout1Cfg0
and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files
(both 3GB and 4GB BCTs) so that the BOMs can be written.
Any future revisions to these BCT files should take this
into account.
BUG=None
BRANCH=None
TEST=Built and booted on my P5 A44. Saw the carveout regions
in the boot spew, and CBMEM living just below the last region
(TSEC). Dumped the MC GeneralizedCarveoutX registers and
verified their values (same as BCT, with only BOM/CFG0 changed).
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23
Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/290452
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60)
Original-Reviewed-on: https://chromium-review.googlesource.com/291081
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5
Reviewed-on: http://review.coreboot.org/11381
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Struct edid defien pvsync & phsync as an character,
like '+' or '-', so we need to check sync polarity
by comparing with characters '+' and '-' instead of
treating as boolean.
BRANCH=None
BUG=chrome-os-partner:42946
TEST=Mickey board, light monitor normally
Change-Id: I92d233e19b6df8917fb8ff9a327ccb842c152d65
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 2d22d4b6e7108474f67200e0fb1e4894cd88db85
Original-Change-Id: I14c72aa8994227092a1059d2b25c1dd2249b9db1
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/289963
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It doesn't hurt to expose declarations. Instead of
a compile-time error there'll be a link error if someone
tries to malloc() anything.
Change-Id: Ief6f22c168c660a6084558b5889ea4cc42fefdde
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11406
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Do not guard the inclusion of "drivers/intel/gma/int15.h"
and "arch/interrupt.h" with configs that control option rom execution.
These headers already have the proper guards. The
install_intel_vga_int15_handler() is unconditionally called, even when
the header that declares it is guarded out.
Change-Id: Ia273437486f5802aa2b53212f2a1b5704c9485fa
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11379
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This seems like more of a debug option, than something that should
be forced to be enabled by the platform. Since it's causing a Kconfig
warning, I'm just removing it.
The alternative to removing it would be to add dependencies on
CONSOLE_CBMEM && !CONSOLE_SERIAL
Change-Id: Ifc4e4cbeea08a503c38827dd75e0e2e78e8a5eda
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11343
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The acpi_fill_ssdt_generator function pointer is evaluated for
each device. As there are multiple cpus in the system the
acpi_fill_ssdt_generator was being called more than once creating
duplicate ACPI entries because there was more than 1 cpu device.
Fix this by only generating them once by removing the
acpi_fill_ssdt_generator for the cpu devices, but add the
generator to the cpu cluster device.
BUG=chrome-os-partner:44084
BRANCH=None
TEST=Built and booted on glados. Noted ACPI entries only generated once.
Original-Change-Id: I695c30e6150f6d3a79d13744c532f1b658b10402
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294240
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Change-Id: I7c85f44ba65398bda668e13db8be531535a983c5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11285
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The prior implementation of PAD_CFG_GPI kept the pad
ownership as ACPI. The gpio driver in the kernel then
wouldn't allow one to export those GPIOs through sysfs
in /sys/class/gpio. Fix this by setting the ownership
to GPIO.
BUG=chrome-os-partner:44147
BRANCH=None
TEST=Built and boot glados. PCH_WP gpio is properly exported
by crossystem.
Original-Change-Id: I9fc7ab141a3fd74e0ff8b3ff5009b007b8a0d69b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294081
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ifbb61c5d64bb6a04f140685c70f4681e2babecef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11283
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Move all the various places that look at board specific GPIOs into
the mainboard gpio.h so it can be easily ported to new boards.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2
Original-Change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293942
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I93c4dc1795c1107a3d96e686f03df3199f30de8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11282
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Implement the required Chrome OS specific handlers to read the
recovery mode, clear the recovery mode, read the lid switch state,
and read the write protect state using the appropriate methods.
Also update the Chrome OS ACPI device to use the GPIO definitions
that are exposed now by the SOC.
BUG=chrome-os-partner:43515
BRANCH=none
TEST=build and boot on glados and successfully enter recovery mode
Original-Change-Id: Ifd51c11dc71b7d091615c29a618454a6a2cc33d7
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293515
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia6ef83a80b9729654bc87bb81bd8d7c1b01d7f42
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11281
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a helper function to read the EC switch state on LPC based
ECs instead of having each board need to understand and use the
specific EC LPC IO method that is required.
BUG=chrome-os-partner:43515
BRANCH=none
TEST=build and boot on glados
Original-Change-Id: Id046c7ddf3a1689d4bf2241be5da31184c32c0e1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293514
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id11009e0711b13823e4f76dc9db9c9c20abf4809
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11280
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The part number was the same as the H9CCNNNBLTLAR which means it
is not possible to distinguish the two based on part number alone.
This breaks mosys and thus the factory tests.
BUG=chrome-os-partner:43514
BRANCH=none
TEST=boot on glados P2 SKU3 and verify memory reported by mosys
Original-Change-Id: I606ef3989bd7273d134a258bc933088ccc865542
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293513
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7cea7cc4c61a20fda47673c8e25c431d391aa3bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11279
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add the ELAN touchscreen device in ACPI to bind it to the I2C
device at bus I2C0, address 0x10, interrupt 31 (GPP_E7).
BUG=chrome-os-partner:43514
BRANCH=none
TEST=boot on glados P2 and see touchscreen initialized by kernel
Original-Change-Id: I23b071b2767547baed239c94216cda6162d045dd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293512
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8a9492e6fa1f650cef0871329ae8944caffdaf5a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11278
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Clean up the device code for the glados mainboard, using
the defined values for interrupts by the SOC and moving the
various codec i2c addresses to the top of the file.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados
Original-Change-Id: Iead1aeb54363b15a6176d4f4a9511674195c0505
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293511
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I083c9ef6140e20a433cb2017e4c3cbc7a41e8fed
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11277
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patche enables the deep S5 and disables Deep S3.
Kunimitsu does not resume from deep S3. This change will
unblock the S3 resume path on kunimitsu board.
BRANCH=None
BUG=chrome-os-partner:42331
TEST=Built and booted on kunimitsu; check s3 works.
Original-Change-Id: Ia828a39bceef615fd194bb3614ba2de87c3af805
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291250
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I07b95a324a27ab658e80674686b47b86412ea097
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11274
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
RISCV requires a trap handler at the machine stage to deal with
misaligned loads/stores, as well as to deal with calls that a linux
payload will make in its setup. Put required assembly for jumping
into and out of a trap here to be set up by the bootblock in a later
commit.
Change-Id: Ibf6b18e477aaa1c415a31dbeffa50a2470a7ab2e
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11367
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
With VIRTUAL_DEV_SWITCH moved under 'config CHROMEOS' in all of the
mainboards, this is no longer needed.
Change-Id: I5fbea17969f6b0c3b8a5dcd519ab9d36eb2ad6f1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11337
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the CHROMEOS dependent symbols VIRTUAL_DEV_SWITCH and
VBOOT_DYNAMIC_WORK_BUFFER under the CHROMEOS config options for the
mainboards that use them.
Change-Id: Iad126cf045cb3a312319037aff3c4b1f15f6529d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Add 'select MAINBOARD_HAS_NATIVE_VGA_INIT' which is just used as a gate
symbol to display MAINBOARD_DO_NATIVE_VGA_INIT to the mainboards that
are already selecting MAINBOARD_DO_NATIVE_VGA_INIT.
Since MAINBOARD_HAS_NATIVE_VGA_INIT is not used in any code, this should
not have any other effects.
This fixes the warning:
warning: (BOARD_SPECIFIC_OPTIONS) selects MAINBOARD_DO_NATIVE_VGA_INIT
which has unmet direct dependencies (VENDOR_ASUS && BOARD_ASUS_KFSN4_DRE
|| MAINBOARD_HAS_NATIVE_VGA_INIT)
Change-Id: I8ceee69ebae90dc32f55df58c2e80fe25397f049
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere
it existed.
Remove the Kconfig symbol and get rid of the #if statements
surrounding the code.
This fixes the Kconfig warning for Haswell & Broadwell chips:
warning: (NORTHBRIDGE_INTEL_HASWELL &&
NORTHBRIDGE_INTEL_SANDYBRIDGE &&
NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE &&
NORTHBRIDGE_INTEL_IVYBRIDGE &&
NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE &&
CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN
which has unmet direct dependencies
(CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989)
Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11270
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When the check for global symbols in romstage happens, if everything is
good, a warning appears, telling us that the segment is empty. While the
empty segment is good, the warning is distracting:
"BFD: build/cbfs/fallback/romstage_null.debug: warning: Empty loadable
segment detected, is this intentional ?"
This change hides that particular warning, but shouldn't hide any other
output from objcopy.
Change-Id: If22489280712d02a61c3ee5e0cb2a53db87d6082
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11302
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
The AMD K8 northbridge uses the Kconfig symbol QRANK_DIMM_SUPPORT,
but the symbol was used on a number of Family 10 boards as well.
AMD Family 10 doesn't use this Kconfig symbol for anything.
I verified that the symbol wasn't used actually getting used in any
of these platforms.
Fixes Kconfig warnings for these 19 mainboards:
warning: (BOARD_SPECIFIC_OPTIONS...) selects QRANK_DIMM_SUPPORT which
has unmet direct dependencies (NORTHBRIDGE_AMD_AMDK8)
Change-Id: I454992a4975566fd6439a21f5a800d0cfa1b4d3b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11300
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Add CHROMEOS dependencies to selects for the following Kconfig
symbols:
CHROMEOS_RAMOOPS_DYNAMIC
CHROMEOS_RAMOOPS_NON_ACPI
CHROMEOS_VBNV_CMOS
CHROMEOS_VBNV_EC
CHROMEOS_VBNV_FLASH
EC_SOFTWARE_SYNC
LID_SWITCH
RETURN_FROM_VERSTAGE
SEPARATE_VERSTAGE
VBOOT_DISABLE_DEV_ON_RECOVERY
VBOOT_EC_SLOW_UPDATE
VBOOT_OPROM_MATTERS
VBOOT_STARTS_IN_BOOTBLOCK
WIPEOUT_SUPPORTED
This gets rid of these sorts of Kconfig errors:
warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has
unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS)
Note: These two boards would never actually have CHROMEOS enabled:
intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out
google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS
Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11272
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CHROMEOS is a user-visible bool. It must not be 'select'ed in Kconfig.
That's why we have MAINBOARD_HAS_CHROMEOS. This is the fifth time I
find this being used wrong.
Why is this confusing/so hard to get right?
Change-Id: Icb4629355c63508f5a044b46842524b3d203c2da
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11290
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory
regions reserved by fsp for chipset use. With that being removed, the
function needs to properly walk though the memory map resulted from fsp
memory init to find out the usable address for cbmem root.
Refer the FSP 1.3.0 Integartion guide for more details on the Memory
Map.
systemagent should also use the same mechanism to create the reserved
RAM resource.
BRANCH=None
BUG=None
TEST=Build and Boot kunimitsu (FAB3)
CQ-DEPEND=CL:*226035,CL:*226045,CL:291573
Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291611
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: http://review.coreboot.org/11239
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(1) Wifi is connected on RP1 which is 1c.0 , so enabling
1c.0 and disabling 1d.0
(2) kepler is on RP5 which is 1c.4, so enabling it
(3) enabling ClkReqSupport for RP1 and RP5 so that L1 substates can
get enabled.
BRANCH=None
BUG=chrome-os-partner:43738
TEST=Built and boot for Kunimitsu. checked all PCIe powersaving
states (LTR, L1, L1S) are enabled
Original-Change-Id: I525661399d1a4d939b53d5ed5f7991598b84ddcd
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293482
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ib9a771a6ec137217668fb0385efc13b1824772b4
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/11237
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The skylake IO-APIC supports up to 120 redirection entries.
In practice it seems FSP has already written to this write-once
register. However, it doesn't hurt to actually be correct within
the source.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I666b1b6034f0d37a37ea918f802317f9d5f15718
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293251
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I6ddbc89c98c262e2dd0f9f0b76adb092d3043602
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The skylake SoC code now has macros for the previously
hard-code numbers for IRQs and GPEs. Switch over to using
those as they bring a little more clarity.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Ic8fcc59d680cdddec9dfbc3bf679731f6d786793
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293411
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I594907005372100a3c9d17dda9d17769844ad272
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11234
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
One thing that is brittle is lining up GPE0 bits in ASL
and with a board's design proper. This results in open
calculated magic numbers. To help alleviate this provide
just #defines that C preprocessor can use before handing
the source off to the ASL compiler.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados. Everything's intact.
Original-Change-Id: I359616ebe4bfc83c05bafe0ca36b766efd16dcca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293410
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I32513c324b923fa0adbd6a0ee920c27e9b97dd1b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11233
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The location of the AMD ROMSIG binary was being checked and warnings
were being printed even when the ROMSIG file wasn't being used.
These false warnings are avoided by moving the warnings into the
block where the CBFS file for the ROMSIG is generated.
Change-Id: Ie44a2ad97ff3b15df6dc9b8166992de6ed837997
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11161
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Commit 27baa32 (cpu/amd/model_10xxx: Do not initialize SMM memory if
SMM is disabled) deactivated TSeg SMRAM, which had the side effect
of routing legacy VGA memory access to DRAM. Restore the correct
MMIO mapping via the MMIO configuration registers.
TEST: Booted KGPE-D16 with nVidia 7300LE card and verified proper VGA
functionality.
Change-Id: Ie4b7c0b2d6f9a02af9a022565fe514119513190a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11240
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Broadwell and Skylake chipsets, along with a few mainboards were
selecting ALWAYS_LOAD_OPROM without making sure that the dependency
for that symbol was met as well.
Looking at the dependencies for VGA_RUN_ROM, we see:
PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT
Since ARCH_X86 selects PCI, that's always met here.
Since Broadwell and Skylake don't have native VGA init yet, that's
not needed.
- Make sure that VGA_RUN_ROM is selected as well.
- Add dependency on !PAYLOAD_SEABIOS for both ALWAYS_LOAD_OPROM and
VGA_RUN_ROM symbols where they're selected.
Fixes Kconfig warning for these boards and chipsets:
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS)
selects ALWAYS_LOAD_OPROM which has unmet direct dependencies
(VGA_ROM_RUN)
Change-Id: I787a87e9467e1fc7afe8b04864b2a89b54824b9f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11246
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change the dependency on CONSOLE_SERIAL to select CONSOLE_SERIAL based
on this question.
The dependency was causing multiple warnings on every platform tested.
src/console/Kconfig:21:error: recursive dependency detected!
src/console/Kconfig:21: symbol CONSOLE_SERIAL depends on
DRIVERS_UART_8250MEM
src/drivers/uart/Kconfig:16: symbol DRIVERS_UART_8250MEM is selected by
UART_DEBUG
src/soc/intel/skylake/Kconfig:198: symbol UART_DEBUG depends on
CONSOLE_SERIAL
Change-Id: Ia0426cd150561694081b5ea7c6797d36022c1f57
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11243
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
When the user's primary group contains a space ls -l and awk get the
wrong value for the file size. This results in padding the
coreboot_psp_directory_combine_pubkey.bin file too much which ultimately
means RtmPubSigned.key can not be placed at the necessary offset.
Changing from ls -l to ls -ln seemed like the most minimal,
POSIX-friendly way to effect this change.
Change-Id: Icbeaad476753924626adb6de53dc9a30052d91a6
Signed-off-by: Dan Christensen <opello@opello.org>
Reviewed-on: http://review.coreboot.org/11242
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In order for the EC_SCI_L to work the GPE0 route needs
to be set along w/ the GPE event for the EC. As the GPE0
route is dynamic the EC_SCI_GPI needs to be set along
with the route so everything lines up. In this case, the
GPE0 route is set to the defaults such that GPP_C, GPP_D,
and GPP_E are routed to GPE0 block 0, 1, and 2, respectively.
This works out for glados because the EC_SCI_L is connected
to GPP_E16.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados. The 'acpi' interrupt in /proc/interrupts
is incrementing as well as /sys/firmware/acpi/interrupts/gpe50.
Original-Change-Id: I71fc4bec124f3ac87453a099412154e67aba6280
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/292011
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Idbb6d29364655537abc9ae6f012b3abb38edf138
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11210
Tested-by: build bot (Jenkins)
Set the EC_SMI_GPI define to be GPP_E15 and route that
GPIO for SMI generation. Also, the mainboard_smi_gpi_handler()
was introduced on skylake in order to process any GPI that could
generate an SMI. Switch to this handler so one can process the
appropriate events.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Used 'lidclose' on EC command line during depthcharge
to confirm EC_SMI_L generates SMI and shutdown happens.
Original-Change-Id: Ia365b86161670a809e3fa99dde38fccc612d5e77
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291934
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ic16ea8e8d6ff564977ed2081d2353c82af71adea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The current construction for processing SMI GPI events
didn't allow for the mainboard to query the state of a
particular GPI for the snapshotted SMI event. The
skylake part can route GPIs from any (there are design
limitations) GPIO group. Those status and enable registers
are within the GPIO community so one needs to gather
all the possibilities in order to query the state.
The call chain did this:
southbridge_smi_gpi(
clear_alt_smi_status() -> reset_alt_smi_status() ->
print_all_smi_status() -> return 0)
As a replacement the following functions and types are
introduced:
struct gpi_status - represent gpi status.
gpi_status_get() - per gpi query on struct gpi_status
gpi_clear_get_smi_status() - clear and retrieve SMI GPI status
mainboard_smi_gpi_handler() - mainboard handler using gpi_status
Also remove gpio_enable_all_smi() as that construct was never
used, but it also is quite heavy handed in that it would
enable SMI generation for all GPIs.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built.
Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291933
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The first pass of the GPIO configuration patch didn't
enable the SMI# generation for GPIs marked as SMI
routed. Now when a pad is configured as SMI routed
the bit for the SMI enablement is set accordingly.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados. Confirmed SMI_EN being set
for SMI routed GPIOs.
Original-Change-Id: I796b68accb7a49b03ef18539861e72fa9d169c26
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/292010
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I3be770234d3f605ae630ecd5cd4cfe4867243999
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The gpio pad configuration currently defaults to ACPI
owned GPIs. A '0' was used which wasn't so clear. Add
a comment and explicitly set it to ACPI. Also,
PAD_CFG_GPI_ACPI_SMI wasn't using the _PAD_CFG_ATTRS
macro which causes compliation errors if attempted
to be instantiated. No piece of code tried to use
it so the error was overlooked.
Lastly, allow for soc/gpio.h to be included during
ASL compilation. That allows for gpio_defs.h to be
included and those macros utilized without needing
to know the file name and where it lives; just use
the generic gpio.h.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I9dbadb0b494683ab38babfc1ac5e13093ee37730
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291935
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id4fa8b65ec1e1537dbf09824c2155119a768807e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of using a hard-coded value leverage the existing
definitions to perform GPE0 block length calculations. There
are 4 pairs of 32-bit status/enable registers.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291932
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11205
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The ec_smi_gpio and alt_gp_smi_en devicetree options are
goign to be removed. The plan for skylake is to set the
settings by the mainboard through either gpio pad
configuration or through helper functions.
Moreover, these values only allow *1* SMI GPIO configuration
in that the following has to be true:
alt_gp_smi_en = 1 << (ec_smi_gpio % 24)
If not, then another gpio(s) from the same group has the
SMI_EN bit set for it.
Lastly, remove all the subsequent dependencies as they are
no longer used: enable_alt_smi() and gpio_enable_group().
BUG=chrome-os-partner:43778
BRANCH=None
TEST=None
Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291931
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On skylake the GPE0 routing can be dynamically changed to
a particular GPIO group. Provide the ability for the mainboard
to set the route accordingly. If any of the values in the
devicetree are the same the current setting in the PMC register
is used. The GPIO communities need to have matching configuration
for the plumbing to work properly.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados w/ and w/o devicetree changes. Fields
are set accordingly.
Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291930
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
IedSize is not used in replace of IED_REGION_SIZE.
Drop it from chip.h.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: I38f6518701306c0ffc6d2b2e3fe01624a5eadf54
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290933
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: I9dd9e689d4d4f7b4770369dcd042d3325990ae32
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11201
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The skylake code is using IED_REGION_SIZE instead of
devicetree.cb. Drop the the option from the device trees.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=None
Original-Change-Id: Ib252266060fbc6ed0eeaac19a6b79c173c6c9a13
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290932
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: Ib08628e163ac27d4c49eddcbec6cab3252abd4aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11200
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The stage_cache_external_region() calculation is actually
dependennt on the properties of the chipset. The reason
is that certain regions within the SMRAM are used for
chipset-specific features. Therefore, provide an API
for abstracting the querying of subregions within
the SMRAM.
The 3 subregions introduced are:
SMM_SUBREGION_HANDLER - SMM handler area
SMM_SUBREGION_CACHE - SMM cache region
SMM_SUBREGION_CHIPSET - Chipset specific area.
The subregions can be queried using the newly
added smm_subregion() function.
Now stage_cache_external_region() uses smm_subregion()
to query the external stage cache in SMRAM, and this
patch also eliminates 2 separate implementations of
stage_cache_external_region() between romstage and
ramstage.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290833
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11197
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The smm_subregion() support allows the SMM relocation
to not use duplicated math by calling out the specific
regions it wants. IED base is now correct and not
pointing outside from SMRAM.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: Ief8940c2ab6320449500ced2121d0cd7ed73af4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290930
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: I00c3284cfacb2a73942640ccfa7912b7d65efb9d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11198
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The fsp_ramstage.c code was not taking advantage of the stage
cache which does all the accounting and calculation work for
the caller. Remove the open coded logic and use the provided
infrastructure. Using said infrastructure means there's no
need for the FSP_CACHE_SIZE Kconfig variable. Therefore, remove
it.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, and resumed on glados.
Original-Change-Id: I4363823c825b4a700205769f109ff9cf0d78b897
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290831
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ifd3cc4a538daac687949c5f4cab2c687368d6787
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11196
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The TSEG is defined to be from TSEG->BGSM in the
host bridge registers. Use those registers at
runtime to calculate the correct TSEG size.
Lastly, use a few helper macros to make constants
more readable.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290832
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11195
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Using struct prog and struct region_device allows for the
caller to be none-the-wiser about where FSP gets placed. It
also allows for the source location to be abstracted away
such that it doesn't require a large mapping up front to
do the relocation. Lastly, it allows for simplifying the
intel/commmon FSP support in that it can pass around a
struct prog.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, and resumed on glados.
Original-Change-Id: I034b04ab2b7e9e01f5ee14fcc190f04b90517d30
Original-Signed-off-by: Aaron Durbin <adurbin@chroumium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290830
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ibe1f206a9541902103551afaf212418fcc90e73c
Signed-off-by: Aaron Durbin <adurbin@chroumium.org>
Reviewed-on: http://review.coreboot.org/11193
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The stage_cache_add() function should not be manipulating
the struct prog argument in anyway. Therefore, mark it as
const.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, and resumed on glados.
Original-Change-Id: I4509e478d3c98247b9d776f6534b949d9ba6282c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290721
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ibadc00a9e1cbbf12119def92d77a79077625fb85
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11192
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch enables GPIO controller for skylake. It adds
community base addresses and offset for Community0, Community1,
and Community3. Community2 is not exposed in BIOS or enabled
in the kernel driver.
Also, clean up the carry over GWAK implementation from BDW.
BRANCH=None
BUG=chrome-os-partner:42393
TEST=cat /sys/kernel/debug/gpio should list of GPIOs
TEST=export a GPIO pin using /sys/class/gpio/export
Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291230
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Reviewed-on: http://review.coreboot.org/11191
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
acpi_is_wakeup_s3() was introduced in upstream coreboot
while the FSP support code was written. Move to using
that instead of using the romstage_handoff structure
directly.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, and resumed on glados.
Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290720
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11190
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Explicitly clear all write-1-to-clear fields in the
appropriate power state registers. That way stale
state isn't left around from boot to boot. The
MMIO PMC registers are always added such that the
resource can be accessed from reg_script. It doesn't
hurt to add the resource, and it's actually more
informative by attaching the actual resources
owned by the device.
BUG=chrome-os-partner:43625
BRANCH=None
TEST=Built and boot glados. Did global reset. Noticed bits
set. Did normal reset and saw those same bits no longer set.
Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290339
Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11186
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Leaving a sentinel 0xC0DEBABE and fixing it up is
is the old way of setting the correct base address
for GNVS. One just needs to reference NVSA which is
already filled in by the skylake ACPI code.
BUG=chrome-os-partner:43611
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados. /sys/firmware/log shows
up as well as ramoops using the correct address.
Original-Change-Id: I1d4979b1bb65faa76316a4ec4c551a7b9b9eed32
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290338
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I25efea73a383215f9365ce91230f79516b0201a6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11185
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Provide #defines for the bit fields in the SMI status register.
This allows for one to set the callback accordingly without
hard coding the index.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289802
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11184
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM
training is complete. However, as a 8-bit write was
being performed the bit was never being set.
BUG=chrome-os-partner:43516
BRANCH=None
TEST=Built and booted to kernel. Rebooted. Noted full memory
training was not being peformed.
Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290337
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11183
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Open coding bitfields is really annoying as no one knows
what they are unless you have a doc in front of you.
Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B
registers.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290336
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11182
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to run with the debug FSP the SMBus device needs
to be enabled. Additionally, the TCO block lives within
the SMBus device so if TCO is to be employed then the
SMBus device needs to be enabled as a prerequisite.
BUG=chrome-os-partner:42407
BRANCH=None
TEST=Buit and booted into kernel.
Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290364
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11181
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
FSP was setting up the TCO registers to be mapped at 0x400.
However, the SMBus initialization in romstage was mapping
its I/O BAR to 0x400 as well. The result seemed to cause the
TCO register to be hidden. However, the board was rebooting in
depthcharge when the SMBus device was enabled from a TCO timeout.
As the TCO timer was halted before the double resource assignment
it's not clear how the TCO was getting re-enabled. In either case,
the current behavior is wrong.
BUG=chrome-os-partner:42407
BRANCH=None
TEST=Built and booted glados w/ SMBus enabled.
Original-Change-Id: I43c0d67a76abac51ccfd5105245792981fbcd04c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290363
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I3839290768c27626c3fd2d67d5de94c291c1386e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of relying on FSP to do gpio configuration in one
place use the native support in coreboot. This also removes
the open coded configuration of the memory configuration
ids.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I4655221d821d91a2270d774305a02d6bd5c3959c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289800
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2e66242d050c3825f6bc65d3d2c7f51d2cdfbd73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11175
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It's important to be able to configure the gpio pads at
various stages instead of a single place using FSP. Without
this support there is a lot of duplicated open-coded pad
configuration taking place both within the SoC code and
mainboards.
Current limitation is that all GPIOs are in ACPI mode. i.e.
The HostSW ownership register sets the pad configuration to
only update GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. The
GPI_STS update is masked within the GPIO community registers.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Id8a00e99c7a4c3912de2feaff9cea12b402f2c68
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289789
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I4c86b47ac5ab004f2bfd7cb07dd23c458f7dbb7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11174
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In the wake of the recent Intel "Memoy Sinkhole" exploit a code review
of the AMD SMM code was undertaken. While native Family 10h support
does not appear to be affected by the same SMM flaw, it also does not
require SMM to function. Therefore, the SMM memory range initialization
should only be executed if SMM will be used on the target platform.
Change-Id: I6531908a7724933e4ba5a2bbefeb89356197e8fd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11211
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Many Kconfig options changed in coreboot.org since
skylake was first started. Fix Kconfig option name
changes, and also provide a common option, UART_DEBUG
that can be selected to select all the necessary
options.
Note: It's still a requirement to manually unset the
8250IO option because that's unconditionally set.
BUG=chrome-os-partner:43419
BUG=chrome-os-partner:43463
BRANCH=None
TEST=Built glados. Booted into kernel. Kernel reboots somewhere.
Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289951
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11172
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Enable the Deep Sx pins to allow wake from the EC via LAN_WAKE#.
Report the EC wake pin LAN_WAKE as GPE[112].
BUG=chrome-os-partner:43079
BRANCH=none
TEST=suspend/resume on glados with wake from keyboard
Original-Change-Id: I99664e1e406d15e7460046a6168cbd3a377aaca4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288921
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I19db144ed5db183f47af03340886a5e770af8bc8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11171
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add support for enabling various pins in Deep Sx by setting
a register in the mainboard devicetree.
BUG=chrome-os-partner:43079
BRANCH=none
TEST=build and boot on glados
Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11170
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There was no implementation for uart_fill_lb() in the 8250mem
driver. Rectify this so when 8250MEM and CONSOLE_SERIAL are
employed then the build doesn't fail.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=Built with glados using 8250MEM
Original-Change-Id: I35d6b15e47989c1854ddcee9c6d46711edffaf3e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289899
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: I972b069a4def666f509268816de91ed6c0f655d9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11169
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
CBFS_SIZE is living as a mainboard attribute. Because
of the Kconfig include ordering the SoC *cannot* set
the default. Remove from the soc Kconfig and add a
default Kconfig for SOC_INTEL_SKYLAKE.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=built glados
Original-Change-Id: I8808177b573ce8e2158c9e598dbfea9ff84b97c7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289833
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Icf52d7861eee016a35be899e5486deb0924a0f3c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11168
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In the review process for http://review.coreboot.org/#/c/11052/
the code was mangled and the result was unbuildable code. Fix this.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=Can actually build bootblock.
Original-Change-Id: I5bc63b8c435dbf025f1c334e9a1bc4a9da2b4902
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289788
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: Id0f67d8b74fa9146bf01990f599d538222f7e0e2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11167
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The asl_template previously unconditionally included
dsdt.aml. However, COMPILE_IN_DSDT=y results in the
dsdt.aml being linked directly into ramstage. Thus
the information is duplicated.
The inclusion of this file unconditionally throws
some errors as certain assets need to be included
in CBFS. However, as there isn't fine-grained
ordering control in how files are added fixed
resource requirements for other assets collide
result in failure to build.
To remedy both things, provide a 2nd argument to
asl_template which defaults to 'y' for CBFS
addition. In the COMPILE_IN_DSDT=y case pass
'n' so that dsdt.aml is no longer added.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=For glados:
Built with COMPILE_IN_DSDT=y. dsdt.aml not included.
Built with COMPILE_IN_DSDT=n. dsdt.aml was included.
Original-Change-Id: I4767e5be2915c1732251fe415017f30314c5efc9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289840
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id1828627ba0a034eb05b2fe23be76e19f3040444
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11166
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Remove dependency of common reset code on FSP
BRANCH=none
BUG=None
TEST=Build and run on Braswell and Skylake
Original-Change-Id: I00052f29326f691b6d56d2349f99815cafff5848
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286932
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7f59f0aad7dfae92df28cf20fff2d5a684795d22
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11165
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
The sysinfo object within the k8 ram init is used
to communicate progess/status from all the nodes in the
system. However, the code was assuming where the sysinfo
object lived in cache-as-ram. The layout of cache-as-ram
is dynamic so one needs to do the lookup of the correct
address at runtime. The way the amd code is compiled
by #include'ing .c files makes the solution a little
more complex in that some cache-as-ram support code
needed to be refactored.
Change-Id: I6500fa7b005dc082c4c0b3382ee2c3a138d9ac31
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10961
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I4afec92c57c6af4c99858afae53fa7746f47bc7a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11159
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Derived from what the vendor BIOS is doing.
Change-Id: Ie2cba7b86b6bb3f1dcc4a5e1c189aa45d0aab109
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: fwts 15.08
Reviewed-on: http://review.coreboot.org/11142
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adapts Ia5101d5a1 for the p470.
Change-Id: Ib09a0bc58fddd6240834cc890f00df91a74f4161
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11160
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
One may prefer to include vboot from another directory than 3rdparty for
convenience. This is especially the case in Libreboot, where 3rdparty is not
checked out at all.
Change-Id: I13167eb604a777a2ba87c3567f134ef3ff9610e4
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11116
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
$(obj) might be defined either as a relative or an absolute path. Thus, it has
to be filtered out before adding $(top) to it (in case of an absolute path) when
building vboot. It is then provided separately in CFLAGS (as an absolute path).
In addition, VB2_LIB inherits $(obj), so it might also already be an absolute
path, and prefixing $(top) to it doesn't apply. Thus, the absolute path to it
should be passed to the vboot make command.
Change-Id: I13e893ebdf22c4513ee40d9331a30ac7de8f9788
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11120
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The used functions require the ELOG_GSMI feature, not just ELOG.
Change-Id: If38cf0b710d9236012bfb1f0b119c10f9e533a25
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This enables adding the GPU specific entries to the SSDT.
Change-Id: I04d0eb7bf6f3e28d89c9318b777875e8a78b1ab5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11140
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I7f17cd1418f05ff3e8cd559eca6ec3ce7f9bfb79
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As acpi_write_hpet() uses CONFIG_HPET_ADDRESS in the HPET table we
need to use CONFIG_HPET_ADDRESS when assigning it to the device.
Change-Id: I656f917658f1c1717bb3653fa048a6d36fca2454
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10925
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Related-to: I3175c8b29e94a27a2db6b11f8fc9e1d91bde11f9
(ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systems)
Change-Id: I0b5f265278d90cbaeddc6fc4432933856050f784
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10912
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This should probably be moved out of lib and to arch/x86,
since it does not even apply on x86-64, and ARM has its
own copy of libgcc.
Change-Id: I4fca1323927f8d37128472ed60d059f7a459fc71
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11110
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Run `indent -linux src/drivers/pc80/i8254.c` and manually put the `;` in
the while loop back on a separate line.
Change-Id: I58c4c5df3846a91ef92aafb608962dc26a21f811
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10452
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Spike support: QEMU RISCV is broken, and the maintainers at Berkeley
are working on it, but at the moment spike is the only way to test
on riscv. Add support for spike console output for debugging.
Privileged ISA: Update to privileged ISA in RISCV (machine,
supervisor, hypervisor, user modes) broke exisitng RISCV asm, and
bootblock.S was updated to match the new spec. Clean old assembly
[pg: things build with gcc 4.9 now, but don't expect them to work.
Hardcoding register names into the assembler language may not be the smartest
idea of the RISCV folks.]
Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some FSF addresses found their way back into our tree.
Change-Id: I34b465fc78734d818eca1d6962a1e62bf9d6e7f3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11145
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The spec states (5.2.10): "The BIOS aligns the FACS on a 64-byte boundary
anywhere within the system's memory address space."
Change-Id: Ie9415e505525dbdd418028d4954018c829921a18
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: fwts 15.08
Reviewed-on: http://review.coreboot.org/11141
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
vboot2 requires it
Change-Id: I63bc3f176af72da8ea172a09aa536a10f1184b14
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11099
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The AMD AGESA binaryPI sources were incorrectly committed to
3rdparty/blobs. Move them from blobs to vendorcode and fix
Kconfig and Makefile.inc to match.
Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10982
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The *_SELECTED Kconfig variables are not needed with the
options contained within "if CPU_AMD_AGESA_BINARY_PI"
introduced in e4c17ce8. It also removes the need to
source and select the default prior to selecting the
AGESA source or AGESA PI option.
Change-Id: Iffa366f575f7f155bd6c7e7ece2a985f747c83be
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10981
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On x86-64 the current way of calculating the base address
of the boot device (SPI flash) gets an unwanted sign extension,
making it live somewhere at the end of 64bit address space.
Enforce rom_base to be at the upper end of the 4G address space.
Change-Id: Ia81e82094d3c51f6c10e02b4b0df2f3e1519d39e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11121
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This patch resolves the outstanding issues with
PCI device enumeration and getting the board to boot into
GNU/Linux with VGA rom.
Previously the board would not boot to GNU/Linux with video,
even if VGA rom was used.
Bugs in the devicetree were fixed according to superiotool output.
Tested on GA-B75M-D3H with VGA rom.
Booted to GNU/Linux (Fedora 22 4.0.4-301.fc22.x86_64)
Change-Id: Ide1f406652659e6f99ee5d993719c187650fffe4
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10895
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Make SB800 code compile with x64 compiler
These fixes probably apply 1:1 to the other SB components
in that directory.
Change-Id: I9ff9f27dff5074d2faf41ebc14bfe50871d9c7f7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10573
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
1. Use enable_imc_thermal_zone to enable fan control.
2. The ACPI method ITZE works on Ubuntu 14.04 and Windows 7
but does not work on Windows 8, so I didn't use it.
After this issue is fixed, I'll add ACPI_ENABLE_THERMAL_ZONE
in bettong/Kconfig.
3. Fan control works on Bettong. I used "APU Validation Toolkit"
to test on Windows 8. This tool can put load to APU. The fan's
behaviour is just like bettong/fchec.c defined. When the temperature
is 40 Celsius, the fan start to run.
Change-Id: I0fc22974a7a7cf3f6bdf5f1c66be95219a177e12
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10721
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
1. Add functions to support fan control.
2. When IMC firmware is added, the current firmwares' layout
cause build error. There is not enough space to add some firmwares,
so HUDSON_PSP_OFFSET is added to fix this problem.
Change-Id: Ie470a88cb9da256d9f72ea56bf268c15df195784
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10720
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Binary PI doesn't provide fan control lib.
HwmLateService.c and ImcLib.c are ported from Kabini PI.
I have tested on AMD Bettong. The two files work.
Change-Id: Ia4d24650d2a5544674e9d44c502e8fd9da0b55d3
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10719
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
For Skylake, Microcode is being loaded from FIT, Skylake supports
the PRMRR/SGX feature. If This is supported the FIT microcode
load will set the msr (0x08b) with the Patch id one less than the
id in the microcode binary. This results in Microcode getting
reloaded again in bootclock and ramstage (MP init).
Avoid the microcode reload by checking for PRMRR support.
BUG=chrome-os-partner:42046
BRANCH=None TEST=Built for glados and tested on RVP3
CQ-DEPEND=CL:287513
Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a
Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/287674
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11056
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Some Intel SoCs which support SGX feature, report the
microcode patch revision one less than the actual revision.
This results in the same microcode patch getting loaded again.
Add a SoC specific check to avoid reloading the same patch.
BUG=chrome-os-partner:42046
BRANCH=None
TEST=Built for glados and tested on RVP3
CQ-DEPEND=CL:286054
Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b
Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/287513
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11055
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
If Skylake microcode is being loaded from FIT, Skylake supports
the PRMRR/SGX feature. If this is supported the FIT microcode
load will set the msr (0x08b) with the patch ID one less than the
ID in the microcode binary. This results in microcode getting
reloaded again in the bootblock cpu init.
Avoid the microcode reload by checking for PRMRR support.
BUG=chrome-os-partner:42046
BRANCH=None
TEST=Built for glados and tested on RVP3
Change-Id: I06e59f5cad549098c7ba2dfa608cd94a0b3f0ae1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6242b9dea283149bd0c968af1ba186647d37162d
Original-Change-Id: Iea5a223aa625be3fc451e8ee5d3510f548b07f8b
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286054
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11052
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
We've seen an increasing need to reduce stack sizes more and more for
space reasons, and it's always guesswork because no one has a good idea
how little is too litte. We now have boards with 3K and 2K stacks, and
old pieces of common code often allocate large temporary buffers that
would lead to very dangerous and hard to detect bugs when someone
eventually tries to use them on one of those.
This patch tries improve this situation at least a bit by declaring 2K
as the minimum stack size all of coreboot code should work with. It
checks all function frames with -Wstack-usage=1536 to make sure we don't
allocate more than 1.5K in a single buffer. This is of course not a
perfect test, but it should catch the most common situation of declaring
a single, large buffer in some close-to-leaf function (with the
assumption that 0.5K is hopefully enough for all the "normal" functions
above that).
Change one example where we were a bit overzealous and put a 1K buffer
into BSS back to stack allocation, since it actually conforms to this
new assumption and frees up another kilobyte of that highly sought-after
verstage space. Not touching x86 with any of this since it's lack of
__PRE_RAM__ BSS often requires it to allocate way more on the stack than
would usually be considered sane.
BRANCH=veyron
BUG=None
TEST=Compiled Cosmos, Daisy, Falco, Blaze, Pit, Storm, Urara and Pinky,
made sure they still build as well as before and don't show any stack
usage warnings.
Change-Id: Idc53d33bd8487bbef49d3ecd751914b0308006ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e5931066575e256dfc2295c3dab7f0e1b65417f
Original-Change-Id: I30bd9c2c77e0e0623df89b9e5bb43ed29506be98
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236978
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Remove the items that are obviously broadwell left or become no-need
with fsp.
BUG=chrome-os-partner:43186
BRANCH=None
TEST=build and boot on sklrvp3.
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Change-Id: I5dfd62363eecc514e45a7b7ba0961ec7fe0499ee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 570920cdc9e9c08ee85dcb08998069f1cae2d3cd
Original-Change-Id: I63176584042516c4d28f1bb6403e7bbe5de61010
Original-Reviewed-on: https://chromium-review.googlesource.com/288833
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: http://review.coreboot.org/11072
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some of the field and register names in the power management
code were not reflecting current chipset documentation. While
in there fix 0-sized array in the power_state structure. Lastly,
log the entire STD GPE register for visibility in elog. It reports
as an extension of other GPIO wake events.
BUG=None
BRANCH=None
TEST=Built and booted.
Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e
Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288296
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11070
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to aid users of the PCR register space provide
pcr_port_regs().
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built glados.
Change-Id: Ibfcffbfd4304a59dd80a88dc18404d3a5dfa2f5d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5f796319ba1d00557e32bf18309fc3cc772ccae0
Original-Change-Id: I21243d18c1bbd19468f8f279b2daa4e40a8f0699
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288193
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11068
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to provide more clarity on what some of the gpio
functions are doing add a 'gpio_' prefix to the globally
visible functions.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built glados.
Change-Id: I4cf48558c1eb9986ed52b160b6564ceaa3cb94b4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f79ef113797884063621fe6cd5cc374c53390ebd
Original-Change-Id: I0d8003efff77b92802e0caf8125046203f315ae4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288192
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11067
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These types and definitions were carried over from a previous
platform. However, they are not used. Remove them.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built on glados
Change-Id: Ib3d20222df34a32865aac6b6cf13517c208e17c6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: be2d0d273a6c02483a944edac95ab48c433b29cd
Original-Change-Id: I56a0d549f5733eec8f405f2024ced8c153fa545c
Original-Signed-off-by: Aaron Durbin <adurbin@chormium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288191
Original-Trybot-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As in cold boot path, implement MBIST workaround in lp0
resume path.
BUG=chrome-os-partner:40741
BRANCH=None
TEST=Tested on Smaug; able to suspend/resume
Change-Id: I997009ecb0f52fb5a47c62b8daea33e472ec2664
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4b1f80ea4c1d3782eb9f2c90c2a8d7b2e97ba050
Original-Change-Id: Ib4944401e1df02bf0aab1e78db7e14ef56c7f829
Original-Reviewed-on: https://chromium-review.googlesource.com/287287
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
Reviewed-on: http://review.coreboot.org/11071
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Copied from Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769
BUG=chrome-os-partner:43022
BRANCH=None
TEST=Used physical recovery button to enter dev mode on rialto
Change-Id: I39fd13fee3b9f272f3dc08a447091e05a3d74741
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: eed0652f84cba963044908bb91aac7b8c1c81fd4
Original-Signed-off-by: Jonathan Dixon <joth@chromium.org>
Original-Change-Id: I388d8bb0faa93b54540be095e68450192592a093
Original-Reviewed-on: https://chromium-review.googlesource.com/287660
Original-Reviewed-by: Jason Simmons <jsimmons@chromium.org>
Reviewed-on: http://review.coreboot.org/11069
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Modify MR3_I/O Configuration, Change 34.3 ohms to 60 ohms. This
resolves an issue that was observed on some Mickey boards with
the Samsung 2GB LPDDR3 and is believed to be caused by inferior
routing on the small PCB. (Elpida 2GB LPDDR3 seems unaffected.)
BUG=chrome-os-partner:41905
TEST=Boot from mickey
BRANCH=None
Change-Id: Ic20d9eceb00658c214fd032a2f213dbe0d51a91b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1305010aee6818910ad1dec26d9d948505ca281e
Original-Change-Id: I5517e07fc5716ed4cd58e5502f13ccd61ffb5357
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286333
Reviewed-on: http://review.coreboot.org/11051
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The PLLU and UTMIPLL power-up sequences have been fixed in the
kernel. It's no longer necessary for the XUSB partitions to
be ungated at boot.
This reverts commit 3a4a8a97c1851b6f3dd211451d9678358fac3ad7.
BUG=chrome-os-partner:41244
TEST=Build and boot on Smaug; xHCI still works.
BRANCH=none
CQ-DEPEND=CL:282765
Change-Id: Id9a1c9960b6c7286b3185c60371d864874f50bb3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d52e50240bca62997af729722fbcdf5226438b7f
Original-Change-Id: Ieb9c8644a5fb108d77703933fde82d359f403fd1
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286810
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Mark Kuo <mkuo@nvidia.com>
Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-on: http://review.coreboot.org/11050
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Commit "BCRD2: Enable LPDDR3" with the Change-Id listed below contained
additions to braswell's chip.h which were lost during merging.
BRANCH=None
BUG=None
TEST=google/strago builds
Change-Id: I995b788b6a308cefa23228544127bb1e384bbcc7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 561edf23ab696772fd0a6af34cb435db9d96e912
Original-Change-Id: Ie08900bc62d517394412cc597274fb8f5b6b0f51
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Original-Change-Id: I1cb5a03b77baf2df125b648dd75c9f8166f5571e
Original-Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Original-Reviewed-on: https://chromium-review.googlesource.com/282155
Original-Reviewed-on: https://chromium-review.googlesource.com/288880
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/11065
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Enable PMIC SVID config for BCRD2 based
on board id. UPD parameter is used to
select the SVID config and PMIC I2C bus
number
BRANCH=None
BUG=None
TEST=Build and boot the system
Change-Id: I3c4c06bd25c241abdf46aa14af74eecf77cf77a6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 10bb8d4ad96d1187f6e135ca1535d70ae45ee887
Original-Change-Id: I9191db7bace4f4840e3c32381093c6c0806f7c32
Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/282156
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11060
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Aaron Durbin