Certain SATA devices claim to support SATA 6 Gbps, but in fact have
bugs. For these devices, add a config option to force the SATA link
speed to something other than default.
Change-Id: I2dc1793cd58771298a392345162d39d20eb0afbb
Signed-off-by: Shawn Nematbakhsh <shawnn@google.com>
Reviewed-on: http://review.coreboot.org/2765
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This enables power management and clock gating on XHCI.
Change-Id: I124ea6c5aca034b7ec4b5286d971c2adfce25c88
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2761
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
objcopy -B provides symbols of the form _binary_<name>_(start|end|size).
However, the _size variant is an absoult symbol. If one wants to
relocate the smi loading the _size symbol will be relocated which is
wrong since it is suppose to be a fixed size. There is no way to
distinguish symbols that shouldn't be relocated vs ones that can.
Instead use the _start and _end variants to determine the size.
Change-Id: I55192992cf36f62a9d8dd896e5fb3043a3eacbd3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2760
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The bd82x6x requires some additional setting on S3/S4 entry.
Change-Id: I24489ab94dd7cd5a4a64044f25153f5b01a45b77
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2759
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add the PCH function to SMM for follow-on SMM patches that
require these functions.
Change-Id: I7f3a512c5e98446e835b59934d63a99e8af15280
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2758
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
These enables are hidden behind IOBP for some reason.
Boot to linux with SDIO disabled and see that
the SDIO driver does not load and crash the system.
Change-Id: Icfbfa117e9e57a51d32db7f6366a9d0d790adcf0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2695
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit updates the Lynx Point resource reservations before
the coreboot allocator assigns resources. There is no need to mark
anything as subtractive decode because there are no devices/buses
linked to the LPC device.
The I/O range reservations consists of claiming the first 4KiB
of I/O space. The PMBASE, GPIOBASE, and LPC generic I/O decode
ranges are checked against the default claimed range. If those
ranges overlap or fall outside of the default range then those
resources are added.
The MMIO range reservations consist of claiming everything from
the I/O APIC to 4GiB. The RCBA and the LPC Generic Memory range
register are then conditionally added if they fall outside of
the default MMIO range.
Change-Id: I0f560a03814a2b15961fdbe61e4164cd54cff7a5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2682
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Add ME device ID for Lynxpoint LP
- Add GPU device IDs for ULT
- SATA init tweaks from checking against DXE reference code
- Remove the ICH7 from the SPI driver so it works on all lynxpoint
without having to add more LPC device ID checks
- Add function disable for audio dsp and xhci, remove PCI bridge
- Add interrupt route registers for new devices (needs romstage setup)
Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2680
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Add device IDs for lynxpoint mobile and LP variants.
- Update the clock gating setup based on BWG
- Update the SATA programming based on BWG
- Add a DEVSLP0 mux config register
Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2649
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The low power variant of the chipset introduces a completely
new interface to the GPIOs.
This is a 1KB region and so needs to be moved as well so it does
not conflict with other IO regions.
Also expose the gpio_get functions to ramstage and move the
prototypes to pch.h so they can be used for both GPIO interfaces.
Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2648
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
There are enough subtle differences that it is useful to have
a Kconfig entry to differentiate the ULT/LP chipet from the
desktop/mobile versions.
Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2645
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit contains a bevy of updates:
- PCI device id is updated to match Lynx Point EDS in the ME driver.
- Allocate the memory to store the consumption of the MBP.
- me_bios_payload structure is now a structure of pointers that point
into the allocated memory.
- The ICC profile structure was updated to correctly reflect the
documentation.
Verfied that output of MBP reading can handle unknown items.
Change-Id: I43cc45e6b797444c105e7c842eb5684e9c104687
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2641
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
According to the 0.8.0 ME BWG this is a new state. It's not very clear
what exactly it entails, but the Basking Ridge CRB was tripping it when
MRC_DEBUG was enabled (presumably because of a DID timeout).
Instead of 0x17 one can now see the proper message for this state.
Change-Id: I5bda1de7d3d957d38a4760a02dcd170ec48782e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2640
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is no longer tied to a GPIO but has a proper chipset pin.
Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2643
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2618
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The register that controls global reset is named the Power
Mangement Initialization Regiser (PMIR). Update the defines
to reflect the documentation.
Additionally, there is no core well reset control according to the
EDS. There is, however, a CF9 lock field to lock this register down.
Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2619
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ME9 requirements have added some registers and changed some
of the MBP state machine. Implement the changes found so far in
the ME9 BWG. There were a couple of reigster renames, but the
majority of th churn in the me.h header file is just introducing
the data structures in the same order as the ME9 BWG.
Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18
Signed-Off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2620
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order for coreboot to assign resources properly the pci
drivers need to have th proper device ids. Add the host controller
and the LPC device ids for Lynx Point.
Resource assignment works correctly now w/o odd behavior because
of conflicts.
Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2638
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
This follows the new method outlined in the LPT BWG.
It is also very pedantic about its operation so it
is easier to read and compare against the docs and
the reference code implementation.
Change-Id: I235d634cded0c75ec0e9f53488f5b366107a18fa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2694
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore,
the southbridge support is included as well. The basis for this code is
the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires
more attention, but this is a good starting point.
This code partially gets up through the romstage just before training
memory on a Haswell reference board.
Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2616
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The current default is IDE mode which is slower compared to AHCI
mode. Therefore use AHCI mode by default.
A similar change was made for AMD Persimmon in commit
»Enable SATA AHCI for faster boot with SeaBIOS.« (96be74c7) [1]
but was indirectly reverted by »sb800: Add sata ahci/raid mode
kconfig option« (d4a0e7d0) [2].
[1] http://review.coreboot.org/220
[2] http://review.coreboot.org/225
Change-Id: I4fa31b0a3280891e7a3f37675ae8415205818947
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.
Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
The power up default for the 14M_25M_48M_OSC switchable clock output ball of
the SB800 chipset is 14 MHz. sb800/bootblock.c changes this to 48 MHz,
which is the correct value for almost all SIOs. However, not for
'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not
configurable for other clock speeds. A wrong SIO clock supply results in
funny RS232 output (wrong bit speed) and non-working PS/2.
We could switch back to 14 MHz in the mainboard's romstage.c, but then the
clock frequency would change twice. The resulting short 48 MHz burst causes
a handful of rubbish characters on RS232 on every boot until the SIO clock
has stabilized again.
This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz.
This does not affect any boards currently in the repository (yet).
Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
According to both Haswell and the SandyBridge/Ivybridge
BWGs the save state area actually starts at 0x7c00 offset
from 0x8000. Update the em64t101_smm_state_save_area_t
structure and introduce a define for the offset.
Note: I have no idea what eptp is. It's just listed in the
haswell BWG. The offsets should not be changed.
Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2515
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Adding RTC init code to the Southbridge initialization
code in 'lpc_init'. This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup. By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts
This is the same edit made to the CIMX SB800 titled
'AMD/Persimmon: Add RTC init to CIMX SB800' with commit
ID: c4d3d which can be viewed here:
http://review.coreboot.org/#/c/2488/
Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2510
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Adding RTC init code to the Southbridge initialization
code in 'late.c'. This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup. By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts
This was tested on a Persimmon but will apply to
other mainboards as well.
Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2488
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently the size of the volatile storage for S3 reserved in the
image is hardcoded to 32768 bytes. Make that configurable by
introducing the Kconfig 'S3_DATA_SIZE'.
As the storage space is needed for storing non-volatile, volatile and
MTRR data, add a check if the size is big enough.
Change-Id: I9152797cf0045c8da48109a9d760e417717686db
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2383
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For whatever reason tabs got inserted in the license header text.
Remove one occurrence of that with the following command [1].
$ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,'
[1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt
Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2460
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory,
builds failed when all files were configured to point to other sources.
This change modifies the blob mechanism so that cbfs-files can be tagged as
"required" with some specification what is missing.
If the configured files can't be found (wrong path, missing file), the build
system returns a list of descriptions, then aborts.
Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2418
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marcj303@gmail.com>
S3_DATA_POS defines address where the whole S3 data is stored.
Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2438
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.
Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.
Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Since there are and will be other files in nb/sb folders, we change
the general spi.h to a file name which is not easy to be duplicated.
Change-Id: I6548a81206caa608369be044747bde31e2b08d1a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2309
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The "system is legacy free" question accidentally escaped
from the hudson Kconfig where it was intended to stay and
went coreboot-wide. This puts it back inside the boundries
of the hudson southbridge where it belongs.
I also commented the endif statements to make it easier to
tell where things belong.
Change-Id: I49f7a5eadb96d40c6101a93bc390e644617a5654
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2179
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Go through southbridge/amd/agesa/hudson, thatcher and parmer
mainboard directories and change all references to sb800 to
reference hudson instead.
This is just cleanup and should make no functional difference.
Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2177
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Add Kconfig option for Legacy free and hook it into the parmer
AGESA initialization as well as the FADT code. This should really
be done inside the southbridge wrapper and not in the mainboard,
but for now the code to attach it to is inside the mainboard.
Update Kconfig for parmer and thatcher to default to legacy free.
Change-Id: Ib899bd02ddc5506caae4aca2c589cc2526638cb8
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2157
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Update the southbridge/amd/agesa/hudson FADT generation for ACPI
3.0 compliance similar to what was done for cimx/SB800/fadt.c in
commit 9aa4389.
commit 9aa43892e6
Author: Martin Roth <martin@se-eng.com>
Date: Fri May 25 12:23:32 2012 -0600
Update SB800 CIMX FADT
According to the datasheet, PMA_CNT_BLK is no longer available
and PM2_CNT_BLK should not be used. Setup for these has been
removed from the table and .h file.
Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2140
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The cimx/sb800 IMC Firmware location Kconfig option has
a typo which would could set it to the wrong location.
Change-Id: I38016bebd1bfe6ad6d3f1c02cb1960712fbf4ab2
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2120
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
That code will be used to disable the internal GFX card and enable the
external PCIe card.
The following lines from function `rs780_internal_gfx_enable()` are
taken and reversed.
/* Disable external GFX and enable internal GFX. */
l_dword = pci_read_config32(nb_dev, 0x8c);
l_dword &= ~(1<<0);
l_dword |= 1<<1;
pci_write_config32(nb_dev, 0x8c, l_dword);
It has been tested on the M4A785T-M with the following card inside the
PCIe 16x slot:
02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2)
Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2065
Tested-by: build bot (Jenkins)
If a 3rd party blob option is selected, make sure that it makes the
user select CONFIG_USE_BLOBS as otherwise the build will fail.
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I04429f23137946525c8577dd9c979bd4a0d17cdc
Reviewed-on: http://review.coreboot.org/2080
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Since SB800, USB2.0 debug port is dev 0x12, func 2.
Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1880
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
We ship it in the 3rdparty repository.
Change-Id: Ida52bc7e813f8468910c4ea7838ebb863c52b88a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2060
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Add prefix coreboot_ to let make clean find it and delete it.
Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2029
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800
platforms.
- Allows user to add the IMC rom to the build and to configure the
location of the "signature" between the allowed positions.
- Allows for no fan control, manual setup of SB800 Fan registers, or
setup of the IMC fan configuration registers.
- Register configuration is done through devicetree.cb. No files need
to be added for new platform configuration.
- Initial setup is for Persimmon, but may be extended to any cimx/sb800
platform.
Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The file generated when the IMC or XHCI binaries are included in the rom
was named $(obj)/hudson_romsig.bin. The problem with this is that it
doesn't get deleted when the user does a make clean.
changing the name to coreboot_hudson_romsig.bin makes this happen.
Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1978
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
There was already a special case for the SPI base address in
lpc_set_resources for southbridge/amd/cimx/sb800 and
southbridge/amd/agesa/hudson, but it needed to be modified
to keep from killing the IMC rom during initialization. As
soon as the BAR is disabled by setting the new base address,
the IMC dies. The fix is to make sure it's still enabled
when setting the new base address instead of setting the new
address then re-enabling it.
Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER
to more accurately describe what we're using.
Change-Id: I216d75b722c4332c239d487111a9880eabf59e91
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1975
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The SB800 and Hudson now support adding the IMC ROM which runs from the same
chip as coreboot. When the IMC is running, write or erase commands sent to
the spi bus will fail, and the IMC will die. To fix this, we send a request
to the IMC to stop fetching from the SPI rom while we write to it. This
process (in one form or another) is required for writes to the SPI bus while
the IMC is running.
Because the IMC can take up to 500ms to respond every time we claim the
bus, this patch tries to keep the number of times we need to do that to a
minimum. We only need to claim the bus on writes, and using a counter for
the semaphore allows us to call in once to claim the bus at the beginning
of a number of transactions and it will stay claimed until we release it
at the end of the transactions.
Claim() - takes up to 500ms hit
claim() - no delay
erase()
release()
claim() - no delay
write()
release()
Release()
Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1976
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Remove the old, unflexible code for storing S3 data in SPI flash.
Refer to flashrom. Tested on Parmer.
Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.
Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
This broke because those components were not yet
committed when the patch to drop the driver class
was made.
Change-Id: I29948223503a6c4b196eafa169c064cd26da1be1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1873
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.
These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.
With ramstage.a gone, we can drop this special class, too.
Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add support for ICH9 southbridge
Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
e.g.
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
This will make it easier to switch over to use the config_enabled()
macro later on.
Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
hard_reset was indeed consolidated and moved into the southbridge
code a while ago, but the config variable was still kept alife, with
some duplicate code.
Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1837
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The search for save state was comparing the entire RAX
value when it needs to just operate on the bottom byte
so it can find the GSMI command in bits 7:0 but not the
extended command code in bits 15:8.
Change-Id: I526c60e6b3732fa3680a17a4bed2a2ef23ccf94f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1774
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Instead of hijacking some random memory addresses to
relay the GNVS pointer to SMM we can use EBX register
during the write to APM_CNT register when the SMI is
triggered.
Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1766
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Using global variables with the TSEG is a bad idea because
they are not relocated properly right now. Instead make
the variables static and add accessor functions for the
rest of SMM to use.
At the same time drop the tcg/smi1 pointers as they are
not setup or ever used. (the debug output is added back
in a subsequent commit)
Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1764
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is currently used by the ELOG GSMI interface but is a
good way to pass data to SMM so move the current searching code
to a separate function and make it a bit more versatile with the
checks it does to find a match so it can be used in other
situations.
Change-Id: I5b6f92169f77c7707448ec38684cdd53c02fe0a5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1763
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The SMM GNVS pointer is normally updated only when the
ACPI tables are created, which does not happen in the
resume path.
In order to restore this pointer it needs to be available
at resume time. The method used to locate it at creation
time cannot be used again as that magic signature is
overwritten with the address itself. So a new CBMEM ID
is added to store the 32bit address so it can be found
again easily.
A new function is defined to save this pointer in CBMEM
which needs to be called when the ACPI tables are created
in each mainboard when write_acpi_tables() is called.
The cpu_index variable had to be renamed due to a conflict
when cpu/cpu.h is added for the smm_setup_structures()
prototype.
Change-Id: Ic764ff54525e12b617c1dd8d6a3e5c4f547c3e6b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1765
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
For reasons of security and testing we want to be able to
enable/disable ME section locking through a config option.
Change-Id: I341c577cdae86be62c0e3d32bbd6b3333c004a5f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1798
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Right now coreboot's build process produces images that are
not booting on actual hardware because they are smaller than
the actual flash device and also don't have an IFD nor an ME
firmware in them. In order to produce bootable images, you
needed a wrapper script / extra step until now. With this
change, the resulting coreboot.rom is actually bootable.
Change-Id: I82714069fb004d4badc41698747a704bd9fed4da
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1771
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is a basic romstage driver that can be used for the
MRC cache code on systems where we do not have the MRC cache
stored in a flash region that is memory mapped.
It uses the hardware sequencing interface to avoid having
to know anything about the flash chip itself.
BUG=chrome-os-partner:15031
BRANCH=stout
TEST=manual: this was tested with debug code added to romstage
that attempted to read the MRC cache at offset 0x3e0000.
SPI READ offset=003e0000 size=64 buffer=ff7fba00
SPI ADDR 0x003e0000
SPI HSFC 0x3f00
SPI READ: 0=4443524d
SPI READ: 1=00000bb0
SPI READ: 2=00008e24
SPI READ: 3=00000000
SPI READ: 4=001c8bbb
SPI READ: 5=0c206466
SPI READ: 6=0a043220
SPI READ: 7=000058b4
SPI READ: 8=00000000
SPI READ: 9=00000000
SPI READ: 10=00100000
SPI READ: 11=00100005
SPI READ: 12=20202025
SPI READ: 13=000e0001
SPI READ: 14=00000000
SPI READ: 15=00000000
Change-Id: I5f78f53111f912ff5dda52bbf90fdc1824b82681
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1777
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Fix handling of 5-byte Fast Read command in the ICH SPI
driver. This fix is ported from the U-boot driver.
- Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by
defining a name for the bool in Kconfig and removing the
forced select in southbridge config
- Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers
to use #if instead of #ifdef
- Relocate flash functions in SMM so they are usable.
This really only needs to happen for read function pointer
since it uses a global function rather than a static one from
the chip, but it is good to ensure the rest are set up
correctly as well.
Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1775
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The Intel PCH can override the ASPM settings via the MPC2 register.
Add a chip override for F0-F7. Mainboards may implement this as
needed.
This also fixes the final PM setup being done too early. It was
being done prior to the PCIe ASPM setup, which happens in the
bridge scan.
Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1796
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Right now the SPI bus is getting set to 20mhz for transactions
initiated with the software sequence interface.
In order to be able to do reasonable fastread/write/erase we
can bump this up to a higher value at boot before it gets
locked at 20mhz.
To do this read out the speed set in the SPI descriptor for
hardware sequencing and apply it to software sequencing.
Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The chips we are using do not use BE52 (block erase 0x52)
so we can use that opcode menu location to enable fast read.
Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
And move the pre-hardwaremain post code to 0x79
so it comes before hardwaremain at 0x80.
Emit these codes from ACPI OS resume vector as well
as the finalize step in bd82x6x southbridge.
Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The sleep type is 5 for S3 and 7 for S5.
Change-Id: I7ffdb3d27b6994ac4a12a343caf4d7abb82fe6ca
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1760
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These bits are used by the IGD OpRegion code
Change-Id: I89a11fc5021d51e0c1675ba56f6a3bc3b79bb8aa
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1751
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
In order to support Intel's IGD Opregion standard, we need
an additional set of flags shared between firmware, ACPI, SMM, and the
graphics driver.
Change-Id: I1a9b8dff5e5ee8d501b6672bc3bcca39ea65572e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1750
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
If the driver is initialized before the lockdown then it will
fail to work after the lockdown bit is set.
Change-Id: Idc05d33d8d726bf29cb3c9b1b4604522bd64170a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1745
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In case tseg_relocate() is called again on a pointer we should not
relocate it again.
Change-Id: Ida1f9c20dc94b448c773b14d8864afe585369119
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1740
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We are seeing ME disabled and ME error events on some devices
and this extended info can help with debug.
Also fix a potential issue where if the log does manage to get
completely full it will never try to shrink it because the only
call to shrink the log happens after a successful event write.
Add a check at elog init time to shrink the log size.
Change-Id: Ib81dc231f6a004b341900374e6c07962cc292031
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The handling of write enable was not entirely correct,
the opcode needs to be skipped when the controller is
locked down.
Addresses were not getting set properly for erase commands
which seemed to mostly work when the previous command had
set an address.
Tested by adding events to the event log at runtime on a
freslhy flashed device (with locked down SPI controller)
until the log log shrink happens to ensure it does not hang:
hexdump -C elog.event.kernel_clean
00000000 01 00 00 00 ad de 00 00 00 00
for x in $(seq 1 232); do
cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog
done
mosys eventlog list | tail -6
154 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
155 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
156 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
157 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
158 | 2012-09-01 13:54:43 | Log area cleared | 1030
159 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
Change-Id: I3a50dae54422a9ff37daefce3632f8bcbe4eb89f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1717
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Now that WREN prefix is handled properly ELOG is able to write
when the SPI controller is locked down.
To test, ensure that runtime SPI write via ELOG is successful by
checking the event log for a kernel shutdown reason code:
5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown
6 | 2012-08-27 11:09:50 | System boot | 26
7 | 2012-08-27 11:09:50 | System Reset
Change-Id: If6d0dced7cb0f5ca7038b3d758f31b856826d30b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1712
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
The code that attempts to use the opmenu needs to have a special
case for write enable now that it is handled as an atomic prefix
and not as a standalone opcode.
To test, ensure that runtime SPI write via ELOG is successful by
checking the event log for a kernel shutdown reason code:
5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown
6 | 2012-08-27 11:09:50 | System boot | 26
7 | 2012-08-27 11:09:50 | System Reset
Change-Id: I527638ef3e2a5ab100192c5be6e6b3b40916295a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1710
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
This appears to fix an infrequent resume hang on Ivybridge.
Tested on 2 devices with 15k suspend/resume cycles each
Change-Id: I53618bc7966824413f1720a2be3cbd2550e29473
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1704
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Every line of text after a 'help' label in a Kconfig
file must have the same whitespace preceding it, otherwise
it's no longer considered help text.
Change-Id: I97093bee72b295b315d78d4c26d7186bf1017fda
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1687
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Unfortunately the reference tool chain was updated
without ever even testing it on an abuild run. This
broke a number of ports.
This change gets coreboot at least compiling again
for all supported systems.
Change-Id: I92c7cbc834de6d792fdab86b75df339e2874c52e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1670
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
HPET's min ticks (minimum time between events to avoid
losing interrupts) is chipset specific, so move it to
Kconfig.
Via also has a special base address, so move it as well.
Apart from these (and the base address was already #defined),
the table is very uniform.
Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Also deletes files not included in build:
src/southbridge/amd/cimx/sb700/chip_name.c
src/southbridge/amd/cimx/sb800/chip_name.c
src/southbridge/amd/cimx/sb900/chip_name.c
Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Some 32 bit machines print integer higher than 0x80000000
as negative number.
Change-Id: Ieb512ed2a7499ce7e91e45e4075d4f119780b57d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1547
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Try
sh> printf %d 0x005500AA | LC_ALL=C awk '{printf("%c%c%c%c", \
$1 % 256, $1/256 % 256, $1/65536 % 256, $1/16777216);}' | \
od -Ax -t x
On Linux with gawk, we get
000000 005500aa
000004
On FreeBSD with nongnu-awk, we get
000000 000055aa
000002
In awk, all the numbers are floating point number. So division doesn't
round the result from 0.75 (3/4) to 0.
And, There is a fact that, for the FreeBSD awk,
sh> awk 'BEGIN {printf("%c", 0.75)}';
produces nothing, instead of 0.
Here we need to convert the floating point number to
integer by int(X), which is an awk built-in function, instead of GNU
extension.
Change-Id: I3470d5f13e7ea59a978d5575a54c0d56368dc78d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1529
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
TRACE has redefined warnings in src/southbridge/amd/cimx/sb700/Platform.h,
so we do some changes to remove such warnings.
Change-Id: I24979e08b83434f91a8fa37cd9f16303fa0b298d
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1499
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Command expr in some systems only take 32bit as integer, which
value is at 0x7FFFFFFF ~ -0x80000000. Use awk as alternate way to
calculate.
And some system doesnt take hex value in Makefile, even in awk instruction.
Change-Id: Ie35d6a5b96eea4192bd9cab857af4d4dcb37b9ed
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1527
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Forgot to change the code back after debugging.
Change-Id: Iaf58d65c14d53ca77958080faf6ab85d60992226
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1491
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Prior to this change the setting would be zeroes and
would cause a BSOD in 64 bit versions of Windows.
Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1475
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Maybe sooner or later python is not a default tools to build coreboot.
Most of the work is done by awk now. GNU extension of gawk is not used, isn't?
echo, expr, printf, cat, awk, test, mv are the external tools.
If XHCI, IMC or GEC firmware is not available and not defined, this script can skip
integrating them.
Change-Id: I9944b22b0b755672a46d472c355d138abafd6393
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1417
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
The includes removed here were previously required for
struct lb_memory and lb_add_memory_range().
Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1391
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
The names were set at various times during development, but
the way the code works, you might end up with the wrong name
being displayed in the logs. Instead of doing magic, just
display both names for each component
Change-Id: I1f8ce44d156442f5f7d717e1a2b47ed1218d4527
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1413
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Move beep commands to board-specific area as they need to be different for
different codecs.
Change-Id: I2a1ac938c49827cc816a95df10793a7e234942bf
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: http://review.coreboot.org/1410
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Use IORESOURCE_RESERVE to exclude the region from system RAM table.
Change-Id: I61b51022165e1304a41554f67af75b3089d892af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1393
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Apply the change
http://review.coreboot.org/1390
to all the AMD southbridge.
Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1406
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
In accordance to PCH EDS 14.1.35.1
Change-Id: I2e6cec6d4f49f404e33a171a8fbd6e4880327896
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1411
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Parmer and thather hang at windows 7 booting process. Setting the
valid date in CMOS can fix that.
Change-Id: I5e427cfb42430ebebdb4c1e48bd25860c0fec45f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1390
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The code in rs690 or rs780 is always used with K8 or AMDFAM10
northbridge. Without GFXUMA, both of these set the same static value
indirectly using the variable uma_memory_base.
Make the register setting with immediate value, to remove the obscure
use of variable uma_memory_base.
Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1246
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Compilation fails with set_debug_port undeclared in ramstage and
smm code. Fix that by adding usb_debug.c to the appropriate stages.
Change-Id: I2a037d3c5fab76ae6ea65c3a7f4d4e7561bb6d34
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1376
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Our driver infrastructure became more flexible recently.
Make use of it.
These are the low hanging fruits (files with 5 device
variants or more), but there are still lots of files
with less potential for deduplication.
Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
We used a hard coded value for some reason. Don't do that, but use CMOS
instead.
Modelled after http://review.coreboot.org/#/c/443 to get bd82x6x in
sync.
Change-Id: I36d715310157b9f9074f2a1c80710f85833020b4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1324
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This will log if the ME is disabled or has an error.
1) disable ME via EC console: gpioset PCH_HDA_SDO 1
2) boot the device
3) read eventlog with "mosys eventlog list"
71 | 2012-07-13 10:10:55 | Management Engine | Disabled
Change-Id: I9f6ee452d2aea76e6a5ea2cd50a50ff36245692a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1345
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This will allow various teams to select which thermal sensor
will control the thermal zones.
Also add a method to notify the thermalzones of a change
so these threshold/sensor methods take effect.
Needs a modified BIOS that uses the NVS TMPS value in
the thermalzone to read a different sensor.
Then, use a kernel driver that contains the following:
/* Adjust temperature sensor id to 2 */
union acpi_object param;
struct acpi_object_list input;
param.type = ACPI_TYPE_INTEGER
param.integer.value = 2
input.count = 1;
input.pointer = ¶m;
acpi_evaluate_object(NULL, "\\TMPU", &input, NULL);
And ensure that the temperature sensor that is being
monitored switches to ID 2.
Change-Id: I6319741358ba31eb8a3dc635d64f3f0acf683386
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1340
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ME device was being sent EOP and the PCI device hidden during
coreboot so it was not available in the SMI finalize step.
This also flips the PCI vendor/device dword around for the match.
Boot on Panther Point with serial and SMI debugging enabled and see
that ME EOP message is sent and the device is hidden at end of
U-boot and before the kernel loads.
Finalizing Coreboot
SMI# #0
ME: mkhi_end_of_post
ME: END OF POST message successful (0)
PM1_STS: TMROF
PM1_EN: 120
Starting kernel ...
Change-Id: I230038c62c50db2a1c94078c0a2a67bdc232440e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1338
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The LPC bus normally allocates the range for legacy devices,
0-0x1000. Some devices on LPC are above that range and need to
be accounted for. Check the decode range settings for addresses
> 0x1000 and reserve them.
Change-Id: Idba800d7cee3185296f29dd237ba306f3de8de55
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1337
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Events are logged for SMIs that trigger ACPI sleeps state
entry and when the power button press triggers an SMI such
as at the developer/recovery screens.
Generate ACPI sleep state events and power button
events and verify they show up in the log:
153 | 2012-06-23 17:12:59 | ACPI Enter | S5
184 | 2012-06-23 17:15:50 | ACPI Enter | S3
216 | 2012-06-23 17:28:58 | Power Button
Change-Id: Iba134d619780e459bce189d36d57844997ffb009
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1320
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Unfortunately the drive strength values are very much board
specific and different between mobile and desktop so we don't
try to do any fancy detection here but let it be specified
directly in the devicetree.
Change-Id: I66674bff0de04ecd088fb09afad1cf801a374df2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1347
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order to support the GSMI interface the SMI handler needs
to find and use the state save area from the same CPU that
initiated the SMI. In this case it is a synchronous SMI
resulting form an IO write to port 0xB2.
To find the right CPU state save area iterate over the region
until the "IO Misc Info" field reports the expected value and
then proceed to use that state save area.
This is needed because the coreboot SMI handler only executes on
one core, and that core is non-deterministic. It is likely that
the core executing the C SMM handler is not the same one that
actually did the IO write to 0xB2 and generated the SMI.
The GSMI parameter buffer is passed as a pointer to EBX in the
tate save area, and the GSMI command is extracted from EAX before
it is used as the return value.
This interface is tested by enabling CONFIG_GOOGLE_GSMI in the
kernel and generating events and verifying that they end up
in the event log.
159 | 2012-06-23 16:22:45 | Kernl Event | Clean Shutdown
184 | 2012-06-23 17:14:05 | Kernl Event | Oops
185 | 2012-06-23 17:14:05 | Kernl Event | Panic
Change-Id: Ic121ea69e9f50c88467c435e095c3e3629989806
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1317
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is a temporary workaround so the SPI bus can be accessed
at runtime in SMM code until the SPI opcode menu is used
properly.
Change-Id: I93d188c55b66d8dce49fa91a1de53ee195944b30
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1318
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is called from the SMI handler install because those
setup functions clear many of these registers.
Ensure that these events show up in the log as appropriate.
Example log output:
159 | 2012-06-23 14:31:54 | SUS Power Fail
160 | 2012-06-23 14:31:54 | System Reset
161 | 2012-06-23 14:31:54 | ACPI Wake | S5
Change-Id: I48c423c10ee7e6c2829bcc95f6cfabb4979c25a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1319
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This function is exported so it can be used in other
places that need similar relocation due to TSEG.
Change-Id: I68b78ca32d58d1a414965404e38d71977c3da347
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1310
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This was introduced when porting the SPI driver over from u-boot but it
is not needed. Hence drop the extra typedef and use device_t instead.
Change-Id: I3ab797a8e482d1c9aa1d004e488e99aeaffcdd8b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1331
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
CPUs with configurable TDP will run the TSC at the max non-turbo
ratio for the maximum TDP value, which can cause issues if another
TDP is desired. To deal with this we set the flex ratio to the
nominal TDP ratio early in the boot and then configure the Soft
Reset Data registers so the PCH can tell the CPU what frequency
to run at after a reset.
This is done very early in the bootblock because it is necessary
to reset the system after setting a flex ratio.
The end result is that the TSC will now increment at the max
non-turbo frequency for the nominal TDP.
On some system with 1.8GHz CPU ensure that the kernel
detects the CPU speed as ~1800mhz rather than ~2300mhz:
> dmesg | grep "MHz processor"
[ 0.004000] Detected 1795.801 MHz processor.
Change-Id: I8436dced9199003b6423186a2b041e3f7b84ab8c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1329
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There are enough differences that it is worth defining the
proper map for the sandybridge/ivybridge CPUs. The state
save map was not being addressed properly for TSEG and
needs to use the right offset instead of pointing in ASEG.
To do this properly add a required southbridge export to
return the TSEG base and use that where appropriate.
Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1309
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- add Kconfig option for CONFIG_SPI_FLASH_SMM
- compile subsystem and chip drivers for smm if enabled
- change mdelay(1) to udelay(500) since mdelay is not defined
in SMM and a 1ms delay is worth avoiding
- make flash chip structure non-const so the probe function
pointers can be relocated for use in TSEG
- Make SMM PCI access possible in southbridge SPI code
Change-Id: Icfcbbe8e4e56658769d46af0b5bf6c79a6432641
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1313
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ME needs to be talked to through the PCIe memory mapped config
space.
Change-Id: Ic2c5a572a126722a08a82d95df13d11507586c6b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1284
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In the short term there might be devices with Sandy Bridge CPUs
on mainboards with Panther Point PCHes. While this configuration
option is perfectly valid, coreboot currently ties Sandy Bridge to
Cougar Point and Ivy Bridge to Panther Point. One occurence is in
the ME handling code.
To make coreboot most flexible, compile both ME handlers into
coreboot and decide at runtime which one to use.
Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1280
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- On Cougar Point there may have been stack corruption during the
ME hash verification
- On Panther Point the ME firmware hash was not passed on to the
OS
Change-Id: I73fc10db63ecff939833fb856a6da1e394155043
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The PCIe device enable function prints when it disables a device.
The PCIe ports(bridges) use a different routine that didn't print
the message. Add it to be consistent and to provide better debug
output.
Change-Id: I8462c48e7f4930db68703f0bfb710c01c9643a98
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1326
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Changing CMOS value for power-on-after-power-fail was only honored
after reboot, which is counter intuitive (set from "enable" to
"disable",
power-off, replug device -> device turns on; and similar cases).
Modelled after http://review.coreboot.org/#/c/444
Change-Id: I2b8461dff1ae085c1ea4b4926084268b4da90321
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1323
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The function was too eager shifting stuff around, this change corrects
the problem.
Change-Id: I4c13dbe86cb627835dae05bb74af9867c28e143d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1291
Tested-by: build bot (Jenkins)
There are enough subtle differences in the magic values that
it is easier to make a separate function.
This fixes a reset hang with pantherpoint chipset.
Change-Id: I02b03cb37e5fd5ee2fd62067644f0a62dc2cd26a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1322
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
This makes it available early in romstage without having to
worry when the different romstagse enable it.
Check for extended CMOS to be enabled in early romstage.
This is used by a later commit which uses the extended
CMOS region for stoage.
Change-Id: I9e026d48499c63d6503c2b020d4cc3047126fa93
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1306
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
- Convert all PCI ID lists to new scheme
- Unify code (variable names)
- add missing PCI IDs for Panther Point PCIe root ports.
Change-Id: I6357f6ebce7ddffe45a3ec642b0c594147f6134c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1301
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This lets the SPI driver and the LPC driver know about HM70 and NM70.
Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1300
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
With this patch it is possible to use the smbus in ramstage. The
biggest part of the patch is a simple code split into a general
part (smbus.h) and the concrete users (early_smbus.c and cs5536.c).
After the switch from romstage to ramstage the smb base address
has changed, but that is no problem as the new base address is
stored in bar0 of the ISA bridge. It could also be read via msr,
but via PCI it is simpler. I used the following patch as
reference on how to readout the new base address:
http://lists.laptop.org/pipermail/commits-kernel/2006-November/000178.html
Change-Id: I9f86a1e474368c62f9ed3a95edfb3e63117aa156
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1243
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
We don't ever free memory in coreboot, hence drop spi_flash_free() and
spi_free_slave()
Change-Id: I0ca3f78574ceb4516e7d33c06ab1a58abfb3b0ec
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1273
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Set the default location of hudson firmware to 3rdparty.
Move UMA code from mainboard to northbridge.
Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1241
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.
It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.
Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Hudson code has been integrated from CIMx to AGESA. This patch is about the wrapper.
Change-Id: I63d951982140b82a3a77a97eb3d55fc75fc0caa3
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1157
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
awk on Cygwin created the UTF-8 value for the 0xff code point,
which makes it two bytes wide. This broke the build.
Change-Id: I4937ae7ce1136ba7a76d05b42f9dd2771203175d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1164
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
The wrapper for Trinity. Support S3. Parme is a example board.
Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1156
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Required for Supermicro X7DB8, which needs the FBDIMM clock generator
setup during romstage.
Change-Id: I30ca8354087e851487aee0614595782131d4d9bc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1116
Tested-by: build bot (Jenkins)
i3100/i5000 have a second IOAPIC which handles IRQs for PCI-X.
Add code to enable it.
Change-Id: Ib447628f501b152c8adc9c7c89bd09b5615b9e5a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1118
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The constant value 0x100000000 is used in linker scripts to calculate
offsets from the end of 32-bit-addressed memory. There is nothing
wrong with it, but 32-bit versions of ld do the calculation wrong.
Change-Id: I4e27c6fd0c864b4d98f686588bf78c7aa48bcba8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1129
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
- Add #define to allow the FADT PM Profile to be overridden.
- Change the location of the PMA_CNT_BLOCK_ADDRESS to match
current documentation.
- cst_cnt should be 0 if smi_cmd == 0
- add a couple of default access sizes.
- Add a couple of #define values for unsupported C2 & C3 entries.
- Add PM Profile override value into amd/persimmon platform.
This does not use the #defines in acpi.h so that the files that
include this don't all need to start including acpi.h.
Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1055
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This change adds utility functions which allow to read any GPIO pin,
as well as a vector of GPIO pin values.
As presented, these functions will be available to Sandy Bridge and
Ivy Bridge systems only.
There is no error checking: trying to read GPIO pin number which
exceeds actual number of pins will return zero, trying to read GPIO
which is not actually configured as such will return unpredictable
value.
When reading a GPIO pin vector, the pin numbers are passed in an
array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a
three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass
pointer to array of {4, 2, 15, -1}.
Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1049
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Right now coreboot compilation fails when SPI flash debugging is
enabled. Fix it by using the right set of memory functions.
Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1044
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Experiments have shown that writing plain value of 6 at byte io
address of 0xcf9 causes the systems to reset and reboot reliably.
Change-Id: Ie900e4b4014cded868647372b027918b7ff72578
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Shawn Nematbakhsh