Commit Graph

2346 Commits

Author SHA1 Message Date
Alexander Couzens aa3dd5d5db inteltool: add `-s` to dump spi bar and bios_cntl registers
Change-Id: I3bb5dc23885af8c992456ee5e4bd374cd4b813bf
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8049
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-01-08 17:49:58 +01:00
Hung-Te Lin 0780d67ffe util/cbfstool: Fix byte-ordering for payload type field.
In https://chromium-review.googlesource.com/181272 the payload->type has been
changed to big-endian (network ordering) but the cbfs_image is still parsing
type as host ordering, which caused printing cbfs image verbosely
(cbfstool imge print -v) to fail to find entry field and print numerous
garbage output.

Payload fields should be always parsed in big-endian (network ordering).

BUG=none
TEST=make; cbfstool image.bin print -v -v -v # see payloads correctly

Original-Change-Id: If1ac355b8847fb54988069f694bd2f317ce49a1a
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200158
Original-Reviewed-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 423f7dd28f8b071692d57401e144232d5ee2e479)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5a4694e887c7ff48d8d0713bb5808c29256141a9
Reviewed-on: http://review.coreboot.org/8005
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-03 17:33:13 +01:00
Vadim Bendebury 8b143c5c8b cbmem: use a single id to name mapping table
CBMEM IDs are converted to symbolic names by both target and host
code. Keep the conversion table in one place to avoid getting out of
sync.

BUG=none
TEST=manual
  . the new firmware still displays proper CBMEM table entry descriptions:

    coreboot table: 276 bytes.
    CBMEM ROOT  0. 5ffff000 00001000
    COREBOOT    1. 5fffd000 00002000

  . running make in util/cbmem still succeeds

Original-Change-Id: I0bd9d288f9e6432b531cea2ae011a6935a228c7a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199791
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5217446a536bb1ba874e162c6e2e16643caa592a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0d839316e9697bd3afa0b60490a840d39902dfb3
Reviewed-on: http://review.coreboot.org/7938
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-30 19:17:47 +01:00
Patrick Georgi 1dda372582 abuild: silence make
make called within make prints 'Entering directory'
cruft which confuses the architecture support test.
Silence it.

Change-Id: I7ce7e0ff49e9317fe736ed80f5f18186d416ae63
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7968
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-12-29 18:44:07 +01:00
Kyösti Mälkki f9b8ed86dd cbfstool: Fix update-fit command
Regression in commit 3fcde22 caused parse_microcode_blob() to access
data outside cpu_microcode_blob.bin file in CBFS and create invalid
Intel Firmware Interface Table entries.

Change-Id: I1a687060084c2acd6cac5f5053b74a332b4ac714
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7958
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-28 19:58:35 +01:00
Alexandru Gagniuc 6c90f3334e util: Remove 'getpir' and 'mptable' tools
They create output in an obsolete form, are not actively maintained,
and the quality of the output is not better than randomly copy
pasting from other boards. These tools are no longer of any practical
value. remove them.

Change-Id: I49d7c5c86b908e08a3d79a06f5cb5b28cea1c806
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5158
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-19 21:15:18 +01:00
Felix Held 5eabe25a69 util/superiotool: change displayed name of chip id 0xc333 (nct6776)
nct6776f and nct6776d are just two package variants containing the same die

Change-Id: I4d319fa0e791e66ad04857dede2fdfc8e42dd45a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7806
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-19 19:01:47 +01:00
Felix Held 4a699d12c5 util/superiotool: fix default values for nct6776 (rev. c)
change default values according to the datasheet in revision 1.2

Change-Id: Iec1d55dd7b906a7a41940f3f8e42413922883efd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7805
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-19 19:01:27 +01:00
Scott Duplichan f2c9837e6f ifdtool: Add O_BINARY to open flags for Windows compatibility
Windows requires O_BINARY when opening a binary file. Otherwise
\n characters get expanded to \r\n and <ctrl>z is treated as
end of file. For compatibility with non-Windows hosts, the patch
defines O_BINARY if it is not already defined.

Change-Id: I04cd609b644b1edbe9104153b43b9996811ffd38
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/7789
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19 18:55:48 +01:00
Scott Duplichan e1a4dc803a arm_boot_tools: Add 'b' to fopen flags for Windows compatibility
Windows requires the 'b' (binary) flag when using fopen to open a
binary file. Otherwise \n characters get expanded to \r\n and <ctrl>z
is treated as end of file.

Change-Id: I3b85e4f9a8f7749801a39154881fe2eedd33f9b8
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/7790
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19 18:55:34 +01:00
Patrick Georgi efb2a8f7f3 nvidia/cbootimage: update to latest upstream
Scott Duplichan provided a win32 related fix that
we want to use.

Change-Id: I791b470f9f6c5bf140fc190d290741f35f05d254
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7827
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18 02:21:38 +01:00
Martin Roth 51dde6fe3b inteltool: Start adding Bay Trail
- Add silvermont (Bay Trail core) MSRs - these are shared with
rangeley/avoton.
- Add GPIO values and GPIO muxing information.
- Add Bay Trail to the PM list.

Still to do:
- Northbridge functionality (RCBA, Memory timings, etc.)
- Add Graphics registers

Change-Id: I9fe0c0f1efe5f4344aeb3bad3f13037555109060
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-16 00:42:13 +01:00
Scott Duplichan 4270a9777c buildgcc: Fix msys2 crossgcc build fail
A leading double slash can result when $DESTDIR/$TARGETDIR is expanded
in the libelf portion of buildgcc. The leading double slash causes buildgcc to fail when run from Windows/Msys2. Replace $DESTDIR/$TARGETDIR
with $DESTDIR$TARGETDIR to avoid the problem.

Change-Id: Ide2bae41c07c1566f80104c3a2e2acab53de0d17
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/7788
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-15 16:49:42 +01:00
Alexandru Gagniuc 0f0d497217 abuild: Don't print "Using payload ..." message in quiet mode
It's not useful in quiet mode, and is very distracting.

Change-Id: I59dc8caa22b66980560d5afb76eae801efaa29ad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/124
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-11 05:10:27 +01:00
Patrick Georgi e420139a52 crossgcc: clean up aarch64 target integration
We already have aarch64 targets. Extend the "all" target.

Change-Id: I74d9bf5123695318c15b73c89f170f3ebb20aa80
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7729
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-12-10 10:22:58 +01:00
Martin Roth ddb7a9d4a1 abuild: update output so multithreaded is decipherable
- add a 'quiet' mode that only prints important messages
- add vendor/mainboard to all strings printed

With quiet on, multithreaded looks like this:
skipping google/storm because we're missing compilers for (arm armv4 armv7)
iwill/dk8_htx built successfully. (took 5s)
jetway/j7f2 built successfully. (took 6s)
iwill/dk8x built successfully. (took 8s)
iwill/dk8s2 built successfully. (took 8s)
jetway/j7f4k1g5d built successfully. (took 10s)

With quiet off, single threaded now looks like this:
Building intel/emeraldlake2
Creating config file for intel/emeraldlake2...
    intel/emeraldlake2 (blobs, ccache)
intel/emeraldlake2 config created.
Compiling intel/emeraldlake2 image...
intel/emeraldlake2 built successfully. (took 5s)

And quiet off multithreaded looks like this:
Building iwill/dk8_htx
Creating config file for iwill/dk8_htx...
    iwill/dk8_htx (blobs, ccache)
intel/mohonpeak config created.
Compiling intel/mohonpeak image on 1 cpu...
intel/minnowmax config created.
--- snip ---
intel/mtarvon built successfully. (took 4s)
Building iwill/dk8s2
Creating config file for iwill/dk8s2...
    iwill/dk8s2 (blobs, ccache)
intel/mohonpeak built successfully. (took 5s)
Building iwill/dk8x

Change-Id: Ib7b9a625d77bb8e0663afc00d7133e415866ecec
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7716
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-10 00:17:31 +01:00
Marcelo Povoa 9b56b44eb6 aarch64: Add aarch64-elf toolchain to crossgcc Makefile
BUG=None
BRANCH=none
TEST=Build crosgcc for aarch64-elf
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>

Original-Change-Id: Ifc886b6bd125552855ad1cf49ee7c1b7a0350895
Original-Reviewed-on: https://chromium-review.googlesource.com/186413
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Marcelo Póvoa <marcelogp@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org>
(cherry picked from commit 9959047c82c96108f4bdedad1db0219fcdc85378)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5e781443bb11a7db3420bb8cfc447de8494b1d24
Reviewed-on: http://review.coreboot.org/7661
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-09 18:40:17 +01:00
Marcelo Povoa dcc1c86c7f aarch64: Add ELF support
BUG=None
BRANCH=none
TEST=Build coreboot
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>

Original-Change-Id: I38684794fdf5bd95a32f157128434a13f5e2a2d5
Original-Reviewed-on: https://chromium-review.googlesource.com/185271
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Marcelo Póvoa <marcelogp@chromium.org>
Original-Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org>
(cherry picked from commit 67b74d3dc98a773c3d82b141af178b13e9bb6c06)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id82a31dc94bb181f2d24eddcbfbfb6d6cdc99643
Reviewed-on: http://review.coreboot.org/7659
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09 18:39:58 +01:00
Martin Roth 48a243b16e utils: Remove references to tracker from manpages
abuild, inteltool, and superiotool's manpages still referenced reporting
bugs to tracker.coreboot.org.  Remove that url and change the message
to point to the coreboot mailing list instead.

Change-Id: I7a85bc2b36ccdb7f3798a39a08345c1a02a67e65
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7712
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-09 03:02:56 +01:00
Vladimir Serbinenko 2697c0767b to-wiki.sh: Show the same status for clones.
While it may not be the best way theoretically as theoretically only one
of clones may fail if clones are not perfect, in practice there is more
variance between e.g. different X60 variants than between most of the clones,
yet we put all X60 variants together.
Also in most cases we don't even have a way to tell the clones apart.

Change-Id: I786aeed55300026fae0d9f0497d0c830a9f5e452
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7564
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-04 09:03:24 +01:00
Paul Menzel 29635415a6 util/cbmem: Print name instead of ID of CBMEM_ID_SMM_SAVE_SPACE
Commit b4b9eb39 (x86: provide infrastructure to backup default SMM
region) introduced the new CBMEM type `CBMEM_ID_SMM_SAVE_SPACE`, but
did not add its name `SMM BACKUP` to the utility `cbmem`, causing the
following output, when running `cbmem` on a system making
use of `BACKUP_DEFAULT_SMM_REGION`.

	 7. 07e9acee   7f7e5000   00010000

Fix that by adding the name `SMM BACKUP` to the struct
`cbmem_id_to_name`.

Change-Id: Ib24088c07af4daf6b7d8d5854283b5faa2ad6503
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7176
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-03 12:33:43 +01:00
Patrick Georgi 59ab4e99ee nvramtool: make sure that strings are 0-terminated
The call site expects them to be.

Change-Id: Ic05fc5831f5743d94fe617dfb3b9e329f01866d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7621
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-02 11:02:17 +01:00
Andrew Engelbrecht e8905312f0 nvramtool: cmos_read(): Use malloc() instead of alloca()
Fixes crash occurring when 'nvramtool -a' tried to free a prematurely
freed pointer. (Tested on x60)

malloc() is correct because the pointer is accessed outside the calling
function. The pointer is freed in the parent function list_cmos_entry().

Change-Id: I1723f09740657f0f0d9e6954bd6d11c0a3820a42
Signed-off-by: Andrew Engelbrecht <sudoman@ninthfloor.org>
Reviewed-on: http://review.coreboot.org/7620
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-02 10:15:00 +01:00
Patrick Georgi 32a5a5f467 buildgcc: support DESTDIR for libelf
The libelf build system doesn't support the
DESTDIR variable. Work around by mangling prefix
when installing.

Change-Id: I3a56eb2bf919bcb9b586b945dce26a02dbaff931
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7613
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-30 12:20:17 +01:00
Patrick Georgi 02ac6c3572 build system: only do the compiler test for gcc
There isn't a history of broken clang compilers yet
so let's give it a chance.

Change-Id: Iddb63700e3850116313c1ddee69111f936191055
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7607
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30 12:20:11 +01:00
Vladimir Serbinenko 8251e9070c Rewrite board_status in go.
This allows easy creation of redistribuable binary.

Change-Id: I12a82d509cd4bd46baeb4f4066e509c69301ab95
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7565
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-26 23:18:58 +01:00
Vladimir Serbinenko bcc3a87c7e lint-stable: Ignore .bin files for whitespace check.
.bin is the most convenient format for storing SPDs and since it's
not text format, whitespace check is useless and gives false positives.

Change-Id: I8a7569eac8a1dfbffabe166a38e4dd3e895fdef1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7567
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-25 23:47:43 +01:00
Patrick Georgi e00196e803 buildgcc: Fix documentation
Change-Id: I3983d7a393260238b75e9f52e9451b454c551c30
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7550
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-23 09:08:27 +01:00
Francis Rowe 3fb8b0d75b util/cbfstool/cbfs-mkstage.c: Fix build issue on 32-bit x86
Fixes regression caused by commit 405304ac
(cbfstool: Add option to ignore section in add-stage)

Change-Id: If9e3eea9ab2c05027f660d0057a635abf981b901
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7545
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-21 19:46:18 +01:00
Patrick Georgi 3bff5d9064 crossgcc: Add buildsystem support for aarch64 compiler
This adds the crosstools-aarch64 and crossgcc-aarch64
make rules to create a toolchain (with or without gdb)
for AArch64 targets.

Also adapt xcompile, since it's aarch64-elf.

Change-Id: I6fbe09d44ee8b8493d3cd8dbbba869b409e311f7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7527
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-20 13:54:59 +01:00
Patrick Georgi d730ca8529 crossgcc: Update GCC from 4.7.3 to 4.8.3 and update to version 1.25
gcc 4.9.2 fails on our tree right now. We should clean that
up and test before we make it the reference version.

Also, the AMD K8/Fam10 issue we had last year, for which
Vladimir provided an "untested" fix (which is in,
commit a6c29fe684), isn't
reproducible: I boot-tested an unpublished AMD K8 board
with coreboot built with gcc 4.8.3.
(Disclaimer: since the old issue depended on compiler
decisions on register allocation, any change to code
or compiler could mix up things in semi-random ways.)

Change-Id: I8f1460a8da2c9e2d581482b22a4824b10b8987fa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7526
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-20 13:54:57 +01:00
Patrick Georgi 129462da1b kconfig: create files in target directory if requested
Otherwise rename() fails when used across filesystem
boundaries.

Change-Id: I22a62310f0e46ac9cfee50b7e9eeed93536ed409
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7504
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-18 08:25:50 +01:00
Patrick Georgi 7d221b4ef2 nvidia/cbootimage: update to master
It contains a number of fixes to bugs found
by Coverity Scan.

Change-Id: I362a069afd37783f59d8831e44ae885e8490819e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7392
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-14 16:38:33 +01:00
Patrick Georgi c32b4a40d2 abuild: pass compiler configuration options to tool building step
This is required to run abuild parallely with clang
without the canonical coreboot toolchain installed.

Change-Id: Iea56d3f552d50ab6e762afa134091b0d8e38792c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7369
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-09 22:46:47 +01:00
Felix Held fac95e3bfe inteltool: add more hardware IDs and PCIEXBAR/PXPEPBAR read support
Add IDs of some SNB and Haswell chips; use more descriptive names.
Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell.

Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7360
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2014-11-09 21:11:27 +01:00
Mathias Krause 5ad6ec55f8 inteltool: Fix message in case of multiple LPC controllers
If we find multiple LPC controllers, we want to tell the user that we'll
ignore all but the first. However, we use 'dev' in the message (the
current device found) instead of 'sb' (the one we want to use).

Fix the message by using 'sb' and break the loop right away in this
case. It's sufficient to tell the user once which LPC controller we'll
use.

Change-Id: Ibd27e40525fabe8c63b112691ad49fd994c70a48
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/7342
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-11-06 06:45:48 +01:00
Felix Held 0cc8f29316 inteltool: Add support for Sandy Bridge desktop processors
Change-Id: I5e68b89c30d5550e4bce5c3e4c7b0689c38756bc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7337
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2014-11-06 06:44:29 +01:00
Vladimir Serbinenko 44bc11c3eb inteltool: Show more info on sandy/ivy.
Change-Id: I408614e743ab6f0f447b327c01d8f4dacf787124
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6692
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-05 00:02:25 +01:00
Vladimir Serbinenko 9c4f1b8e05 inteltool/sandybridge: Kill mch_registers codepath.
It never worked.

Change-Id: Ic68614bb8ed481babf54b4f9d8db00635755f4d1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7324
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 23:01:05 +01:00
Patrick Georgi 511f82398e abuild: fix cross compiler test
Actually abort if a cross compiler is missing, but also handle
subarchitectures (currently: armv4 and armv7 for arm)
properly.

Change-Id: Idf37fb029178df6f2ac029466c66aaa2010bdbd2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7297
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 17:28:42 +01:00
Dennis Wassenberg ae6685fe4f inteltool: Add support for Haswell ULT and Lynx Point LP
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Change-Id: I2d5a31c831afeb92522b2673fde82922dc4efca5
Reviewed-on: http://review.coreboot.org/7275
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-04 15:01:04 +01:00
Furquan Shaikh 405304aca3 cbfstool: Add option to ignore section in add-stage
Allow add-stage to have an optional parameter for ignoring any section. This is
required to ensure proper operation of elf_to_stage in case of loadable segments
with zero filesize.

Change-Id: I49ad62c2a4260ab9cec173c80c0f16923fc66c79
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7304
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 00:52:33 +01:00
Furquan Shaikh cc6f84c411 cbfstool: Convert cbfs-mkstage.c into pelf
Change cbfs-mkstage to use parsed elf instead of calling elf_headers. That
allows us to have access to the complete elf including the string table.

Change-Id: Ie767d28bdf41af38d1df0bce54bc0ada45123136
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7303
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 00:52:17 +01:00
Stefan Tauner b75a39a2fe inteltool: refine GPIO and PMBASE/TCO printing on Ibex Peak/5 Series
Nicolas Reinecke was noticing that in my Lenovo T410s logs the GPIO*3
settings were missing. This led to some investigation and this patch, thanks!

Change-Id: I7ba28aa00d10f988a7fe81e61d2e216b54a11006
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/7239
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-02 15:59:01 +01:00
Vadim Bendebury a85a92d292 A tool for IPQ8064 encapsulation
This is a copy of the tool provided by the vendor. It adds a
header which tells the early stage loader where to load the next phase
blob for execution. It is going to be used to encapsulate the
bootblock.

Usage of this tool is as follows:

  ipqheader.py <base-addr> <input-file> <output-file>

Old-Change-Id: I448c006719f4f3dd5a6716ff2e47f7fc275c805e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193494
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 201630f8637eb627f0894ecd7bceb31017244ad4)

Make ipqheader.py executable

Modify the utility to become a Linux executable. While at it, fix the
program name reported by error messages.

Old-Change-Id: I25061d43fdea72655a696deb9e494e9c7382f670
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193495
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit bbbf69c754aa3b6a1bf17ab3ced1c739c3ee0688)

ipq8064: SBL headers must have 4 byte aligned blob sizes

It turns out that for SBL3 to load the next phase, the sizes in the
MBN header must be 4 byres aligned. This change makes sure that this
requirement is enforced.

Old-Change-Id: Ia64f04bb281ae772b060d2f7713c98dd348972ba
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196167
(cherry picked from commit fa6a52a07cb87ecf2538a6b0d47605d79104e4cc)

Add proper license to the ipqheader tool

This patch adds a vanilla BSD 3-Clause license.

Original-Change-Id: I9da7176e670b598808ef5be2461b6105a4c5f6c5
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225783
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Tested-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a0c47a8d74f1ac131c91e978b6d68bbcfaa52c37)

Squashed 4 commits for the ipqheader util.

Change-Id: I144c01947a89e1348a06aa82590e972e2ec31247
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/6976
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-10-28 19:31:26 +01:00
Aaron Durbin 785e47bbf3 rmodtool: add support for ARM
Add support for creating ARM rmodules. There are 3 expected
relocations for an ARM rmodule:
- R_ARM_ABS32
- R_ARM_THM_PC22
- R_ARM_THM_JUMP24

R_ARM_ABS32 is the only type that needs to emitted for relocation
as the other 2 are relative relocations.

BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built vbootstub for ARM device.

Original-Change-Id: I0c22d4abca970e82ccd60b33fed700b96e3e52fb
Original-Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190922
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit a642102ba7ace5c1829abe7732199eda6646950a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib3b3c90ebb672d8d6a537df896b97dc82c6186cc
Reviewed-on: http://review.coreboot.org/7204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-28 18:15:18 +01:00
Gabe Black 845aa1416d cbfstool: If compression fails, warn and use the uncompressed data.
The LZMA compression algorithm, currently the only one available, will fail
if you ask it to write more data to the output than you've given it space for.
The code that calls into LZMA allocates an output buffer the same size as the
input, so if compression increases the size of the output the call will fail.
The caller(s) were written to assume that the call succeeded and check the
returned length to see if the size would have increased, but that will never
happen with LZMA.

Rather than try to rework the LZMA library to dynamically resize the output
buffer or try to guess what the maximal size the data could expand to is, this
change makes the caller simply print a warning and disable compression if the
call failed for some reason.

This may lead to images that are larger than necessary if compression fails
for some other reason and the user doesn't notice, but since compression
errors were ignored entirely until very recently that will hopefully not be
a problem in practice, and we should be guaranteed to at least produce a
correct image.

Original-Change-Id: I5f59529c2d48e9c4c2e011018b40ec336c4fcca8
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/187365
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit b9f622a554d5fb9a9aff839c64e11acb27785f13)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>

Change-Id: I5f59529c2d48e9c4c2e011018b40ec336c4fcca8
Reviewed-on: http://review.coreboot.org/6958
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28 17:08:29 +01:00
Patrick Georgi 667c7a3b23 util/fletcher: fix debug option parsing
sizeof(char[]-type+1) isn't very useful. Since one of
the strings is constant, we also don't need to use
strncmp that string's length. While at it, str*cmp don't
return booleans, so check for value instead of faux bools.

Change-Id: Iebb194a60eac454dafeade75f135df92068cf4ab
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6988
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-18 14:45:42 +02:00
Patrick Georgi 02802dfa5a abuild: skip boards for which we lack a cross compiler
We don't support them, they won't ever pass the build test,
so no need to report an error.

Change-Id: I2409a79f3c0d66a79b0e065e6b9ebf62d0359b3e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7121
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-18 14:45:36 +02:00
Patrick Georgi 0a76bccc94 abuild: don't track architecture
This didn't work for a while, and we don't _really_ need it.

Change-Id: I952243f30e985e7577cd511f40957066db6dd3c5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7120
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-18 14:45:36 +02:00
Patrick Georgi 96990a285d cbfstool: free memory
Change-Id: Ic53127a61154460fa3741a92a3b2de0eba446e9f
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6987
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-18 14:45:15 +02:00
Paul Menzel 747c07f08a util/cbmem: Fix CBMEM TOC printing
Since commit c0199078 (cbmem utility: Find actual CBMEM area) [1], at least on
the Lenovo X201, X230 and X60, printing the CBMEM table of contents did
not work.  It still worked on the ASRock E350M1 though.

	$ sudo /src/coreboot/util/cbmem/cbmem -l --verbose # Lenovo X60t
	Looking for coreboot table at 0
	Mapping 1MB of physical memory at 0x0.
	Found!
	  coreboot table entry 0x11
	    Found forwarding entry.
	Unmapping 1MB of virtual memory at 0xb74dc000.
	Looking for coreboot table at 7f6c4000
	Mapping 1MB of physical memory at 0x7f6c4000.
	Found!
	  coreboot table entry 0xc8
	  coreboot table entry 0x01
	    Found memory map.
	  coreboot table entry 0x03
	  coreboot table entry 0x04
	  coreboot table entry 0x05
	  coreboot table entry 0x06
	  coreboot table entry 0x07
	  coreboot table entry 0x08
	  coreboot table entry 0x09
	  coreboot table entry 0x0a
	  coreboot table entry 0x16
	    Found timestamp table.
	      cbmem_addr = 7f7dd000
	  coreboot table entry 0x17
	    Found cbmem console.
	      cbmem_addr = 7f7de000
	Unmapping 1MB of virtual memory at 0xb74dc000.
	No coreboot CBMEM area found!

The address of the boot info record has to be used for checking, that reading
takes place in the bounds of the boot info record.

	$ sudo ~/src/coreboot/util/cbmem/cbmem -l # Lenovo X60
	CBMEM table of contents:
	    ID           START      LENGTH
	[…]

Big thanks to David and Stefan for their help.

[1] http://review.coreboot.org/2117

Change-Id: I1eb09a6445d9ea17e1e16b6866dece74315d3c73
Found-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7093
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18 14:29:29 +02:00
Paul Menzel e4626bfc5b util/cbmem/cbmem: Remove obsolete comment
Originally the utility cbmem was just used for reading out the time
stamps and was later extented. The removed comment is currently at the
wrong place and `cbmem` does much more now, so that the comment is just
removed.

Change-Id: Ief1d7aef38a4b439e3e224e6e6c65f7aa57f821f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7091
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-10-18 10:29:33 +02:00
Ronald G. Minnich 833bf20f92 RISCV: add this architecture to cbfstool
Change-Id: I6d972e595f12585cda08e1a6d2b94b4bf4f212f5
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7067
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-16 18:05:13 +02:00
Ronald G. Minnich b9a0809fae xcompile: detect and use RISCV binaries
RISCV is a new architecture. This change simply setups up xcompile
to detect and use RISCV compilers if they are found.

Change-Id: Iad1a88ef2e3c8dd1e601549aeca26fb29b2bc7ae
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-08 15:44:17 +02:00
Ronald G. Minnich 34fc4ab80b mkelfimage: remove
It's not been needed for years, is definitely not needed now
that cbfstool parses bzImages, and its presence keeps confusing
people.

Also, rewrite history. We never mentioned mkelfimage in the
documentation. Never, ever, ever.

Change-Id: Id96a57906ba6a423b06a8f4140d2efde6f280d55
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7021
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-08 14:27:24 +02:00
Aaron Durbin ffda804b52 sconfig: add cpu device type
In order to enumerate CPU devices that are non-x86 (read: no lapic)
provide a generic 'cpu' device.

Change-Id: Ifeafdad8076935c3448784e6958117002509acbf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-07 21:03:25 +02:00
Patrick Georgi 758f26aa2d nvidia/cbootimage: avoid upstream's build system
It brings in useless dependencies, a weird autotools
configuration, and tons of pain everywhere.

Instead just build things ourselves.

Change-Id: I67f06e711cb9dcd594363bc1a4f99d3273074549
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6986
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-02 10:26:58 +02:00
Gabe Black dbd006b082 cbfstool: Propogate compression errors back to the caller.
When compression fails for whatever reason, the caller should know about it
rather than blindly assuming it worked correctly. That can prevent half
compressed data from ending up in the image.

This is currently happening for a segment of depthcharge which is triggering
a failure in LZMA. The size of the "compressed" data is never set and is
recorded as zero, and that segment effectively isn't loaded during boot.

Change-Id: Idbff01f5413d030bbf5382712780bbd0b9e83bc7
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/187364
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit be48f3e41eaf0eaf6686c61c439095fc56883cec)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6960
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-25 20:26:04 +02:00
Furquan Shaikh 7eb809af40 cbfstool: Add AARCH64 reloc types to elf.h
Change-Id: Ifd4726491e01c3acebd3dfc326c1be994b0aefb8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214328
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6955
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-09-23 22:28:20 +02:00
Furquan Shaikh 4194338e62 mkelfimage: Add EM_AARCH64 as elf image type for arm64
Change-Id: I5510a4fe5085430b767161133113578b7cffa237
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214327
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6954
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-09-23 22:27:31 +02:00
Furquan Shaikh b237c10899 rmodtool: Allow rmodules with 0 relocations
Currently, rmodules with 0 relocations are not allowed. Fix this by skipping
addition of .rmodules section on 0 relocs.

Change-Id: I7a39cf409a5f2bc808967d2b5334a15891c4748e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/6774
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-09-23 22:26:57 +02:00
Furquan Shaikh 2af76f4bdc coreboot arm64: Add support for arm64 into coreboot framework
Add support for enabling different coreboot stages (bootblock, romstage and
ramstage) to have arm64 architecture. Most of the files have been copied over
from arm/ or arm64-generic work.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197397
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 033ba96516805502673ac7404bc97e6ce4e2a934)

This patch is essentially a squash of aarch64 changes made by
these patches:

d955885 coreboot: Rename coreboot_ram stage to ramstage
a492761 cbmem console: Locate the preram console with a symbol instead of a sect
96e7f0e aarch64: Enable early icache and migrate SCTLR from EL3
3f854dc aarch64: Pass coreboot table in jmp_to_elf_entry
ab3ecaf aarch64/foundation-armv8: Set up RAM area and enter ramstage
25fd2e9 aarch64: Remove CAR definitions from early_variables.h
65bf77d aarch64/foundation-armv8: Enable DYNAMIC_CBMEM
9484873 aarch64: Change default exception level to EL2
7a152c3 aarch64: Fix formatting of exception registers dump
6946464 aarch64: Implement basic exception handling
c732a9d aarch64/foundation-armv8: Basic bootblock implementation
3bc412c aarch64: Comment out some parts of code to allow build
ab5be71 Add initial aarch64 support

The ramstage support is the only portion that has been tested
on actual hardware. Bootblock and romstage support may require
modifications to run on hardware.

Change-Id: Icd59bec55c963a471a50e30972a8092e4c9d2fb2
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6915
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-09-23 18:10:32 +02:00
Ronald G. Minnich 5f43184349 cbfstool: add aarch64 as a name
The aarch64 is not really an arm variant, it's sufficiently
different that it can be considered (for purposes of cbfs, certainly)
to be a new architecture.

Add a constant in cbfs.h and strings to correspond to it.
Note that with the new cbfstool support that we added earlier,
the actual use of aarch64 ELF files actually "just works" (at
least when tested earlier).

Change-Id: Ib4900900d99c9aae6eef858d8ee097709368c4d4
Reviewed-on: https://chromium-review.googlesource.com/180221
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit f836e14695827b2667804bc1058e08ec7b297921)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6896
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-15 19:00:12 +02:00
Vladimir Serbinenko 76998336aa to-wiki: Add IVYBRIDGE_NATIVE to the list of ivybridge names.
Change-Id: I6e63abd9491a76e362347b7616e00104305827ee
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6691
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-13 20:22:26 +02:00
Vladimir Serbinenko f4ea9b2551 towiki.sh: Rename GM45 slot and cpu to correct ones.
Change-Id: Idc8135911549ac39c28932065897ca6643c13656
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6690
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-13 20:22:18 +02:00
Stefan Reinauer 8f50e53a4b cbfstool: Fix architecture check when adding payload
In the process of rewriting cbfstool for ARM and using
a new internal API a regression was introduced that would
silently let you add an ARM payload into an x86 CBFS image
and the other way around. This patch fixes cbfstool to
produce an error in that case again.

Change-Id: I37ee65a467d9658d0846c2cf43b582e285f1a8f8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176711
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 8f74f3f5227e440ae46b59f8fd692f679f3ada2d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6879
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-12 22:07:19 +02:00
Gabe Black b6b1077eec exynos: Install the BL1 and set the checksum in the Makefile.
Install the BL1 and set up the checksum in the Makefile instead of relying on
post processing. Import the exynos checksum script, split it in two and
simplify it significantly. Stop putting the CBFS header in the midst of the
bootblock so that it can be checksummed before CBFS is put together. Stop
saving space for it and leaving an anchor in the bootblock which nobody looks
for.

Change-Id: Icbb5a5914ece60b2827433b6dc29d80db996ea6c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/179229
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit aa3a416705517c0a6ddfdeb19905ac8cafb33df1)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-09 20:01:18 +02:00
Gabe Black 51edd54738 ARM: Generalize armv7 as arm.
There are ARM systems which are essentially heterogeneous multicores where
some cores implement a different ARM architecture version than other cores. A
specific example is the tegra124 which boots on an ARMv4 coprocessor while
most code, including most of the firmware, runs on the main ARMv7 core. To
support SOCs like this, the plan is to generalize the ARM architecture so that
all versions are available, and an SOC/CPU can then select what architecture
variant should be used for each component of the firmware; bootblock,
romstage, and ramstage.

Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171338
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>

ARM: Split out ARMv7 code and make it possible to have other arch versions.

We don't always want to use ARMv7 code when building for ARM, so we should
separate out the ARMv7 code so it can be excluded, and also make it possible
to include code for some other version of the architecture instead, all per
build component for cases where we need more than one architecture version
at a time.

The tegra124 bootblock will ultimately need to be ARMv4, but until we have
some ARMv4 code to switch over to we can leave it set to ARMv7.

Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7
Reviewed-on: https://chromium-review.googlesource.com/171400
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483)

Squashed two related patches for splitting ARM support into general
ARM support and ARMv7 specific pieces.

Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6782
Tested-by: build bot (Jenkins)
2014-09-08 18:59:23 +02:00
Isaac Christensen 94b4a266fb nvidia-cbootimage: add submodule
Change-Id: I3ad8eed42255db426987065190c197baead40673
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6836
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08 18:58:40 +02:00
Patrick Georgi 34e7615235 romcc: avoid use-after-free
Windows bugchecks on this for a while, so we ifndef'd the free() call out.
Now some Linuxes (depending on their glibc) also fail on it, so just
remove the call altogether at the cost of some leaked memory (couple
hundred kilobytes) because tracking down the precise fix is too hard.

In case someone wants to fix it, valgrind sees the issues, so
revert this change and work on romcc's memory management until valgrind
is happy.
To get a fix in, provide a good explanation why your change is actually
the right way to fix it - for silencing valgrind, this change will do.

Change-Id: Iae3f847e09a0d7bcb8bb4f50983a1b0727570b23
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6846
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-09-06 09:21:07 +02:00
Curt Brune 3c12cb0384 cbfstool:linux_trampoline: config CS and DS segment descriptors
The Linux trampoline code does not set up the segment descriptors for
__BOOT_CS and __BOOT_DS as described in the Linux kernel
documentation:

  ... a GDT must be loaded with the descriptors for selectors
  __BOOT_CS(0x10) and __BOOT_DS(0x18); both descriptors must be 4G
  flat segment; __BOOT_CS must have execute/read permission, and
  __BOOT_DS must have read/write permission;

This is not a problem when launching a Linux payload from coreboot, as
coreboot configures the segment descriptors at selectors 0x10 and
0x18.  Coreboot configures these selectors in the ramstage to match
what the Linux kernel expects (see
coreboot/src/arch/x86/lib/c_start.S).

When the cbfs payload is launched in other environments, SeaBIOS for
example, the segment descriptors are configured differently and the
cbfs Linux payload does not work.

If the cbfs Linux payload is to be used in multiple environments
should the trampoline needs to take care of the descriptors that Linux
requires.

This patch updates the Linux trampoline code to configure the 4G flat
descriptors that Linux expects.  The configuration is borrowed from
the descriptor configs in coreboot/src/arch/x86/lib/c_start.S for
selectors 0x10 and 0x18.

The linux_trampoline code is slightly refractored by defining the
trampoline entry address, 0x40000, as TRAMPOLINE_ENTRY_LOC.  This
definition is moved into a separate header file, linux_trampoline.h.
This header file is now included by both the trampoline assembly
language code and the trampoline loader C code.

The trampoline assembly language code can now use TRAMPOLINE_ENTRY_LOC
as scratch space for the sgdt CPU instruction.

Testing Done:

Verified the Linux payload is booted correctly in the following
environments:

1.  Coreboot -> Linux Payload

2.  Coreboot -> SeaBIOS -> Linux Payload: (previously did not work)

Change-Id: I888f74ff43073a6b7318f6713a8d4ecb804c0162
Signed-off-by: Curt Brune <curt@cumulusnetworks.com>
Reviewed-on: http://review.coreboot.org/6796
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-04 23:34:32 +02:00
Patrick Georgi f9d7252a8d lint: simplify board-status check
git can do lots of things by itself, no need to parse
its output and redo that.

Change-Id: Id2cdd2ea8d34c1ba2b0abddc88e1f3260d74f47d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6798
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-03 00:23:26 +02:00
Bruce Griffith 3a2310e05c AMD Steppe Eagle: Add 32-bit Fletcher's Checksum computation
The AMD Platform Security Processor (PSP) requires a Fletcher's
Checksum at the end of the PSP directory.  This code implements
a Fletcher's Checksum by reading bytes from stdin and writes the
bytes back to stdout with a checksum inserted into the byte stream
at the appropriate offset.

This utility is used on PSP binaries during coreboot build.

Include a runtime debug option such that the command:

	fletcher --print <file.bin >file_with_cksum.bin

will print out the computed checksum value for debugging.  The
compile-time debug option is retained that allows -DDEBUG to
be added to the compilation line.  This option has the same
effect as "--print".

Change-Id: I506a479d8204ca4f8267d53aa152ac4b473dbc75
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6676
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30 00:28:06 +02:00
Aaron Durbin 518a322d58 rmodtool: correct final memory size calculation
Apparently when I originally wrote this I confused myself to no end.
The code/data of an rmodule has a set memory size which is associated
with the .payload section. The relocation entries may increase the
overall footprint of the memory size if the rmodule has no bss but
a lot of relocations. Therefore, just compare relocation entries size
plus the file size of the .payload section with the memory size of the
paylod section. The .empty section is added only when we have not met
the final target size.

Change-Id: I5521dff048ae64a9b6e3c8f84a390eba37c7d0f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6767
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-27 03:20:27 +02:00
Idwer Vollering b123e0d334 util/inteltool: fix typo
Change-Id: I8c30742f6cd759dce4c9641edad107d9e3154975
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/6766
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-26 10:08:30 +02:00
Aaron Durbin 8414d3c0b4 xcompile: always use -march=i686
When compiling coreboot for x86 on gcc the compiler is
free to pick whatever defaults it is using at the time of
gcc's compile/configuration when no -march is specified.
Not properly specifying -march then opens up the use of SSE
instructions for compilation units it should not be used such
as the SMM module as this module doesn't save/restore SSE
registers.

Change-Id: I64d4a6c5fa9fadb4b35bc7097458e992a094dcba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172640
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit d49358f7959bb52c3e7ff67d37c21a1b294adf72)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6716
Tested-by: build bot (Jenkins)
2014-08-25 23:33:20 +02:00
Aaron Durbin bc349b81e9 elfheaders: fix 64-bit ELF writing
The sh_flags for a 64-bit section header entry are
64-bit in size. Correct this.

Change-Id: I2fa79d9a0fb46cc1dfa97c172357bbd2394843e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6737
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-22 21:30:09 +02:00
Vladimir Serbinenko b46f5891d2 board-info: Output errors to stdout like make lint-stable expects
Change-Id: I7eb2283808cde86c79d6b770a176daee57a7f9f2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6696
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18 09:09:22 +02:00
Vladimir Serbinenko fb2a9a9e30 lint-stable: Check that modified boards contain meaningful board_info.txt.
Change-Id: Idd3ff029e16b4b963f13d341dabdc1949c4e9275
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6670
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16 17:17:52 +02:00
Edward O'Callaghan ef3a17bd88 util/inteltool: Typo in dump output for 'GP_IO_SEL3'
The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header
is incorrectly reported as 'GPIO_SEL3'.

Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6459
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13 05:01:58 +02:00
Patrick Georgi dd1aab95a6 nvramtool: plug some memory leaks
Change-Id: I8f672b872862d3448ccd2cf28fd3c05b0108ff8b
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6561
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12 22:15:20 +02:00
Patrick Georgi 32eeff4b6e util: replace fseek/ftell/rewind with fstat
It's a more direct approach to get the file size.

Change-Id: If49df26bf4996bd556c675f3a673d0003b4adf89
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6594
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-12 11:53:24 +02:00
Patrick Georgi 77b182a31a board-status: be protocol agnostic on upload
Generate the board-status repo URL by replacing the
last occurrence of "/coreboot" by "/board-status",
which works across repo URL schemes (gerrit provides
several).

Change-Id: Iccb53bde994be619c1436815e13741d63738edf7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6574
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12 11:52:49 +02:00
Daniele Forsi ea70a5068f util/genprof: improve handling of command line arguments
Accept only one command line argument (the input file name); close input
stream both on error and on success; print more informative error messages
when files could not be opened.

Change-Id: Ib2f0622a332317d7a13f33f1e5787381804c43a9
Found-by: missing fclose()'s found by Cppcheck 1.65
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6573
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12 09:02:44 +02:00
Patrick Georgi 40c845d352 lint: provide better GPL license text test
Still not lint-stable due to too many open issues, but
at least it doesn't try to touch files that aren't part
of the repository anymore.

Change-Id: I654b15480094c7731a7d0d17fa1622a0b41ac34a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6584
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-11 19:13:25 +02:00
Patrick Georgi 4b65c2ad33 lint: improve whitespace test
The whitespace test only trips on files that are part
of the git index - in particular not temporary editor
files or other cruft that doesn't hurt anyone.

Change-Id: I793fcc773845ee02281d8614b07e9c5958126a5a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6582
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-11 19:12:22 +02:00
Patrick Georgi 4ef309e85d board-status: avoid shell error
[ $3 -eq 1 ] fails if no third argument is given.
[ "$3" -eq 1 ] still fails.

Doing a string comparison is robust across shells.

Change-Id: I3ee388fdbe51b7ab9344d86e67827654714d3191
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6576
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-11 08:21:45 +02:00
Patrick Georgi 466ea0c3d3 board-status: remove whitespace
Change-Id: I76ae5e294c157e73d07fd30cdb1c191d78efd5eb
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6581
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-11 06:24:40 +02:00
Patrick Georgi 802ad52180 ifdtool: Provide bounds on string parser
While the result will not be pretty (ie. ifdtool will
mis-parse string components longer than 255 characters),
at least it doesn't overflow stack variables anymore.

Change-Id: I263c5cf823a2d8a863dcece7c4ee0b26475f9fc4
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6562
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-08-10 18:50:30 +02:00
Patrick Georgi a65c21eeb5 cbfstool: free stale memory
The process probably terminates not much later, but in
case anyone reuses the function in something with
longer life-time, free unused resources.

Change-Id: I10c471ee3d9dc9a3ebf08fe4605f223ea59b990e
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6559
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-10 08:20:30 +02:00
Patrick Georgi c5d179123d nvramtool: check for successful seek
Otherwise the following write might end up anywhere.

Change-Id: Ie42d984824e9308bd58b8bb905b6ea823543adf0
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6560
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-10 08:20:09 +02:00
Patrick Georgi b6239b81aa romcc: properly check out-of-range unsigned longs
Testing if an unsigned long is greater than ULONG_T_MAX isn't very
useful. The second half of the test checked for too small values
(ie. <= -ULONG_T_MAX).

In both cases errno is set to ERANGE, so just check for that.

Change-Id: I92bad9d1715673531bef5d5d5756feddeb7674b4
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6568
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-10 08:19:44 +02:00
Patrick Georgi e887ca5a74 cbfstool: fix option parsing
"cbfstool create -B bootblock -s size" (in this order)
would break bootblock selection.

Change-Id: I9a9f5660827c8bf60dae81b519c6f026f3aaa0f3
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6564
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2014-08-09 19:54:09 +02:00
Aaron Durbin ca63027ef7 cbfstool: process cbfs_payload_segment(s) in host byte order
The printing routines of the cbfs_payload_segment assumed the type
could be accessed in host order. Each of the fields need to be
converted to the host order before inspecting the fields. In addition,
this removes all the ntoh*() calls while processing the
cbfs_payload_segment structures.

cbfstool would crash adding entries or just printing entries
containing a payload when -v was passed on the command line.

Change-Id: Iff41c64a99001b9e3920e2e26828c5fd6e671239
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6498
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-08-07 19:05:43 +02:00
Patrick Georgi 6fa6843a8d sconfig: improve argument parsing
Running sconfig with four arguments where the third
does not match /-./ made sconfig use uninitialized
memory to build the output filename.

Change-Id: If4a147ff23771ca9b6a913605af60249be1ca3d0
Found-By: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6483
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04 20:57:12 +02:00
Paul Menzel 80fd01d2cc util/sconfig/main.c: Remove assigned but unused variable `link`
Cppcheck 1.65 report the style style issue below.

	[main.c:434]: (style) Variable 'link' is assigned a value that is never used.

So remove the variable `link` as it is not needed.

Change-Id: Ib77b80b74a70985a76eaa3247c4a43832ef23a59
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6488
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04 20:57:10 +02:00
Patrick Georgi 1f68880e50 sconfig: more careful string resource handling
When parsing a string to numbers, we don't need to copy it.
And when creating strings, we should eventually free them.

Change-Id: I9023fef6e97a1830bc68502be32e79879c1617d4
Found-By: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6484
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04 06:59:51 +02:00
Patrick Georgi 38fa6edf2d ifdtool: Check if file was opened
Check if the new file could in fact be opened before
writing to it.

Change-Id: I6b2d31bf5c18f657fca4dc14fee2f2d5a2e33080
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6477
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-03 15:19:28 +02:00
Patrick Georgi 440daf786a ifdtool: Avoid potential buffer overflow
Filenames of 4091 bytes or more lead to a buffer overflow.

Change-Id: I1b4b3932af096f0fcbfb783ab708ed273d3a844e
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6476
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-03 15:19:27 +02:00
Patrick Georgi edb0a61be4 nvramtool: Close file after use
mmap builds a new reference to the file, so the file
descriptor isn't necessary anymore. Close it.

Change-Id: I639fd13ff8f13cbdfce1d199d75744e56f2b19b3
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6475
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-03 15:19:27 +02:00
Patrick Georgi d11ff6b9df build system: remove duplicate architecture list
Let xcompile pass the list of architectures, given
that it already has it.

Change-Id: I565512d3bef987c9a4e48a39bfd88bacf0b65de9
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6254
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-30 21:06:43 +02:00
Daniele Forsi ddf54b1c8b util/sconfig: fix check for count of command line arguments
Valid invocations are when -s|b|k outputfile is missing (argc == 3)
and when it is followed by the file name (argc == 5); it's an error
when "outputfile" is missing (argc == 4) or when there are more
arguments than expected (argc > 5).
Fixes "Uninitialized argument value" error found by scan-build from
clang version 3.2-11.

Change-Id: I8c489863323eb60cbaa5e82a80f5d78a6ca893c2
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6378
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30 13:16:55 +02:00
Daniele Forsi 201093ef6d util/i915tool: close the file also when fread() returned an error
Change-Id: I92f816aa1351a295287ebbcc78665ac87c318c23
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30 13:16:53 +02:00
Gabe Black 06b13a37f0 cbmem: Terminate the cbmem console at the cursor position.
If the cbmem console buffer isn't zero filled before it's used, there won't be
a terminator at the end. We need to put one at the cursor position manually.

Change-Id: I69870c2b24b67ce3cbcd402b62f3574acb4c2a8f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65300
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8ec61e52a6a27ed518d0abb5a19d6261edf9dab1)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6404
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30 11:49:45 +02:00
Daniele Forsi 8e89847af4 util/cbfstool: free buffer on error path
Fix memory leak found by scan-build from clang version 3.2-11.

Change-Id: Id8f9db46cf42012a0eb0a632c9d83a4eec1989a2
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6379
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30 10:36:00 +02:00
Idwer Vollering b37ee1ee7c util/board_status: use the right location of cbfstool
The cbfstool binary in util/ doesn't exist as often as build/cbfstool does.
Since cbfstool obtains details from coreboot.rom, use the binary in build/

Change-Id: Id7d5632f4e5cbd5ede58cd136c37b0dacee9ff93
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/6299
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-07-28 23:18:56 +02:00
Martin Roth bcd09930d8 board_status.sh minor fixes - no functional changes
- Update some comments
- Whitespace fixes
- change from backticks to $() format for getting command data.

Change-Id: Iaf424224abfd30a3581d0e43a1689cc7c887beec
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6261
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-07-21 17:36:58 +02:00
Martin Roth 8e0071b798 board_status.sh: Read coreboot boot log from a serial device
- Read the boot log from a serial device.

Change-Id: I9daf97fd9b7fc55d0d56d815b185f9b4e3ef9f5a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6260
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
Tested-by: build bot (Jenkins)
2014-07-21 17:35:45 +02:00
Martin Roth 13c7db8fe8 board_status.sh: name temp dir and print the name
- give a template to the temp dir so they're recognizable.
- show the location of the temp files again at the end of the script.

Change-Id: Ieb031ee249043697f6a75e42284c23d0b9bad1b3
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6259
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2014-07-21 17:26:20 +02:00
Martin Roth 224617752b board_status.sh allow cmd() to not save output
- allow for cmd() to be run, but not pipe to a file.

Change-Id: I3e1650e421a49a06218e082ceb5a60b7b4808ce8
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6258
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-07-21 17:25:32 +02:00
Patrick Georgi 913e1718cd build system: fix another cbfstool race
It just doesn't work to have files depend on their parent
directory: As soon as the files are written, the time stamp
of the directory changes, too.

This led to spurious updates of cbfstool and rmodtool, and
related "permission denied" errors when linker and build
system ran into each other.

Change-Id: I44a7d7b4b1d47a1567ece1f57dfd6745d05ee651
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6276
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-15 14:27:04 +02:00
Patrick Georgi 18ff4f166b build system: create .xcompile dependency
It's probably safe to say that .xcompile needs an update if
util/xcompile/xcompile changed, so tell make about this
dependency.

Updates are honored immediately due to GNU make's feature of
reinterpreting everything when an included file changes.  See "How
Makefiles Are Remade" in the GNU make documentation for details.

Change-Id: Ide2f028eaddcee66028c6403688cc83e1622fa6b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6255
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-15 12:26:43 +02:00
Daniele Forsi 3bb0b7230c util/xcompile: Print fatal error messages to stderr instead of stdout
This uses die() which was previously unused.
Before this change an unhelpful error message was printed when make tried
to parse English text as if it was part of the makefile:
.xcompile:1: *** missing separator (did you mean TAB instead of 8 spaces?).  Stop.

After this change the first error message at least mentions that iasl is
missing:
ERROR: no iasl found
make: -print-libgcc-file-name: Command not found
make: -print-libgcc-file-name: Command not found
make: -print-libgcc-file-name: Command not found
/bin/sh: 0: Illegal option -
Makefile.inc:36: *** Please use the coreboot toolchain (or prove that your toolchain works).  Stop.

Change-Id: I79d5de5993e3828460130192df376daa55f32aa0
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6272
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-07-15 11:03:36 +02:00
Martin Roth be5340bad2 board_status.sh add non-fatal test_cmd
- add a non-fatal option to test_cmd.

Change-Id: If74693ea7ec8ea24104d5836e4c24bfb135ef0e1
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6257
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-07-15 03:04:31 +02:00
Edward O'Callaghan 44fd0a0031 utils/cbfstool: No need to pass -g flag twice
Spotted by building with Clang.

Change-Id: I7ab97278d8bd586a71e453c8cc9d26dd6938c8d2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-29 04:16:49 +02:00
Kyösti Mälkki b3594ab489 util/cbmem: Workaround for IS_ENABLED()
Our include files reference CONFIG_xxx declarations, which we should
ignore for utility build.

We cannot include kconfig.h to get IS_ENABLED() as that file
would require build/config.h and we do not want to enforce a build
of the firmware to be able to build the utility.

Since we do not include build/config.h each occurence of CONFIG_xxx
in the included header files is undefined and will be treated as
disabled.

Change-Id: I74f1627fc3f294410db8ce486ab553dac9e967f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6066
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20 19:49:11 +02:00
Damien Zammit 601da481b5 util/inteltool: Add pci ids for 4 northbridge models instead of 1.
This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core.
Tested on 0x0150 (0x0154 previously only model).

Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5873
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-11 03:05:01 +02:00
Paul Menzel 4b10bb7c80 util/board_status/board_status.sh: Move `cbfs.txt` to results directory
Commit 40e936a1 [1]

    util/board_status/board_status.sh: Save ROM contents in `cbfs.txt`

creates `cbfs.txt` in `${tmpdir}` but does not move it to the results
directory `${tmpdir}/${results}`. So move it to the correct place.

[1] http://review.coreboot.org/5867

Change-Id: Ibca691ccf72b56b6271a611d92deaed7d377773b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5883
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-05-31 21:21:01 +02:00
Paul Menzel 40e936a199 util/board_status/board_status.sh: Save ROM contents in `cbfs.txt`
The ROM content (CBFS content) captured with

	cbfstool build/coreboot.rom print

is useful for two reasons.

1. With the used configuration for the build in `.config`, it can be
compared how the size for romstage and ramstage change over time. To
make that reproducible the used toolchain should also be stored
somewhere in the future.

2. With the CBFS content the time stamps can be better interpreted.
For example, the size of the payload file is needed to interpret the
time stamp for loading the payload.

Change-Id: If77ca6412b1710e560f405f9a48df613c1819d36
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5867
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-28 22:42:45 +02:00
Paul Menzel 470c37c372 util/cbfstool: Use `%zu` instead of `%ld` for size_t arguments
cbfstool fails to built under 32-bit platforms since commit

    aa2f739a cbfs: fix issues with word size and endianness.

due to the use of '%ld' format specifier on size_t, which on these
platforms is only 32-bit.

No error is seen though, when cbfstool is built, when building a coreboot
image, where it is put in `build/cbfstool`.

Use the length modifier `z` for size_t arguments, and cast to size_t where
appropriate.

Change-Id: Id84a20fbf237376a31f7e4816bd139463800c977
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5388
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-05-27 15:43:08 +02:00
Patrick Georgi aab0cce888 abuild: make build directory configurable with a variable
Allow overriding the build directly (default: coreboot-builds)
using the COREBOOT_BUILD_DIR variable, in addition to setting
it through the -o parameter.
This helps with build nodes where jenkins wants to run the
same command everywhere but allows different environment
variables.

Change-Id: If907897cf6ac01caa7d1e4b51aad4c005356bc5b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4543
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23 08:35:31 +02:00
Patrick Georgi 2d24279710 abuild: update version and copyright
Enough changed to warrant a new version, date,
and copyright.

Change-Id: Ia099cd4fec3b05efc3f8bac09d38baede1c719e0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5806
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23 08:35:30 +02:00
Patrick Georgi ad27322702 abuild: allow build results outside the source tree
A reasonable configuration that minimizes disk traffic
could be

    $ abuild -o /tmp/abuild-$$ -z

Change-Id: Ic91798af7e799a40a77025e09a6078ea6758cdac
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5805
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23 08:35:29 +02:00
Patrick Georgi b0bc63b519 abuild: allow deleting the work directories immediately
This is useful on pure build nodes that don't care for
object files, just for a build log and success flag.

Change-Id: Ida65d4e41652af0f1b7255309aec2eeb6ef5c9ef
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5804
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23 08:35:28 +02:00
Kyösti Mälkki 49592da27f Board-status: Add second vendor line
Change-Id: I8a962f323cbc6347f266a188a07f870ce174d339
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5751
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19 14:57:39 +02:00
Patrick Georgi 246234fecb abuild: Only build boards with Kconfig
We have dupes in the tree for aliases,
board variants and the like,
for board-status reporting purposes.
But we don't need to build all of them.

Change-Id: Ic1c6415568800350bdc0db97471e3875d9eac98c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5776
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19 14:56:52 +02:00
Patrick Georgi fadbe5f657 build: make scan-build work again
This drops the scan-build related Kconfig options
since it's now possible to simply run

    scan-build [-o outdir] make

and get coreboot built with its report.

There's also no inner make process anymore, and the way
things work should be clearer now.

Also adapt abuild to this new reality.

Change-Id: I03e03334761ec83f718b3235ebf811834cd2e3e3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5774
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:15:14 +02:00
Patrick Georgi 443fbcf6a3 abuild: replace hardcoded values by their variables
Some coreboot-builds/ and makes made their way into
abuild. Stop them.

Change-Id: I5784e1fd623ada30e2fadcc74a7da3ee75c5ee96
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5772
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:15:02 +02:00
Patrick Georgi b145b8301f build: break compiler flags out of $(CC)
Having more than the executable in $(CC) only leads to
trouble in a number of situations.

Change-Id: I7642ca4068b3a3bd5798219d74de9e0eb85bb4e5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5769
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:52 +02:00
Patrick Georgi b83f7deb78 build: get rid of a special case
Don't call things in xcompile i386 and in the
buildsystem x86_32 and then bridge things so
they match. just call it the same everywhere.

Change-Id: Ieef5f03f7aafb0b0a606fbe5a2386e310d2b0e94
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5766
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:35 +02:00
Patrick Georgi 0890a825f3 xcompile: ABIs are really architecture specific
no need to test for i386-eabi or armv7a-elf

Change-Id: Icbef5a64f5b793092ca0f94ee8f54bc896bf39ad
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-05-15 10:27:49 +02:00
Patrick Georgi e0187df61b xcompile: break out big loop content into function
Change-Id: Id98afa956a2af7113a6ef848b436d661a1fa39f2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5745
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15 10:07:29 +02:00
Patrick Georgi adc241326c xcompile: move tempfile cleanup closer together
Change-Id: I4fb3041d505402de3cbcd7ec079dde5e168a90cf
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5744
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15 10:07:22 +02:00
Patrick Georgi ee46712da0 xcompile: actually use "special compile flags" idea
xcompile used to test for special ARM flags - that were
empty.
Meanwhile, -Wa,--divide, which is only useful on i386-elf
was tested for on arm and aarch64, too

Change-Id: I1a5a1bc40fa1040d0939038b073aef31c72d0c6f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5743
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15 10:07:16 +02:00
Patrick Georgi 004295d86d xcompile: fail earlier on missing host tools
No need to test all the cross compiler things if
there's no host compiler or iasl.
Also test that the alternatives work, instead of
assuming iasl or cc are in the path.

Change-Id: I1d2293873f4bf1bb525d794851ec20adddb05ac6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5742
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15 10:07:09 +02:00
Patrick Georgi d387c63576 xcompile: slightly refactor variable expansion magic
Change-Id: Iebe071c863c6c7139128a2ec59acfb9da0f83512
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5741
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15 10:07:01 +02:00
Patrick Georgi aab1740881 xcompile: use bash
I don't think all /bin/sh implement all features used
in xcompile.

Change-Id: Ida2a166242201ed0221316b123888127c83bf3c1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5740
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15 10:06:51 +02:00
Patrick Georgi e9fe6545ca abuild: add -L|--clang to enable clang builds
Change-Id: I11053456fd90cda07143b76de49c2804e38f06e0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5739
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15 10:06:43 +02:00
Aaron Durbin b275757212 cbfstool: account for the trampoline code in bzImage payload
For bzImages the trampoline segment is added unconditionally.
However, that segment wasn't properly being accounted for.
Explicitly add the trampoline segments like the other ones.

Change-Id: I74f6fcc2a65615bb87578a8a3a76cecf858fe856
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5702
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09 08:24:32 +02:00
Patrick Georgi d520840d4c kconfig: update to follow upstream more closely
This might break a bunch of stuff (eg. win32 support),
but otherwise introduces nconfig (ncurses based configuration
frontend), partial configuration headers for improved dependency
tracking (which requires some more build system support) and
various bug fixes.

Change-Id: I5d8a280810c6a26fc3fd056d5d94cb9e591a0ff5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5487
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-05-07 19:39:28 +02:00
Furquan Shaikh fd33781fbf Move ARCH_* from board/Kconfig to cpu or soc Kconfig.
CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.

Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5570
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03 00:25:20 +02:00
Rudolf Marek a8d089d3ac towiki.sh Move vendor link to the first column.
It is not easy to see that there are two links,
one to coreboot wiki and second to the vendor page.
This change moves the vendor page link to the vendor
column, separating it nicely.

Change-Id: I3063be476231d04f833350043010a6e0001697e7
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/5593
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29 21:39:19 +02:00
Andrew Wu b67e9a1acd crossgcc: Support OSX 10.9 built-in tar utility program.
Unlike OSX 10.8, OSX 10.9 doesn't provide GNU tar program, and built-in
tar program is bsdtar 2.8.3. bsdtar can build crossgcc toolchain.
Modify buildgcc to support tar in OSX 10.9 (uname = Darwin).

Change-Id: I093898f8f99e29918387f9b275a30af461a7e1be
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/5598
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29 21:23:10 +02:00
Paul Menzel 47a14b15cb util/board_status/board_status.sh: set its executable flag
Change-Id: I58f6d356bf1625ee205a536ee95c08294891b123
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5171
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-29 17:57:41 +02:00
Furquan Shaikh 20f25dd5c8 Rename coreboot_ram stage to ramstage
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.

Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:27:09 +02:00
Wei Hu 2ad6ee9763 util/cbfstool: Fix "Bad segment type 53534220 Could not load payload".
The magic number mismatch was introduced by commit a8a133
(Add section header parsing and use it in the mk-payload step).

Change-Id: I73b0adb969816e9d130f19f48e175c57124e2f3a
Signed-off-by: Wei Hu <wei@aristanetworks.com>
Reviewed-on: http://review.coreboot.org/5528
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-18 21:18:05 +02:00
Paul Menzel 04eb2e89c6 util/board_status: Only pass switch `-a` once to `git commit`
Change-Id: Iabcb26229401b03ad4ba2df0f78eee08f379aa03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5172
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-16 13:34:01 +02:00
Patrick Georgi aeeafc0860 sconfig: Fix build dependencies
In some cases the build system tried to build main.c before
copying the various "shipped" files (lex/yacc output) where
the place the compiler expects them.

Make the dependency explicit.

Change-Id: Iacef5292aadb9fe7bc967aa4ab5ee6c9fe4df3d7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5510
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-04-16 08:20:24 +02:00
Patrick Georgi 34195beed1 abuild: break early if building tools fails
Change-Id: I8da04df024a31c780b924a586d056a5351845153
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-04-16 08:19:08 +02:00
Patrick Georgi 7bd269e225 abuild: more verbose configuration step
Also pass V=1 to the configuration step, if requested.

Change-Id: If8b413d65d6bac34efab63614d039d74d920c8db
Reviewed-on: http://review.coreboot.org/5492
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-04-16 08:19:05 +02:00
Edward O'Callaghan a0f9ece19c util/cbfstool: Make cbfs_image_delete() NULL-tolerant.
This fixes a double free crash that occurs when a call to
cbfs_image_from_file() fails in cbfs_extract() and falls though to
cbfs_image_delete() with a NULL-pointer.

To reproduce the crash pass the following arguments where the files
passed, in fact, do not exist. As follows:
./cbfstool build/coreboot.rom extract -n config -f /tmp/config.txt

Change-Id: I2213ff175d0703705a0ec10271b30bb26b6f8d0a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5353
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-07 18:34:33 +02:00
Aaron Durbin ab180d85f7 util/cbmem: handle larger than 1MiB mappings for console
In some cases the cbmem console can be larger than the default
mapping size of 1MiB. Therefore, add the ability to do a mapping
that is larger than the default mapping using map_memory_size().
The console printing code will unconditionally map the console based
on the size it finds in the cbmem entry.

Change-Id: I016420576b9523ce81195160ae86ad16952b761c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5440
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 17:01:01 +02:00
Aaron Durbin 4f3bb801ed cbfstool: provide structure to linux payload builder
This change started with tracking down a bug where the trampoline
size was not being taken into account for sizing the output buffer
leading to a heap corruption.  I was having a hard time keeping
track of what num_segments actually tracked as well as what parts
were being placed in the output buffer. Here's my attempt at
hopefully providing more clarity.

This change doesn't crash when adding a bzImage:
$ dd if=/dev/zero of=bb.bin bs=64 count=1
$ ./cbfstool tmp.rom create -s 4M -B bb.bin -m x86 -a 64
$ ./cbfstool tmp.rom add-payload -f ~/Downloads/bzImage -C "1" -n
"fallback"/payload

Change-Id: Ib1de1ddfec3c7102facffc5815c52b340fcdc628
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5408
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-28 14:40:53 +01:00
Wilbert Duijvenvoorde 2164831671 util/superiotool: Add initial support for Fintek F71869ED.
Datasheet: http://www.fintek.com.tw/files/productfiles/F71869_V1.1.pdf
Practically the same as F71869AD, just another ID (0x1408).
Tested on actual hardware, Jetway NC9C-550-LF.

Update:
Fixed F71869ED based on the proper datasheet:
http://www.alldatasheet.com/datasheet-pdf/pdf/459075/FINTEK/F71869ED.html

Change-Id: I5da858565ca16ba4d73b47b42fadd31dabbc290b
Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com>
Reviewed-on: http://review.coreboot.org/5380
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-03-27 10:15:28 +01:00
Wilbert Duijvenvoorde ffdf2e1acf util/superiotool: Register fix for Fintek F71869AD
Fixed F71869AD based on the proper datasheet:
http://www.alldatasheet.com/datasheet-pdf/pdf/459074/FINTEK/F71869AD.html

Change-Id: If22341551c6a1a9bbae088801a6194f7b5b6bf4d
Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com>
Reviewed-on: http://review.coreboot.org/5405
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-24 23:44:52 +01:00
Aaron Durbin 4fde5a66b4 util: add rmodtool for parsing ELF files to rmodules
The current implementation of creating rmodules relies
on invoking the linker in a certain manner with the
relocations overlaid on the BSS section. It's not really
surprising that the linker doesn't always behave the way
one wants depending on the linker used and the architecture.
Instead, introduce rmodtool which takes an ELF file as an
input, parses it, and creates a new ELF file in the format
the rmodule loader expects.

Change-Id: I31ac2d327d450ef841c3a7d9740b787278382bef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5378
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-03-20 21:34:39 +01:00
Aaron Durbin 36be8135d7 cbfstool: add ELF writing support
In order to generate rmodules in the format of ELF files
there needs to be support for writing out ELF files. The
ELF writer is fairly simple. It accpets sections that can
be associated with an optional buffer (file data). For each
section flagged with SHF_ALLOC a PT_LOAD segment is generated.
There isn't smart merging of the sections into a single PT_LOAD
segment.

Change-Id: I4d1a11f2e65be2369fb3f8bff350cbb28e14c89d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5377
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-18 18:59:25 +01:00
Edward O'Callaghan 38608937b6 romcc.c: Fixes warning about unused function from unused macros.
GCC suppresses warnings about unused static functions if they are
inline, however Clang only does this for header files. None of these
MASK_ declarations are used, so just remove them.

Change-Id: Ia230beba3f6367237838d9b3d90536459e1d52cb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5273
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-17 19:09:49 +01:00
Aaron Durbin c078094f39 cbfstool: add symbol table parsing to the ELF parser
Optionally parse the symbol table contained within an ELF
file. It currently assumes there is only one symbol table present,
and it errors out if more than one is found.

Change-Id: I4ac4ad03184a319562576d8ab24fa620e701672a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5376
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14 21:51:38 +01:00
Aaron Durbin c3e6e14a12 cbfstool: add string table parsing to ELF parser
Optionally parse the string tables within an ELF file.

Change-Id: I89f9da50b4fcf1fed7ac44f00c60b495c35555ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5375
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14 21:51:27 +01:00
Aaron Durbin ccb5ad8d3c cbfstool: add relocation parsing to ELF parser
Optionally parse the relocation entries found within an ELF
file.

Change-Id: I343647f104901eb8a6a997ddf44aa5d36c31b44b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5374
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14 21:51:14 +01:00
Aaron Durbin d0f6165923 cbfstool: introduce struct parsed_elf and parse_elf()
In order to make the ELF parsing more flexible introduce
a parse_elf() function which takes a struct parsed_elf
parameter. In addition take a flags parameter which instructs
the ELF parser as to what data within the ELF file should be
parsed.

Change-Id: I3e30e84bf8043c3df96a6ab56cd077eef2632173
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5373
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14 21:50:42 +01:00
Aaron Durbin 19a11d6fe9 cbfstool: remove incorrect section size check
I was overzealous in checking the section size with respect
to the file size. That check makes no sense as the section only
deals with link sizes -- not on-disk sizes. Remove the check as
it doesn't make any sense.

Change-Id: I348e7847ae3a50badc22693439614f813462445a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5384
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 23:02:46 +01:00
Aaron Durbin a31ff73e8d cbfstool: elfparsing: check segment and section regions
While parsing the section and program headers ensure the
locations of their contents are within the elf file proper.

Change-Id: I856f7de45f82ac15977abc06e51bedb51c58dde1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5372
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:31:49 +01:00
Aaron Durbin b1b5118c71 cbfstool: elfheaders: use proper parameters to calloc()
Though the result doesn't matter much, the callers of calloc()
should order the parameters correctly. i.e. the first paramter
is the number of elements in an array and the second is the
size of each element.

Change-Id: Ic7c2910d623d96f380feb4e5f6fa432376f49e9b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5371
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:28:57 +01:00
Aaron Durbin 54ef306377 cbfstool: add eflparsing.h
elfparsing.h serves as the header to working with the elf
parser. Additionally, only include what is needed by the other
files. Many had no reason to be including elf.h aside from fixing
compilation problems when including cbfs.h.

Change-Id: I9eb5f09f3122aa18beeca52d2e4dc2102d70fb9d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5370
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:28:44 +01:00
Aaron Durbin aa8784c2d1 cbfstool: move iself() to eflheaders.c
The only user of iself() was in elfheaders.c. Move it there,
and make it local to the compilation unit.

Change-Id: I0d919ce372f6e2fce75885fb4fcba20d985979b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5369
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:28:07 +01:00
Aaron Durbin a983cea5b9 cbfstool: elfheaders: use common checks and buffer helpers
The elfheaders code was manipulating struct buffers. Use
the introduced buffer helper functions. Additionally fix
up offset and size checks for the program headers and section
headers by using common code paths.

Change-Id: I279c77f77aaa1860a0be43fb111df890dd1d84d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5368
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:27:54 +01:00
Alexandru Gagniuc 0c54bfa0ee Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs"
This reverts commit b845636ce6.
This commit changed the board status script to describe all boards in
terms of x86 terminology, such as CPU->southbridge->northbridge.

This terminology does not apply to a number of SoCs, in which the
buses are not connected via successive bridges, and as such it is
misleading and misguided to describe ideas of southbridge and
northbridge for these devices.

Change-Id: I98ba24ee00b816bf20d507c6d313ec2946acaedf
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5177
Tested-by: build bot (Jenkins)
2014-03-12 16:37:41 +01:00
Aaron Durbin 6e8c2790bb cbfstool: add struct buffer helper routines
There are some open-coded manipulation of the struct buffer
innards in the elf parsing code. Add helper functions to avoid
reaching into the struct itself.

Change-Id: I0d5300afa1a3549f87f588f976184e880d071682
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5367
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:46:45 +01:00
Aaron Durbin 1240d29209 cbfstool: add bputs() to store a byte stream to a buffer
There was already a bgets() function which operates on a buffer to
copy a byte stream. Provide bputs() to store a byte stream to a
buffer, thus making the API symmetrical.

Change-Id: I6166f6b68eacb822da38c9da61a3e44f4c67136d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:43:17 +01:00
Aaron Durbin 01650045f4 cbfstool: add get8/put8 variants to xdr structures
In order to provide consistent usage provide the get8()
and put8() callbacks to xdr operations. That way no futzing
needs to be done to handle 8-bit reads and writes.

Change-Id: I1233d25df67134dc5c3bbd1a84206be77f0da417
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5365
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:42:50 +01:00
Aaron Durbin fae75172d1 cbfstool: move verbose to common.c
In order for multiple tools to use the common code found
in common.c place the verbose variable within common.c's
compilation unit.

Change-Id: I71660a5fd4d186ddee81b0da8b57ce2abddf178a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5364
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:42:30 +01:00
Vladimir Serbinenko 7d48f04bb4 lbtdump: Dump forwarded tables.
Recent coreboot puts real tables in high memory and only pointer
is remaining at traditional location.

This patch makes lbtdump work with recent coreboot.

Change-Id: I1c4945909da16c0ec81e59c2d94d9a7d27e2aba5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4830
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 21:19:29 +01:00
Edward O'Callaghan 2cf9715c9a utils/romcc.c: Fix spurious unsigned integer comparisons.
Clang warns about comparisons of unsigned integers with being below
zero. Remove spurious logic checks that are always false.

Change-Id: I70c4d5331df81e48bf7ef27ff98400c4218f7edc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5275
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-08 15:48:13 +01:00
Alexandru Gagniuc 5edfa3779d cbfstool/lzma: Remove dead code under #ifdefs
Remove a bunch of dead code which depends either on commented out
#defines, or compiler definitions. Use this opportunity to remove the
need for "-D_7ZIP_ST" in the compiler flags.

Change-Id: Ib6629002be7bf4cee6d95d7baa724893b5e8ba32
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5083
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-02 05:14:30 +01:00
Chris Douglass e2718656ec util/ifdtool: cleanup some magic numbers
There are five firmware regions that are (currently) defined. This
was assumed throughout the ifdtool code with many literal 4s and
5s. This patch changes them to refer to a new #define NUM_REGIONS.

Change-Id: I523d3763942f875025ebc4b9ba8b2ccf1db5b2f5
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5313
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-28 21:13:15 +01:00
Chris Douglass 4eabe1e4e1 util/ifdtool: add option to change flash layout
The new option "--newlayout <file>" will read <file> in flashrom's
layout format and copy flash regions from the current flash image
file to a new flash image file.

If a region grows, the padding is added at the beginning of the target
region in the new file so that the data is "right-aligned" to the
end of the region.

If a region shrinks, a warning is given and the tail end of existing
data is copied to the target region in the new file.

Regions of zero or negative size are ignored. (In the example below
00fff000:00000fff regions are an artifact of the address encoding
in the register fields.)

Example Usage:

Given a flash image for a board with a Sandy Bridge processor and
Intel 6-Series chipset in the file vpx7654.bin

ifdtool --layout layout.txt vpx7564.bin
will yield the file layout.txt:
	00000000:00000fff fd
	00180000:003fffff bios
	00001000:0017ffff me
	00fff000:00000fff gbe
	00fff000:00000fff pd

Notice that the "bios" portion extends to the end of the 4MB flash.
It may be edited to extend the bios portion to consume to the extent
of an 8MB flash. like layout2.txt:
	00000000:00000fff fd
	00180000:007fffff bios
	00001000:0017ffff me
	00fff000:00000fff gbe
	00fff000:00000fff pd

ifdtool --newlayout layout.txt vpx7654.bin
will create a file vpx7654.bin.new that is 8MB.

Change-Id: I0e0925a725c40fa44d8c4b6e86552028779d0523
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5312
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-28 21:12:29 +01:00
Chris Douglass 03ce014cfc util/ifdtool: add option to dump flashrom layout
Dump the Intel Flash Descriptor map in the format expected
by flashrom's "layout" option.

Example usage:

Given a 4MB flash image vpx7654.bin that was generated by Intel's
FITC tool for a 6-Series chipset...

./ifdtool --layout l.txt vpx7654.bin
cat l.txt
	00000000:00000fff fd
	00180000:003fffff bios
	00001000:0017ffff me
	00fff000:00000fff gbe
	00fff000:00000fff pd

Change-Id: Ib740178ed6935b5f6e1dba1be674303f9f980429
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5306
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-28 21:10:46 +01:00
Vladimir Serbinenko 970dd9c466 boardstatus/towiki: Skip OVERRIDE_FANCTL
Change-Id: I4c5f69db198c8aa4757c82856fb04aa5ee16879f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5123
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-28 00:32:49 +01:00
Vladimir Serbinenko 50d9752e7f boardstatus/towiki: Skip comments after options.
Change-Id: Id1213f4a44cd3a7a698b761d4942707d7dc1dee6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5122
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-28 00:32:40 +01:00
Vladimir Serbinenko 7035b85f52 boardstatus/to-wiki.sh: Accept Kconfig with non-tab separators.
Change-Id: I3812c6bd6fb11d9e98ef60afb205782f2b1f0e44
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5069
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-28 00:32:31 +01:00
Alexandru Gagniuc 87cc49bc5b crossgcc: Update IASL to latest version (20140114)
Change-Id: I2450cad4a43907b8ca6d8f4d35932d7f451f71ea
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5116
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-02-14 02:52:45 +01:00
Edward O'Callaghan 3a7227852b utils/crossgcc: Refactor Makefiles for separate arm/i386.
Refactor Makefile build system as decompartmentalise armv7a and i386
targets from crossgcc.

Change-Id: If93f62050810ba594c9925a9eb8ba9d04bc76459
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4008
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-12 21:25:25 +01:00
Alexandru Gagniuc 7c9bb41817 cbfstool/lzma: Remove code which depends on commented out defines
These options seem to control the behavior of the encoder/decoder,
with comments citing a trade-off between memory usage and performance.
I removed these in a separate patch to make reverting in the future
easier, if we find these options are useful.

Change-Id: I24cb7101b89e60f4fb96777e3681c03d2a62e3d5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5084
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-11 20:15:48 +01:00
Alexandru Gagniuc c1d1fd850e cbfstool: Deserialize CBFS master header when reading image
Rather than  using [hn]to[nh] whenever accessing a member of the CBFS
header, deserialize the header when opening the CBFS image. The header
is no longer a pointer inside the CBFS buffer, but a separate struct,
a copy of the original header in a host-friendly format. This kills
more of the ntohl usage.

Change-Id: I5f8a5818b9d5a2d1152b1906249c4a5847d02bac
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5121
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-11 20:14:39 +01:00
Alexandru Gagniuc ed87ebc325 cbfstool/lzma: Remove LITTLE_ENDIAN_AND_UNALIGNED_ACCESS_OK
This was designed as a micro-optimization for x86, but it is only used
once. Let the compiler decide if optimizing this is worth the effort.

Change-Id: I5939efa34f0e9d16643893ca04675247842e7db5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5085
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-10 05:45:54 +01:00
Alexandru Gagniuc b63b75b0f7 cbfstool: Fix LzmaEnc.c and build with -Wshadow
LzmaEnc.c was full of shadow definitions. Luckily, shadow definitions
were not used after the scope in which they were redefined, so it is
possible to just remove them.

Tested by successfully booting qemu i440fx to grub2 payload.

Change-Id: I01d44db59882114ffe64434b655b931f3beec8e2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5082
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-10 05:44:12 +01:00
Alexandru Gagniuc ae45a9884b cbfstool: Fix build errors when building with clang
Now that we can set CC to an arbitrary compiler, fix issues that clang
finds. Luckily, there were only two trivial errors.

Change-Id: I0fd1f0f263a8ab7004f39cd36ed42d1a1cba5c04
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5081
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-10 05:43:56 +01:00
Vladimir Serbinenko 892728c65f boardstatus/towiki: Fix 1st gen i3/i5/i7 codename
It was a typo.

Change-Id: I82964b5ed7e7749ba141aeb3ee8dc4c107bcd7a9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5127
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 21:18:01 +01:00
Vladimir Serbinenko b845636ce6 boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs
Change-Id: I3a38ca834606bb53e6f82cbe79c3a99288429aee
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5124
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07 21:16:59 +01:00
Ronald G. Minnich 3fcde22a30 Add an xdr function for the cbfs_file header
And use it in fit.c and remove one more use of htonl.

Change-Id: Ibf18dcc0a7f08d75c2374115de0db7a4bf64ec1e
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/5120
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-05 06:50:41 +01:00
Ronald G. Minnich 818f369da2 Change the linux payload generator to use the standard header generator
When I changed mkpayload, I did not realize we had a duplicate
block of code in the linux payload code. Have it use the same
header generator as the standard payload code does.

Change-Id: Ie39540089ce89b704290c89127da4c7b051ecb0e
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/5115
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-05 01:00:34 +01:00
Alexandru Gagniuc 35850ae88e cbfstool: Eliminate global variable "arch"
Now that unused functions have been removed, the global "arch" is only
used in very few places. We can pack "arch" in the "param" structure
and pass it down to where it is actually used.

Change-Id: I255d1e2bc6b5ead91b6b4e94a0202523c4ab53dc
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5105
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-04 19:37:48 +01:00
Alexandru Gagniuc 2bdc0d0bd6 cbfstool: Remove more unused functions from common.c
A lot of the early functions have been re-implemented in a context-
centric mode, rather than relying on global variables. Removing these
has the nice side-effect of allowing us to remove more global
variables.

Change-Id: Iee716ef38729705432dd10d12758c886d38701a8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5104
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-04 19:37:41 +01:00
Alexandru Gagniuc c677c7d6e4 cbfstool: Hide cbfstool_offset from the global namespace
This is part of a larger effort to reduce global variable usage in
cbfstool. cbfstool_offset is particularly easy to hide since it's only
used in common.c .

Change-Id: Ic45349b5148d4407f31e12682ea0ad4b68136711
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5102
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-04 19:37:26 +01:00
Alexandru Gagniuc bc06691a3b cbfstool: remove unused function create_cbfs_image()
It's not used anymore. Instead, we have the better replacements
cbfs_image_create() and cbfs_image_from_file().

Change-Id: I7835f339805f6b41527fe3550028b29f79e35d13
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5103
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-03 17:02:38 +01:00
Ronald G. Minnich b5adeee1cc cbfstool: add code to serialize the header using the new xdr functions
This change adds a header serialization function. Programmers can thus just
set up a header as needed, without worrying about forgetting if and how to
use the [hn]to[hn]* functions.

In the long term, we will work to remove swab.h, i.e. we need to get to the
point where programmers don't have to try to remember [hn]to[nh]* and where
it goes. To date, even the best programmers we have have made an error with
those functions, and those errors have persisted for 6 or 7 years now. It's
very easy to make that mistake.

BUG=None
TEST=Build a peppy image and verify that it's bit for bit the same. All
     chromebooks use this code and build and boot correctly.
BRANCH=None

Change-Id: I0f9b8e7cac5f52d0ea330ba948650fa0803aa0d5
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/181552
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/5100
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-02 23:48:18 +01:00
Ronald G. Minnich a8a133ded3 Add section header parsing and use it in the mk-payload step
This completes the improvements to the ELF file parsing code.  We can
now parse section headers too, across all 4 combinations of word size
and endianness. I had hoped to completely remove the use of htonl
until I found it in cbfs_image.c. That's a battle for another day.

There's now a handy macro to create magic numbers in host byte order.
I'm using it for all the PAYLOAD_SEGMENT_* constants and maybe
we can use it for the others too, but this is sensitive code and
I'd rather change one thing at a time.

To maximize the ease of use for users, elf parsing is accomplished with
just one function:

int
elf_headers(const struct buffer *pinput,
	    Elf64_Ehdr *ehdr,
	    Elf64_Phdr **pphdr,
	    Elf64_Shdr **pshdr)

which requires the ehdr and pphdr pointers to be non-NULL, but allows
the pshdr to be NULL. If pshdr is NULL, the code will not try to read
in section headers.

To satisfy our powerful scripts, I had to remove the ^M from an unrelated
microcode file.

BUG=None
TEST=Build a peppy image (known to boot) with old and new versions and verify they are bit-for-bit the same. This was also fully tested across all chromebooks for building and booting and running chromeos.
BRANCH=None

Change-Id: I54dad887d922428b6175fdb6a9cdfadd8a6bb889
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/181272
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/5098
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-02 20:18:55 +01:00
Lubomir Rintel ba1f9aaa9e utils: Install man pages as non-executable (chmod 644)
This bothers rpmlint.

Change-Id: I27d9cfac3ef6834ff87acc5a5ccbf332e59eeb1a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: http://review.coreboot.org/5075
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-31 20:14:58 +01:00
Alexandru Gagniuc 9ad52fe56e cbfstool/lzma: Avoid use of typedef with structs and enums
When typedef is used with structs, enums, and to create new typenames,
readability suffers. As such, restrict use of typedefs only to
creating new data types.

The 80 character limit is intentionally ignored in this patch in order
to make reviewing easier.

Change-Id: I62660b19bccf234128930a047c754bce3ebb6cf8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5070
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-29 20:06:26 +01:00
Alexandru Gagniuc 4a7b115211 cbfstool: Don't assume compiler is gcc, and use $(CC)
Change-Id: I49feb5be885369fca10c8db31329e51d87031641
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4841
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-29 20:05:58 +01:00
Alexandru Gagniuc e20f27a098 cbfstool/lzma: Remove windows-specific remnants
Remove checks for MSVC version and references to windows types and
calling conventions. Calling conventions are not needed as functions
are not exported, like in a library.

Change-Id: I884a1502cf56b193de254f017a97275c8612c670
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4836
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-29 20:05:42 +01:00
Alexandru Gagniuc 5719bdc81c cbfstool/lzma: Remove C++ remnants
The original lzma code was probably designed as a library, and had
tons of checks for __cplusplus and extern "C". They were not removed
when imported, but remove them now.

Change-Id: I4ae6e7739d191093c57130de8ae40da835e81bd1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4835
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-29 20:05:09 +01:00
Alexandru Gagniuc 91e9f27973 cbfstool/lzma: Use stdint and stdbool types
This is the first patch on a long road to refactor and fix the lzma
code in cbfstool. I want to submit it in small atomic patches, so that
any potential errors are easy to spot before it's too late.

Change-Id: Ib557f8c83f49f18488639f38bf98d3ce849e61af
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4834
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-29 20:04:53 +01:00
Ronald G. Minnich aa2f739ae8 cbfs: fix issues with word size and endianness.
Add XDR functions and use them to convert the ELF headers
to native headers, using the Elf64 structs to ensure we accomodate
all word sizes. Also, use these XDR functions for output.

This may seem overly complex but it turned out to be much the easiest
way to do this. Note that the basic elf parsing function
in cbfs-mkstage.c now works over all ELF files, for all architectures,
endian, and word size combinations. At the same time, the basic elf
parsing in cbfs-mkstage.c is a loop that has no architecture-specific
conditionals.

Add -g to the LDFLAGS while we're here. It's on the CFLAGS so there is
no harm done.

This code has been tested on all chromebooks that use coreboot to date.

I added most of the extra checks from ChromeOS and they triggered a
lot of warnings, hence the other changes. I had to take -Wshadow back
out due to the many errors it triggers in LZMA.

BUG=None
TEST=Build and boot for Peppy; works fine. Build and boot for nyan,
     works fine. Build for qemu targets and armv8 targets.
BRANCH=None

Change-Id: I5a4cee9854799189115ac701e22efc406a8d902f
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178606
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4817
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-29 20:03:44 +01:00
Edward O'Callaghan 5b5f834e84 util/superiotool: Add initial support for Fintek F71869AD.
Change-Id: Ia2ce8214d8b419d0ca0186e6f6b2241097b0847b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4802
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-27 01:21:22 +01:00
Aaron Durbin 1ebc7e943b cbfstool: correct size left calculation for "empty" entries
After removing a file sandwiched between two other files, that file
could no longer be re-added at the same location. cbfstool tried to
add the file, and a new "empty" entry, which, together, would no
longer fit, so it continued checking for the next available space.

Change the behavior to add the file if there is enough space for the
file alone, then only add the "empty" entry if there is enough space
for it.

Change-Id: Iad3897dd28cf12f12ae877cfd83e1990fa7d2f0f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4772
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-24 04:48:05 +01:00
Patrick Georgi 2a1d5b061d cbfstool: cleaner filling fields
The LARCHIVE header isn't a string (not null terminated).
It confused coverity, and while it should be obvious that
we're not aiming for any null bytes after the header, we
can also just not pretend it's a string.

Change-Id: Ibd5333a27d8920b8a97de554f1cd27e28f4f7d0a
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4088
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-21 19:07:17 +01:00
Vladimir Serbinenko 77005b4768 board_status.sh: Replace [[ with [.
[[ is a bashism.

Change-Id: Ief7c43fc1740db32ed97850a415b0c256b5bb35a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4764
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-21 03:17:13 +01:00
Patrick Georgi 7358643e0a sconfig: don't "const" structs twice
It's useless and makes clang unhappy.

Change-Id: If256b99aebabd87df30a3a078c5804330b82989b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4713
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-20 12:59:27 +01:00
Vladimir Serbinenko df7d5c9e06 boardstatus: Fix creation of links to configs.
The unusual construction ls + grep + while read fails
for unknown reason. Use standard for x in * consruction
instead.

Change-Id: Ibcdf5e18543587f71a605bae2d0df72b6a286a5b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4757
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-20 03:50:03 +01:00
Vladimir Serbinenko 3e51837f9a boardstatus: Add useful info from old page header to foreword.
Change-Id: Ie3d1be1e51df458cd8b55230c888f032ab705ef8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4743
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 19:14:04 +01:00
Vladimir Serbinenko 08c372f460 boardstatus: Do not error out on unknown CPU/northbridge
On bot, stderr is unmonitored, so it make no sense to stop with an error.
Instead use some sensible guesses.

Change-Id: I6292e9fbf446b751471b95f86e7515c6680bddf3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4748
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 19:09:50 +01:00
Vladimir Serbinenko 2a0fc9fbb4 boardstatus: Drop v4 mention of coreboot version.
Change-Id: I5cf34e14f6e11c03822a6ce6226365c76e0f6875
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4742
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 12:42:39 +01:00
Vladimir Serbinenko 5fb48a85dc boardstatus: Accept only hex digits for AMD family number.
Change-Id: Ia13e54f35215d07d93f93887eef5aeb91ffb874d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4741
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 04:04:50 +01:00
Vladimir Serbinenko aa998bb480 boardstatus: Skip SKI_ISA_DMA_INIT configs.
Change-Id: I10872c31baa0d73ce55d1738a0643fda2555c62e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4740
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 04:04:41 +01:00
Vladimir Serbinenko 047c10c0f8 boardstatus: Add new category "sbc".
Change-Id: I8a7bf265ebb30dd5997f93729a0329e74f463a23
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4739
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 03:20:08 +01:00
Vladimir Serbinenko 14a703045d boardstatus: Add category "emulation".
Change-Id: If9d26b9e4cb1895452316c9cf2e8c75a01cfd7c2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4738
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 03:17:18 +01:00
Vladimir Serbinenko 2eaf3b4e3a boardstatus: Handle clones.
Change-Id: I7bfe19eb800729713a549dc0396765a9785e11b1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4732
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 02:18:33 +01:00
Vladimir Serbinenko 03cd8e5fa4 boardstatus: Use Board:$vendor/$board for board pages.
Change-Id: I5249d86188845e1104d25163faa5010b943e707a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4731
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 02:06:17 +01:00
Vladimir Serbinenko 21a2707ea9 boardstatus: Remove support for multiname mobos.
It's ugly and not needed anymore.

Change-Id: I98301c75684813a217c3ca0435a15b6e4ffef558
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4730
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 00:37:58 +01:00
Vladimir Serbinenko 49fef4b6cb boardstatus: Take default board name from MAINBOARD_PART_NUMBER.
Change-Id: I2f775e8919cfd35bbcf5910a8b25776e833ee100
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4722
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-18 22:30:33 +01:00
Vladimir Serbinenko 22210dd95b boardstatus: generate table of all boards with links to latest run
Change-Id: I78f94238d7931c8b41e63174220ec4392108f4ce
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4699
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-18 21:32:36 +01:00
Alexandru Gagniuc 910ce01757 cpu/allwinner/a10: Provide utility to make a bootable image
Up until now, we relied on mksunxiboot to prepend the header which
makes coreboot.rom bootable on Allwinner SoCs. If that tool was not
present, the build silently failed.

Integrate this tool into our util/ package, so that we do not have to
rely on mksunxiboot being in PATH.
Our version of mksunxiboot also eliminates some limitations of the
original tool, so we no longer have to use 'dd' to limit the file
size.

Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4656
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:03:00 +01:00
Paul Menzel 8ebc72cdda util/cbmem/Makfile: Add rule `junit.xml` for Jenkins
The rule has the target `junit.xml` and runs `make clean` and `make` and
logs the result in the file `junit.xml` suitable for consumption by
Jenkins.

Change-Id: I42a31f6c7a45fa9c3773969d78f745fcc4e09dbd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4611
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-11 17:40:38 +01:00
Patrick Georgi 08fec46058 lint: check label style only on changed files
This should probably propagate to the other lint checks.
The idea: only enforce style on files that were at least touched
by the developer.

Change-Id: I5ac690ee726e27e80e790fa9a41cd14b84ad2161
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4644
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-11 10:56:54 +01:00
Patrick Georgi 47777569d2 board-status: fix weekly format
The last few days of the year might belong to the first
week of the new year in the ISO week numbering scheme.

GNU date accounts for that with different-than-usual
notation.

Change-Id: I8047c197971077a845d6c1fdc9da6eb9f3741539
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4610
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-04 00:05:08 +01:00
Patrick Georgi 44af57a78b buildgcc: defer cleaning up the tree a bit
cleanup() uses BUILDDIRPREFIX, which is set after the
getopt loop.

Change-Id: I8a904781ee4fefc42681d31e94b64008cf03750a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4544
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-12-22 04:53:12 +01:00
Yunlian Jiang 063c7c5bf6 nvramtool: add -MG to makefile to make it pass clang
Change-Id: I7878d2639946c6c2222022a72ba54e4df0fce976
Reviewed-on: https://gerrit.chromium.org/gerrit/65335
Tested-by: Yunlian Jiang <yunlian@chromium.org>
Reviewed-by: Yunlian Jiang <yunlian@chromium.org>
Commit-Queue: Yunlian Jiang <yunlian@chromium.org>
Reviewed-on: http://review.coreboot.org/4465
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:19:02 +01:00
Patrick Georgi d03d69bf18 abuild: improve --remove
Make abuild -r work in more sitations (eg. xargs parallelization),
and make it not break junit output.

Also tell Kconfig to just overwrite the config file, instead of
atomically updating it, which help if coreboot-builds is on a
different filesystem (eg. tmpfs).

Change-Id: I2f4eedfd34ea6771732a60b38f1856056089be23
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4542
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-20 21:01:32 +01:00
Zheng Bao f95bb2d7bb crossgcc: Fix a typo.
Change-Id: I8b88957a93e6369c59e9eb17f4ba48954fbc3c02
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/4526
Tested-by: build bot (Jenkins)
2013-12-13 06:09:21 +01:00
Patrick Georgi 041dae1914 board-status: extend wiki foreword
Change-Id: I9791beff44535a0a130292414fcd9875b497b1ca
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4492
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 19:03:22 +01:00
Alexandru Gagniuc f87c20a00d cbfstool: Properly handle EOF in update_fit step
During the update_fit step, 'file_length' is used to determine how many
bytes are left in the CBFS file. It was decremented in a loop from an
array 'mcus[num_mcus].size', but 'num_mcus' was incremented right before.
Since 'mcus' is memset(0) externally, 'file_length' was never decremented.

The loop exited when it reached a dummy terminator, usually 48 bytes of 0
which are internationally added to microcode blobs in coreboot. However,
if that terminator is removed, the loop doesn't stop and continues until
it segfaults.

Change-Id: I840727add69379ffef75b694d90402ed89769e3b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4508
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-09 17:34:25 +01:00
Zheng Bao 691b313c28 crossgcc: Continue to unpack archive if it was incomplete
If the unpacking was interrupt by Ctrl-C, probably part of
an archive is unpacked. If we run buildgcc again, the
incomplete folder would be and skipped.

We can create a file to tell the script the unpacking is done.

Change-Id: Id9eb74d119e22b62c70dca9b38a92c3dbdf0f64c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/4512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-09 11:14:24 +01:00
Patrick Georgi 4eb4a1f6be board-status: update foreword
Change-Id: I6acafee948b1224b88fd640e02c18168c1f90e39
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4496
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-07 20:54:35 +01:00
Patrick Georgi 87932c027e board-status: one-line reports, with links to per-board pages
Make boards take less vertical space, and link to board pages

Change-Id: Ifdd062a15191809b75422416c874161d9114363d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4493
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07 20:03:52 +01:00
Patrick Georgi 7f68dfd6e8 board-status: document the wiki scripts
These were terribly under-documented

Change-Id: I285ea083110d87076281e81065f5f38d0c688358
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4491
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07 18:09:41 +01:00
Patrick Georgi 6f0e160459 abuild: drop xml mode
We use junit style output these days.

Change-Id: I4110ec10bf0e9f4354ee08e7e1c5a81ae605fee0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4484
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-07 03:33:38 +01:00
Patrick Georgi 589555109c abuild: fix and enable USE_XARGS configuration
USE_XARGS mode builds n boards in parallel (with 1 CPU each) instead of
building 1 board with n CPUs.
This requires the main build system to work under such circumstances.

Change-Id: Ib4571a78dfe78fd61ae5b26c18be9745bd8b3d52
Reviewed-on: http://review.coreboot.org/4485
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-05 20:46:00 +01:00
Patrick Georgi d935f03938 sconfig: avoid regenerating the binary all the time
This makes USE_XARGS-abuild unhappy due to races

Change-Id: I1237468366c7f8af7eacd572c2bd32df9a3d58ca
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4486
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-12-05 20:45:57 +01:00
Stefan Reinauer 0db924d74c cbmem: print timestamp names
The numbers alone are hard to parse, so add
some timestamp names to make it easier to read.

Change-Id: Ie32d3e7ca759bd15e7c160bdd829dec19943e6cb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65333
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4314
Tested-by: build bot (Jenkins)
2013-12-05 19:23:49 +01:00
Stefan Reinauer d8ef9e9e9b Fix timestamp output in cbmem utility on ARM
On ARM the timestamps are already in micro seconds, so
no need to convert them.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: If7363b0703e144bde62d9dab4ba845e1ace5bd18
Reviewed-on: https://gerrit.chromium.org/gerrit/63991
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4313
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05 19:23:40 +01:00
Patrick Georgi 274c6c2177 Add scripts to export board status data to wiki
It's a start...

Change-Id: Ibdb0b64ab0349df58bcad5ce553bf0dbec636925
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4483
Tested-by: build bot (Jenkins)
2013-12-05 18:40:25 +01:00
Stefan Reinauer a9c8361c02 cbmem: fix userspace utility to work with dynamic CBMEM
This also adds an option -x/--hexdump to dump the whole
CBMEM area for debugging.

Change-Id: I244955394c6a2199acf7af78ae4b8b0a6f3bfe33
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62287
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4312
Tested-by: build bot (Jenkins)
2013-12-04 22:21:13 +01:00
Stefan Reinauer 7f68150f1e cbmem: Implement ARM support
on ARM the CBMEM utility requires the procfs entry
/proc/device-tree/firmware/coreboot/coreboot-table
provided by the FDT (dynamically created by depthcharge
at the moment)

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: If5f961afb23791af6f32dd4fc9a837a1aa41b70e
Reviewed-on: https://gerrit.chromium.org/gerrit/59322
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4311
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-04 22:21:03 +01:00
Aaron Durbin 8a0cb8de65 cbfstool: check potential microcode update earlier
The update-fit command takes in a parameter for number of slots
in the FIT table. It then processes the microcobe blob in cbfs
adding those entries to the FIT table. However, the tracking of
the number of mircocode updates was incremented before validating
the update. Therefore, move the sanity checking before an increment
of the number of updates.

Change-Id: Ie8290f53316b251e500b88829fdcf9b5735c1b0e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50319
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4161
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:24:57 +01:00
Stefan Reinauer 8c5947709a cbmem utility: compatibility with older coreboot versions
Commit b8ad224 changed the memory address in lb_cbmem_ref coreboot
table entries from a pointer to a uint64_t. This change was introduced
to make the cbmem utility work on both 32bit and 64bit userland.
Unfortunately, this broke the cbmem utility running on older versions
of coreboot because they were still providing a 32bit only field for
the address while the cbmem utility would now take the following 4
bytes as upper 32bits of a pointer that can obviously not be
mmapped. This change checks if the size of the lb_cbmem_ref structure
provided by coreboot is smaller than expected, and if so, ignore the
upper 32bit of the address read.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: If4c8e9b72b2a38c961c11d7071b728e61e5f1d18
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4139
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:02:07 +01:00
Patrick Georgi c37b05c413 nvramtool: write size field more obviously
The field wasn't initialized in RAM first and later overwritten in a somewhat
twisted way (that relied on the size field coming after the tag field in the
struct).

Change-Id: Ibe931b297df51e3c46ae163e059338781f5a27e2
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4087
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-11-19 00:59:55 +01:00
Ronald G. Minnich 72f15bd2be cbfstool: add a constant for the aarch64
Change-Id: Ide2c8b778447de66d95bd8c55b378aa2051ac2a0
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/4091
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-11-18 16:58:58 +01:00
David Hendricks a4affe17f1 board_status.sh: trivial cosmetic changes toward the end
This moves an ugly comment closer to where it is applicable and also
adds a visual break between the commands which gather data and the
part of the script that finishes up. I'm usually not fan of banner
comments, but it seemed to help in my totally subjective opinion.

I was thinking about how to break the part that uploads results into
a separate function, but there are enough variables that are re-used
from earlier parts that the tradeoff probably isn't worth it.

Change-Id: If888329911c4de3b907cdf5973695c707bbb02fe
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4051
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:32:22 +01:00
David Hendricks 406ce8a06e board_status.sh: pass filename as an arg to command wrappers
This allows the command wrappers to delete files if the command
fails. In particular, it delets empty or otherwise useless files
that are generated if a non-fatal command fails.

Change-Id: If26d7b4d7500f160edd1cc2a8b6218792fefae8b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4050
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:32:14 +01:00
David Hendricks f8b90e4622 board_status.sh: add support for non-fatal commands
This adds cmd_nonfatal() for commands which are considered
non-essential and can be expected to fail safely. This can be used,
for example, to gather data that is generated when using non-standard
utilities or coreboot config options.

Change-Id: Ie43944d2eb73f9aae1c30c3a204cfc413e11d286
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4049
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:32:07 +01:00
David Hendricks 1fc65f76f4 board_status.sh: move show_help()
This is really only a cosmetic change, but is intended to make it
slightly easier to remember to update the help menu whenever
options change.

Change-Id: I58b5012309229d08da138a01c7cd1c5096423179
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4048
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:31:37 +01:00
David Hendricks 16955fd665 board_status.sh: Make clobber option use 'C' instead of 'c'
Clobbering output is only really useful when debugging the script.
Since we're only using short options, let's save 'c' for something
more important.

Change-Id: If87a70fdc0cd006818d1736c40f9984dfec663a9
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4047
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:31:30 +01:00
David Hendricks 1b6e7a6748 Updates to the board status script
This is the first major re-work for the board status script.
Summary:
- Added a command to the getrevision.sh script to retrieve tagged
  revision.

- Results are placed in a dynamically generated temporary location.
  This makes it easy to do multiple trial runs and avoids polluting
  the coreboot directory.

- Results are stored in a directory with the following form:
  <vendor>/<mainboard>/<tagged_revision>/<timestamp>/
  Vendor and mainboard are obtained from CONFIG_MAINBOARD_DIR so that
  hierarchy is consistent between coreboot and board-status.

- The results directory is used as the commit message.

- board-status repository is checked out automatically if results are
  to be uploaded.

TODO:
- Add ability to run commands which may fail. Currently we assume
  any failure should terminate the script, but some commands can be
  made optional.

Successfully uploaded first result to board-status repository. See
http://review.coreboot.org/gitweb?p=board-status.git;a=summary .

Change-Id: Icba41ccad4e6e6ee829b8092a2459c2d72a3365b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4039
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:31:17 +01:00
Patrick Georgi 0dde01cad1 romcc: Fix off-by-one
Arrays are indexed 0..(number_of_element-1).

Change-Id: I2157e74340568636d588113d1d2d8cae50082da2
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4089
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-11-16 09:49:35 +01:00
David Hendricks c5e947ef17 rename status-related stuff to board_status
This just moves stuff to be more clear about the purpose of
the script. Other suggestions are welcome.

Change-Id: Ic6095fd4eb347daa5a03eff21b5952d2d42a6bfd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4038
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-12 20:14:23 +01:00
Ronald G. Minnich 12785d9601 util/xcompile/xcompile: set up for aarch64
The tools for aarch64 on ubuntu are called
aarch64-linux-gnu-*
The type is
elf64-littleaarch64

This now finds the right files for building on aarch64

This has only been tested on ubuntu saucy; the aarch64 toolchain
is in a very ill-defined state on most distros.

Change-Id: Ic1bbd40f0d72384d6e80287b850686292a252918
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/4035
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-11-10 04:41:30 +01:00
Zheng Bao 86655cf835 Trivial: Remove trailing whitespaces in status.sh
The whitespaces make "git commit" failed.

lint-stable-003-whitespace
Check for superfluous whitespace in the tree
========
test failed:
File util/status/status.sh has lines ending with whitespace.
========

Change-Id: I52fc5ae3e5aa81dac098b36d2479e4d10325a09b
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/4032
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-07 11:59:24 +01:00
David Hendricks 6583a8108c Another pass at board status script
This reports relevant bits of information about a machine which is
running coreboot. This also includes a script to get revision info
from git, which we may want to split out into another patch.

A remote target can be specified since it is likely that the machine
used to develop the code is not the same machine being developed for.
The remote host must be set up for non-interactive root login.

Example: sh util/status/status.sh -r gizmoboard -u

Change-Id: Ief0a85faca2ec9ce2d270e1e5b09e74836ab0c97
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4021
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-04 17:11:35 +01:00
Paul Menzel 569ad760cc util/lint/lint-stable-003-whitespace: Ignore temporary files ending with a tilde
Some editors like gedit create auxiliary files ending with a
tilde '~'. As these are not checked into the Git repository, do
not check these for whitespace errors.

Change-Id: I2c4cf00f9d623be73ea3bbb7b2da4f1e1900c8e9
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3952
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-22 04:17:30 +02:00
Andrew Wu cd9abf95e7 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify
the xcompile script to search for cpp program path, and pass it to
SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler).

This is needed, so the crossgcc toolchain to build the SeaBIOS payload
under Mac OSX. OSX ships a cpp program, but it works differently
from GNU CPP, so we need to override it.

Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3896
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-17 01:59:50 +02:00
Nico Huber 1bfe37470e lint: Use temporary build directory
`util/lint/lint-stable-002-build-dir-handling` always overwrites your
current `config.h` and `auto.conf` when the pre-commit hook is run. It
can be very confusing when your configuration is suddenly broken. So fix
it by not using the default build directory.

Change-Id: If2bbc97ac2f12a8203a3769d813386a023f93dd6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3593
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-27 11:51:29 +02:00
Patrick Georgi c8883262cf buildgcc: Downgrade to gcc 4.7.3, handle armv7-a
gcc 4.8.x has issues with using ebp, which broke some builds,
so downgrade. The problem also manifested elsewhere, so it's
not necessarily our fault.

While at it, gcc complained about "armv7a" where it seems to
expect "armv7-a".

Change-Id: I6f0c35f49709cb41022475bb47116c12ab1c7ee3
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3930
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-20 20:42:14 +02:00
Patrick Georgi 3af0aa2533 buildgcc: Use per-arch build directories
This simplifies debugging and also fixes an issue when build directories
are kept between buildgcc runs for different architectures.

Change-Id: I5badccd3368e3014680da3eedb607119fff8fa7f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3929
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-18 09:38:30 +02:00
Kyösti Mälkki ecd8424919 Fix whitespace leaked into tree
Clean whitespace errors that have gotten past lint-stable-003-whitespace
and gerrit review.

Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3920
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-17 21:04:35 +02:00
Kyösti Mälkki 370ff4af11 lint whitespace: Fix rule to recurse into subdirectories
The rule "-perm +111 -prune" matched any searchable directory
and did not recursively find files in them. The use of "+mode"
for -perm is deprecated.

Change-Id: I1b43f89ee9ab37928e56104b0f07241ff84b84c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3921
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-17 21:03:28 +02:00
Patrick Georgi 2f39eae41d Remove NRV2B compression support
It wasn't even hooked up to the build system anymore.

Change-Id: I4b962ffd945b39451e19da3ec2f7b8e0eecf2e53
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3892
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-31 08:58:37 +02:00
Patrick Georgi de36d333c2 Add a (b)zImage parser to cbfstool
In the great tradition of LinuxBIOS this allows adding
a kernel as payload. add-payload is extended to also
allow adding an initial ramdisk (-I filename) and a
command line (-C console=ttyS0).

Change-Id: Iaca499a98b0adf0134e78d6bf020b6531a626aaa
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3302
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-31 08:58:34 +02:00
Zheng Bao 3c4bd91a34 Locate the generated iasl in acpica-unix-20130626
acpica-unix-20130626 doesn't use bin32 and bin64 to save the objects
any more.

Change-Id: I419ecc987e2adcd860a8ad1bf2f6b5c4dd40fd8a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/3885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-27 19:55:55 +02:00
Paul Menzel 4159a8012e Correct spelling of shadow, setting and memory
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3768
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16 22:25:56 +02:00
Peter Stuge 3bfd5b8252 cbfstool: Add an add-int command that adds a raw 64-bit integer CBFS file
This simplifies storing SeaBIOS parameters in CBFS.

Change-Id: I301644ba0d7a9cb5917c37a3b4ceddfa59e34e77
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3733
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15 20:46:09 +02:00
Damien Zammit dcea700762 inteltool: Print raw CPUID and make hexadecimal values unambiguous
The raw CPUID is useful for matching the directories under 'src/cpu/intel'
and is not easy to find out otherwise because it is most often decoded
already. The decoded values are not obviously hexadecimal so prepend
them with 0x to make sure they are unambiguous.

The output differences look like this:
-	CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
+	CPU: ID 0x20652, Processor Type 0x0, Family 0x6, Model 0x25, Stepping 0x2

Change-Id: Id47f0b00f8db931f0000451c8f63ac1e966442c4
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3788
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Tested-by: build bot (Jenkins)
2013-07-23 12:06:24 +02:00
Stefan Reinauer 0d2119da46 buildgcc: Update reference toolchain
* GCC 4.8.1
 * binutils 2.23.2
 * GDB 7.6
 * ACPICA 20130626
 * Python 3.3.2

... this adds support for Aarch64. For Ron.

Change-Id: Idec91bcd615bc35c83373bd23d4681f1c8eb015c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3758
Tested-by: build bot (Jenkins)
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-22 20:49:15 +02:00
Benoît Legat f42b83e958 msrtool: Fix verbose ignored by cpuid().
This is a trivial patch moving cpuid() call after reading argv
so that verbose is set.

Change-Id: Ic621191ef650495614a041413c1a0f707d4469e6
Signed-off-by: Benoît Legat <benoit.legat@gmail.com>
Reviewed-on: http://review.coreboot.org/3627
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-08 19:39:00 +02:00
Stefan Tauner e978fc265d cbmem: Fix makefile
The .dependencies rule did not use the CPPFLAGS variable which led
to funny behavior: a spurious termination message the first time
(after checkout/make distclean) one executes make. Afterwards the
(wrongly) empty .dependencies file hides the problem and the binary
is created anyway.

$ make
cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory
compilation terminated.
cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
cc   cbmem.o   -o cbmem

$ make
make: Nothing to be done for `all'.

$ make clean
rm -f cbmem *.o *~

$ make
cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
cc   cbmem.o   -o cbmem

$ make distclean
rm -f cbmem *.o *~
rm -f .dependencies

$ make
cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory
compilation terminated.
cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
cc   cbmem.o   -o cbmem

I fixed that by adding the CPPFLAGS variable to the .dependencies recipe, just
like Stefan Reinauer did in Chromium (Ia9d2e10a3ef122f30d681d16c2291eb108ead835),
hence the split sign-off for this tiny change. :)

Change-Id: Icd11b146ad762cbdf9774630b950f70e1253a072
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3548
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-01 23:12:22 +02:00
Marc Jones 66a68a2af8 abuild: Add xgcc tools to the path
abuild checks the path for toolchains prior to building a
mainboard. It didn't check xgcc/, which would be picked up
by the coreboot make, and fail to build when it shouldn't.

Change-Id: If0ca4238e8c57a6b015fdad623ccdbf237ef1ba6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/3350
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-25 00:36:31 +02:00
Nico Huber 413b0d9846 ifdfake - Create an IFD with just a section layout
This new tool called `ifdfake` just creates an empty Intel Firmware
Descriptor (IFD) and writes the IFD signature plus the section layout
given on the command line.

    usage: ifdfake [(-b|-m|-g|-p) <start>:<end>]... <output file>

       -b | --bios       <start>:<end>   BIOS region
       -m | --me         <start>:<end>   Intel ME region
       -g | --gbe        <start>:<end>   Gigabit Ethernet region
       -p | --platform   <start>:<end>   Platform Data region
       -h | --help                       print this help

    <start> and <end> bounds are given in Bytes, the <end> bound is inclusive.
    All regions must be multiples of 4K in size and 4K aligned.
    The descriptor region always resides in the first 4K.

    An IFD created with ifdfake won't work as a replacement for a real IFD.
    Never try to flash such an IFD to your board!

The output of ifdfake can be utilized to build an image with just the
later added sections (like coreboot itself) being valid. The resulting
image can then be partially written to a machines flash ROM to just
update coreboot (i.e. the BIOS section).

Change-Id: I925b47cab5c6d490a79d684bdd7a7a45ac442640
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3523
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 17:56:42 +02:00
Kyösti Mälkki 6aeb4a269c AMD: Drop empty root_complex
There are no files to build left under AMD nortbridge/x/root_complex
directories. For some cases, even the Kconfig file was no longer sourced.
Remove all such references and empty files.

For devicetree.cb treat component paths with "/root_complex" in them valid
even when the directory does not exists. This is because AMD boards us this
dummy chip component as the root node in their devicetree.cb.

The generated devicetree file static.c remains unchanged.

Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-24 17:22:44 +02:00
Stefan Tauner dbc6fcd021 inteltool: add initial support for Nehalem
Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)

Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.

The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...

Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-23 23:36:03 +02:00
Stefan Tauner 088f569400 util/inteltool: Add support for other 5 chipsets
e4e8e090fa does add support for QM57,
but there are many more that should work with that code(?).

Does not explode on...
CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
Northbridge: 8086:0044 (1st generation (Westmere family) Core Processor)
Southbridge: 8086:3b0f (QS57)

Change-Id: I85e15ba45678a5bd635415a7a8d69c05bff8f7ef
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3321
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-06-13 11:31:41 +02:00
Vladimir Serbinenko 083d35551c Add spkmodem receiver
This is spkmodem receiver counterpart.

Change-Id: Id27d32608502029fb6fcc8154f508811bf5ca77b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3411
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:18:24 +02:00
Patrick Georgi d2e0dd5bc1 buildgcc: Re-add some break statements
While some of the case .. break statement actually weren't needed,
too are, since otherwise the option parsing loop hangs.

Exit conditions for that endless loop: "--" or no more arguments,
in line with GNU command line parsing rules.

Change-Id: I0dbc35e530fb8c93a0f7de05ac47f325555ad4a4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3418
Tested-by: build bot (Jenkins)
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-06-09 08:34:45 +02:00
Olivier Langlois ccc7d1f229 Intel Atom cpu support to msrtool
Added support for Intel Atom cpu to msrtool
Fixed a cut&paste error in nehalem msr bits definition

It has been tested with a N455 cpu and msrtool output can be review at:
http://www.trillion01.com/coreboot/msrtool_atom.txt

Change-Id: I0ecf455b559185e2d16fa1a655bf021efc2ef537
Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
Reviewed-on: http://review.coreboot.org/3351
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 21:02:09 +02:00
Alexandru Gagniuc 67f556c296 viatool: Add utility to read various configuration bits on VIA systems
viatool is a utility for extracting useful for extracting certain configuration
bits on VIA chipsets and CPUs. It is a fork of inteltool.

viatool is currently focused on "quirks". Quirks are device configurations that
cannot be accessed directly. They are implemented as hierarchical configurations
in the PCI or memory address spaces (index/data register pairs). Such
configurations refer to hardware parameters that are board specific. Those
parameters would otherwise be difficult to extract from a system running the
vendor's firmware.

viatool also preserves inteltool's MSR dumps. VIA CPU and Intel CPU MSRs are
nearly identical.

Change-Id: Icbd39eaf7c7da5568732d77dbf2aed135f835754
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1430
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 22:36:26 +02:00
Nico Huber e25984b8c8 superiotool: Add dump facility for HWM of W83627DHG-P
Change-Id: I9355996a8cf1b7cb91cc415ec04f5108a1cc42a5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 21:14:55 +02:00
Nico Huber 28a1324303 superiotool: Add dump facility for ITE IT8516 + I/O 0x20e/f
Change-Id: Iaea08b7eb5aac9ff1e0756f1400a82641bb45b14
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3359
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 21:14:44 +02:00
David Hubbard 5b0420a87b crossgcc/buildgcc: Remove unneeded 'break' statements
Bash case statements are terminated with ';;'.

Unlike C, bash case statements will not continue to the next case. No 'break' is needed.

Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036
Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-on: http://review.coreboot.org/3330
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 01:15:20 +02:00
Nico Huber 8e4bb92898 util/cbmem: Fix format string in cbmem.c
Use PRIx64 to print a u64 instead of "llx". Fixes the following error:

cbmem.c: In function 'parse_cbtable':
cbmem.c:135:2: error: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'u64' [-Werror=format=]

Change-Id: Ibc2bf8597cb86db5b2e71fba77ec837a08c5e3d4
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3301
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-03 22:24:41 +02:00
Vladimir Serbinenko e4e8e090fa util/inteltool: Add support for mobile 5 chipset
Dump registers on mobile 5. Successfully tested on X201.

Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-27 02:53:49 +02:00
Ronald G. Minnich b460a66aa9 Get buildgcc to behave reasonably with the -p choice.
buildgcc has many wrong choices, and two right ones,
but you would never guess that. It's even more
frustrating when it spends lots of time building a
full tool chain and you find out it's not the one you
wanted and, still worse, you've forgotten what it does want
and, even worse, it won't f-ing tell you what the two
right choices are!.

Have it tell you when you've done something wrong, and have it
make reasonable decisions when you say things like
-p arm
instead of
-p armv7a-eabi

This change lowers my blood pressure 10 points.

Change-Id: I44a59d7cb7a6260894d8bcb692a693ed25681ff8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3292
Tested-by: build bot (Jenkins)
2013-05-26 18:18:52 +02:00
Roman Zippel 330bb6acc8 kconfig: fix choice dependency check
Properly check the dependency of choices as a group.
Also fix that sym_check_deps() correctly terminates the dependency loop
error check (otherwise it would continue printing the dependency chain).

Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

=======

Cherry-picked from the Linux kernel.

Change-Id: I0c98760dd0f55cf2ff70c53e0b014288b59574c8
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3290
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 11:50:11 +02:00
Roel Kluin 48757668a5 kconfig: reversed borderlines in inputbox
Fix reversal of dlg.border.atr and dlg.dialog.atr for draw_box()
Makes the inputbox look like expected

Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

=======

Cherry-picked from the Linux kernel.

Change-Id: I596915aab0204ef0e392fefa56fad8e25204e207
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3289
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 11:49:30 +02:00
Roman Zippel 543aa7ba7b kconfig: add named choice group
As choice dependency are now fully checked, it's quite easy to add support
for named choices. This lifts the restriction that a choice value can only
appear once, although it still has to be within the same group,
but multiple choices can be joined by giving them a name.
While at it I cleaned up a little the choice type logic to simplify it a
bit.

Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

=======

Cherry-picked from the Linux kernel.

Change-Id: If0f00d1783907d606220cda5307b8960d3bfc38d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3291
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 11:49:12 +02:00
Stefan Reinauer ec664bcfa4 romcc: support attribute((packed))
right now this is just a fake option to get rid of ifdefs in
coreboot's code.

Change-Id: I59233f3c1d266b4e716a5921e9db298c7f96751d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3225
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-10 19:33:00 +02:00
Ronald G. Minnich 711a6fde0d Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary
This option has never had much if any use. It solved a problem over 10
years ago that resulted from an argument over the value or lack thereof
of including all the debug strings in a coreboot image. The answer is
in: it's a good idea to maintain the capability to print all messages,
for many reasons.

This option is  also misleading people, as in a recent discussion, to
believe that log messges are controlled at build time in a way they are
not. For the record, from this day forward, we can print messages at all
log levels and the default log level is set at boot time, as directed by
DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and
if you are having trouble override it in CMOS and get more messages.

Besides, a quick glance shows it's always set to max (9 in this case) in
the very few cases (1) in which it is set.

Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3188
Tested-by: build bot (Jenkins)
2013-05-10 17:33:49 +02:00
Patrick Georgi a98d3061e9 nvramtool: Use CMOS_SIZE for cmos size
We write CMOS data to 128 byte files, which is a problem
when using them later-on (eg. as part of a coreboot image)
where nvramtool assumes them to be 256 byte, and so data
corruption occurs.

Change-Id: Ibc919c95f6d522866b21fd313ceb023e73d09fb9
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3186
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-04 00:14:11 +02:00
Idwer Vollering 37714f33a6 crossgcc: update to gcc 4.7.3
Update crossgcc to use gcc 4.7.3
The resulting coreboot.rom is not runtime tested (any volunteers?).

Drop the texinfo patch, rename the armv7a patch.

Some Linux distributions have moved on to gcc 4.8,
under certain circumstances this version can't (cross-)compile gcc 4.7.2
Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927

Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/3112
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-03 17:26:48 +02:00
Frank Rysanek c0c620e74a superiotool: add CR dump for W83627UHG = NCT6627UD
This commit adds "register dump capability" to
superiotool for a specific chip by Winbond/Nuvoton:
the W83627UHG   AKA   NCT6627UD  (same chip, different package).
In other words, it fills in the "CR map" definitions in winbond.c,
which so far have been void for this chip.
-
superiotool r4.0-3976-g190011e
Found Winbond W83627UHG = NCT6627UD (id=0xa2, rev=0x32) at 0x2e
Register dump:
idx 02 20 21 22 23 24 25 26  27 28 29 2a 2b 2c 2d 2e  2f
val ff a2 32 ff f0 44 00 00  ff 00 00 00 00 03 00 00  ff
def 00 a2 NA ff f0 MM 00 MM  RR 00 00 00 00 02 00 00  00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2  f4 f5
val 00 00 00 00 02 8e 00 ff  00 00
def 01 03 f0 06 02 8e 00 ff  00 00
LDN 0x01 (Parallel port)
idx 30 60 61 70 74 f0
val 00 03 78 0c 04 3f
def 01 03 78 07 04 3f
LDN 0x02 (UART A)
idx 30 60 61 70 f0
val 01 03 f8 04 00
def 01 03 f8 04 00
LDN 0x03 (UART B)
idx 30 60 61 70 f0 f1
val 01 02 f8 03 00 44
def 01 02 f8 03 00 00
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 72 f0
val 01 00 60 00 64 01 0c 82
def 01 00 60 00 64 01 0c 83
LDN 0x06 (UART C)
idx 30 60 61 70 f0
val 01 03 e8 05 80
def 01 03 e0 04 00
LDN 0x07 (GPIO 3, GPIO 4)
idx 30 e0 e1 e2 e3 e4 e5 e6  e7
val 04 ff ff ff ff ff ff ff  ff
def 00 ff 00 00 00 ff 00 00  00
LDN 0x08 (WDTO#, PLED, GPIO 5,6 & GPIO Base Address)
idx 30 60 61 e0 e1 e2 e3 e4  e5 e6 e7 f5 f6 f7
val 01 00 00 ff ff ff ff ff  ff ff ff 02 00 00
def 02 00 00 ff 00 00 00 ff  1f 00 00 00 00 00
LDN 0x09 (GPIO 1, GPIO 2 and SUSLED)
idx 30 e0 e1 e2 e3 e4 e5 e6  e7 f3
val 02 ff ff ff ff 00 ff 00  00 00
def 00 ff 00 00 00 ff 00 00  00 00
LDN 0x0a (ACPI)
idx 30 70 e0 e1 e2 e3 e4 e5  e6 e7 e8 e9 f2 f3 f4 f6  f7 fe
val 01 00 01 00 0a 00 00 00  0c 00 09 00 01 00 00 00  00 00
def 00 00 01 00 ff 08 00 00  1c 00 RR RR 3e 00 00 00  00 00
LDN 0x0b (Hardware monitor)
idx 30 60 61 70 f0 f1 f2
val 01 02 48 00 81 ff 81
def 00 00 00 00 RR RR 00
LDN 0x0c (PECI, SST)
idx e0 e1 e2 e3 e4 e5 e6 e7  e8 f1 f2 f3 fe ff
val 00 48 48 48 48 00 00 00  00 4c 50 10 23 5a
def 00 48 48 48 48 00 RR RR  00 48 50 10 23 5a
LDN 0x0d (UART D)
idx 30 60 61 70 f0
val 00 00 00 00 00
def 00 02 e0 03 00
LDN 0x0e (UART E)
idx 30 60 61 70 f0
val 00 00 00 00 80
def 00 03 e8 04 00
LDN 0x0f (UART F)
idx 30 60 61 70 f0
val 01 02 38 0a 00
def 00 02 e8 03 00

Change-Id: I834f8767b29f3148f353004edb22cfd7db5ddd56
Signed-off-by: Frank Rysanek <Frantisek.Rysanek@post.cz>
Reviewed-on: http://review.coreboot.org/3027
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-04-22 17:07:13 +02:00
Paul Menzel 8d9ffd93b5 cbmem: map_memory: Use length modifier `j` and cast for an `off_t` argument
cbmem currently fails to build due to `-Werror` and the following
warning.

    $ make
    cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
    cbmem.c: In function ‘map_memory’:
    cbmem.c:87:2: error: format ‘%zx’ expects argument of type ‘size_t’, but argument 2 has type ‘off_t’ [-Werror=format]
    […]

Casting the argument of type `off_t` to `intmax_t` and using the
length modifier `j`

    $ man 3 printf
    […]
           j      A following integer conversion corresponds to an intmax_t or uintmax_t argument.
    […]

instead of `z` as suggested in [1] and confirmed by stefanct and
segher in #coreboot on <irc.freenode.net>, gets rid of this warning
and should work an 32-bit and 64-bit systems, as an `off_t` fits
into `intmax_t`.

[1] http://www.pixelbeat.org/programming/gcc/int_types/

Change-Id: I1360abbc47aa1662e1edfbe337cf7911695c532f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3083
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16 17:46:28 +02:00
Paul Menzel 17c05f23e2 inteltool: pcie.c: Use `0xffULL` instead of `0xff` to avoid shift overflow
When building inteltool with Clang, it warns about the following.

    $ clang --version
    Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
    Target: i386-pc-linux-gnu
    Thread model: posix
    $ CC=clang make
    […]
    clang -O2 -g -Wall -W   -c -o pcie.o pcie.c
    pcie.c:297:40: warning: signed shift result (0xFF0000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                    pciexbar_phys = pciexbar_reg & (0xff << 28);
                                                    ~~~~ ^  ~~
    pcie.c:301:41: warning: signed shift result (0xFF8000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                    pciexbar_phys = pciexbar_reg & (0x1ff << 27);
                                                    ~~~~~ ^  ~~
    pcie.c:305:41: warning: signed shift result (0xFFC000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                    pciexbar_phys = pciexbar_reg & (0x3ff << 26);
                                                    ~~~~~ ^  ~~
    3 warnings generated.
    […]

Specifying the length by using the suffix `0xffULL` fixes these issues
as now enough bits are available.

These issues were introduced in commit 1162f25a [1].

    commit 1162f25a49
    Author: Stefan Reinauer <stepan@coresystems.de>
    Date:   Thu Dec 4 15:18:20 2008 +0000

        Patch to util/inteltool:
        * PMBASE dumping now knows the registers.
        * Add support for i965, i975, ICH8M
        * Add support for Darwin OS using DirectIO

[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1162f25a49e8f39822123d664cda10fef466b351

Change-Id: I7b9a15b04ef3bcae64e06266667597d0f9f07b79
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3015
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15 19:03:19 +02:00
Paul Menzel c3fc1e05a6 cbmem: Makefile: Allow to override `CC` variable
Now users can use a different compiler from GCC like Clang by for example
doing `CC=clang make`.

Change-Id: I664a36df79f7496a56d89bdb61948b2eda33a6b4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3082
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15 07:00:23 +02:00
Paul Menzel 15a1fd1db9 inteltool: Use portable type `uint64_t` instead of `u64`
In [1] Idwer Vollering noted, that the type `u64` is not portable so
on his FreeBSD system, the following warning is shown.

    $ clang -O2 -Wall -W -I/usr/local/include   -c -o amb.o amb.c
    amb.c:441:22: error: use of undeclared identifier 'u64'
                    ambconfig_phys = ((u64)pci_read_long(dev16, 0x4c) << 32) |

The type `uint64_t` seems to be defined also on FreeBSD, so using this
fixes the warning.

Note, this warning is not reproducable with Debian Sid/unstable for
example. I have no idea why though.

[1] http://review.coreboot.org/#/c/3015/

Change-Id: Ic22f4371114b68ae8221d84a01fef6888d43f365
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3086
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-14 23:00:35 +02:00
Paul Menzel cb891de07f cbmem: parse_cbtable: Use length modifier `ll` `u64` argument
Currently on a 32-bit system cbmem fails to build due to `-Werror`
and the following warning.

    $ make
    cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
    […]
    cbmem.c: In function ‘parse_cbtable’:
    cbmem.c:135:2: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘u64’ [-Werror=format]
    cc1: all warnings being treated as errors
    […]

Using the length modifier `ll` instead of `l` gets rid of this
warning.

Change-Id: Ib2656e27594c7aaa687aa84bf07042933f840e46
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3084
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-14 02:06:21 +02:00
Paul Menzel 2c8f81b57b cbfstool: cbfs-mkstage.c: Free `buffer` on error path
Cppcheck warns about a memory leak, present since adding romtool,
which was renamed to cbfstool, in commit 5d01ec0f.

    $ cppcheck --version
    Cppcheck 1.59
    […]
    [cbfs-mkstage.c:170]: (error) Memory leak: buffer
    […]

Indeed the memory pointed to by `buffer` is not freed on the error path,
so add `free(buffer)` to fix this.

Change-Id: I6cbf82479027747c800c5fe847f20b779e261ef4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3069
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-12 20:22:39 +02:00
Idwer Vollering e76d8d7ced acpica: update URL
The URL to acpica-unix-20121114 has changed, update the URL.

Change-Id: I1c8c228094f19455af3682f36f1990586fe3934c
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/3070
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-12 20:15:51 +02:00
Vladimir Serbinenko f4a0d019fa util/cbmem: Don't output trailing garbage for cbmemc
Current code outputs the whole cbmemc buffer even if only part of
it is really used. Fix it to output only the used part and notify
the user if the buffer was too small for the required data.

Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2991
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-09 23:52:36 +02:00
Stefan Reinauer 33e83caff5 cbfstool: completely initialize input and output streams
The LZMA glue code in cbfstool was recently rewritten from C++
to plain C code in:

        commit aa3f7ba36e
        Author: Stefan Reinauer <reinauer@chromium.org>
        Date:   Thu Mar 28 16:51:45 2013 -0700

            cbfstool: Replace C++ code with C code

            Reviewed-on: http://review.coreboot.org/3010

In the progress of doing so, the stream position for the
input stream and output stream was not reset properly. This
would cause LZMA producing corrupt data when running the
compression function multiple times.

Change-Id: I096e08f263aaa1931517885be4610bbd1de8331e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3040
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 21:36:37 +02:00
Stefan Tauner 0c8b7d1ac2 inteltool: remove unused file descriptor variable and ifdefs
Change-Id: I6a119b1f362f481914377e8d14c713159f895130
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3030
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 18:17:59 +02:00
Stefan Tauner 0dc775e894 inteltool: use inttypes for prints in memory.c
This fixes at least one warning on my machine where "llx" is replaced by PRIx64.

Change-Id: Iee3e5027d327d4d5f8e6d8b2d53d051f74bfc354
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-05 20:21:35 +02:00
Paul Menzel 5f3754e66d inteltool: cpu.c: Use conversion specifier `u` for unsigned integers
Cppcheck [1], a static code analysis tool, warns about the
following.

    $ cppcheck --version
    Cppcheck 1.59
    $ cppcheck --enable=all .
    […]
    Checking cpu.c...
    [cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
    [cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
    […]

And indeed, `core` is an unsigned integer and `man 3 printf` tells
the following about conversion specifiers.

       d, i   The int argument is converted to signed decimal notation. […]

       o, u, x, X
              The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or  unsigned  hexadecimal  (x  and  X)
              notation.

So use `u` and Cppcheck does not complain anymore.

[1] http://cppcheck.sourceforge.net/

Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3026
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-05 20:17:03 +02:00
Paul Menzel 72ef8881a3 libpayload, superiotool: README: Prepend `coreboot/` to path of change directory line
Nico Huber spotted [1], that commit (4d6ab4e2) [1] updating
superiotools’s `README` with the Git command line

    superiotool: Update README with Git repository URL and directory location

missed, that after `git clone` one sitll has to change into
the cloned directory.

So prepend the path with `coreboot/` to fix that. The same error
happened in the commit (e1ea5151) for libpayload [2]

    libpayload: Update README with Git repository URL and directory location

and is fixed in this patch too.

[1] http://review.coreboot.org/#/c/3019/
[2] http://review.coreboot.org/2228

Change-Id: Ib6e8b678af6276556a40ccfd52ae35ca7e674455
Reported-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3021
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-04-04 17:22:15 +02:00
Paul Menzel 3402a7fa70 inteltool: Cast to `intptr_t` instead of `uint64_t`
When building inteltool under x86-32, the following warnings are
shown.

    $ gcc --version
    gcc-4.7.real (Debian 4.7.2-15) 4.7.2
    Copyright (C) 2012 Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.  There is NO
    warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    $ make
    […]
    amb.c: In function ‘amb_read_config32’:
    amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config16’:
    amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config8’:
    amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    […]

Nico Huber commented the following [1].

    I don't see those warnings because I build for x86-64. I guess
    they could be fixed by casting to `ptrdiff_t` (from stddef.h)
    instead of `uint64_t`.

And indeed, using `ptrdiff_t` fixes the warning. But as Stefan
Reinauer commented in [2], `intptr_t` is more appropriate as this
is just a pointer and no pointer difference.

So `intptr_t` is taken, which fixes these issues warned about too.

These warnings were introduced in commit »inteltool: Add support for
dumping AMB registers« (4b7b320f) [3].

[1] http://review.coreboot.org/#/c/2996/1//COMMIT_MSG
[2] http://review.coreboot.org/#/c/3002/1/util/inteltool/amb.c
[3] http://review.coreboot.org/525

Change-Id: I2ea1a31dc1e3db129e767d6a9e0433fd75a77d0f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3002
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-04-04 14:24:25 +02:00
Paul Menzel 4d6ab4e2ae superiotool: Update README with Git repository URL and directory location
Change-Id: I36d980cea5ca9cc67262dba809441091757e1fb5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3019
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-04 04:50:00 +02:00
Paul Menzel a8db717d4a inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t`
When buidling inteltool with GCC, the following warning is printed.

    $ make
    […]
    gcc -O2 -g -Wall -W   -c -o memory.o memory.c
    memory.c: In function ‘print_mchbar’:
    memory.c:287:7: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ [-Wformat]
    […]

This was introduced in commit »inteltool: Add support for H65 Express
chipset« (c7fc4422) [1].

Address this warning, by using `%llx` instead of `%lx`.

[1] http://review.coreboot.org/1258

Change-Id: I4f714edce7e8b405e1a7a417d02fa498322c88a8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2994
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-03 11:13:29 +02:00
Stefan Reinauer aa3f7ba36e cbfstool: Replace C++ code with C code
cbfstool was using a C++ wrapper around the C written LZMA functions.
And a C wrapper around those C++ functions. Drop the mess and rewrite
the functions to be all C.

Change-Id: Ieb6645a42f19efcc857be323ed8bdfcd9f48ee7c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3010
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-03 02:35:28 +02:00
Stefan Reinauer 60a4a73fcd cbfstool: fix --machine
The help text says --machine, but the code
actually checked for --arch. Fix it!

Change-Id: Ib9bbf758b82ef070550348e897419513495f154b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3009
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-02 20:27:10 +02:00
Paul Menzel 9ebd8ea7cf inteltool: Allow to override Makefile variables
Allow to override the variables `CC`, `INSTALL`, `PREFIX`,
`CFLAGS` and `LDFLAGS`. Though append `-lpci -lz` to `LDFLAGS`.

This way for example a different compiler can easily be used.

    CC=clang make

As a side note, Clang in contrast to GCC does *not* issue the
following warnings.

    $ clang --version
    Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
    Target: i386-pc-linux-gnu
    Thread model: posix
    $ gcc --version
    gcc-4.7.real (Debian 4.7.2-15) 4.7.2
    Copyright (C) 2012 Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.  There is NO
    warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    $ make
    […]
    amb.c: In function ‘amb_read_config32’:
    amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config16’:
    amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config8’:
    amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    […]

These are only shown under 32-bit and not 64-bit

    $ uname -m
    i686

and are going to be fixed in a separate patch.

Change-Id: Id75dea081ecb35390f283520a7e5dce520f4c98d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2996
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 22:40:45 +02:00
Nico Huber 42c5501c39 inteltool: Add Cougar/Panther Point GPIO defaults
This adds default values for the GPIO setup on Intel's Cougar Point and
Panther Point platform controller hubs (PCH). Values are taken from [1] and
[2], respectively. I've tested this with an H77 PCH. See below for the
output.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
    Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
    Datasheet
    Document-Number: 326776-003

$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

========== GPIO DIFFS ===========

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF

gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF

gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF

gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF

gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF

gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF

gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF

gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF

gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF

gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF

gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF

$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

============= GPIOS =============

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)

Change-Id: If99cf8d5c93e34ad28f52080fff64e01c220eb27
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 22:39:30 +02:00
Nico Huber 09dcbf0cdb inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.

Here's a preview:

$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

========== GPIO DIFFS ===========

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF

gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF

gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF

gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF

gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF

gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF

gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF

gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF

gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF

gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF

gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF

$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

============= GPIOS =============

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)

Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 22:39:04 +02:00
Nico Huber 5ed986b8ab inteltool: Support PM registers on Cougar/Panther Point
This adds the power management register definitions for Intel's Cougar
Point and Panther Point platform controller hubs (PCH). The definitions
are actually a subset of the older ICH10R registers: I've added just
those that are mentioned in the public specifications in [1] and [2].
I've tested dumping with an H77 PCH.

NM70 is missing in [1]. Therefore, I didn't add it here.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
    Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
    Datasheet
    Document-Number: 326776-003

Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2985
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 21:00:16 +02:00
Nico Huber 14290b3cbb inteltool: Add Cougar/Panther Point IDs to rootcmplx.c
This adds the PCI IDs of Intel's Cougar Point and Panther Point platform
controller hubs (PCH) to the dumping of the root complex configuration
under the root complex base address (RCBA). Those PCHs are handled exactly
as the older ICHs which can be seen in [1] and [2]. I've tested dumping
with an H77 PCH.

NM70 is missing in [1]. Therefore, I didn't add it here.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
    Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
    Datasheet
    Document-Number: 326776-003

Change-Id: I2296caae57e614171300362d41715deecec77762
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-30 18:17:08 +01:00
Paul Menzel be2c6340b3 superiotool: Allow to override Makefile variables `CC`, `INSTALL` and `PREFIX`
This way for example a different compiler can easily be used.

    CC=clang make

Change-Id: I50b83554fd4826d00d87e60a30eb1f6a88834397
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2935
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29 21:32:48 +01:00
Nico Huber 6983a6829a inteltool: Support GPIO registers on Cougar/Panther Point
This adds the GPIO register definitions for Intel's Cougar Point and
Panther Point platform controller hubs (PCH). All information is taken
from the public specifications in [1] and [2]. I've tested it with an
H77 PCH.

NM70 is missing in [1]. Therefore, I didn't add it here.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
    Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
    Datasheet
    Document-Number: 326776-003

Change-Id: I31711e24f852e68b3c113e3bd9243dc7e89ac197
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2961
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29 21:07:55 +01:00
Nico Huber 76d60494ef inteltool: Add definitions for Cougar/Panther Point PCI IDs
This adds correspondings #defines for the PCI IDs of the LPC device on
Intel's Cougar Point and Panther Point platform controller hubs. Those
will be used more in later commits.

I've checked all those IDs against the specification updates [1] and [2].

[1] Intel 6 Series Chipset and Intel C200 Series Chipset Specification
    Update
    Document-Number: 324646-019

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)
    Family - Datasheet Specification Update
    Document-Number: 326777-010

Change-Id: Ibef5a30d283c568c345eb8d8149723e7a3049272
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2960
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29 21:07:30 +01:00
Nico Huber 69a21b1eb9 crossgcc: Fix building with texinfo-5.x
If you have a recent version of texinfo installed, building the reference
toolchain fails with the following error:
(in util/crossgcc/build-gcc/crossgcc-build.log)

[...]/gcc-4.7.2/gcc/doc/cppopts.texi:806: @itemx must follow @item

Looks like a warning-became-an-error problem in texinfo, to me. Fix that by
making every erroneous @itemx an @item.

Change-Id: I685ae1ecfee889b7c857b148cfab7411a10e7ecd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2939
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2013-03-28 21:14:50 +01:00
Aaron Durbin 6b0d0d6e14 cbfstool: Add update-fit command
Add support for filling in the Firmware Interface Table.
For now it only supports adding microcode entries.

It takes 2 options:
1. Name of file in cbfs where the mircocode is located
2. The number of empty entries in the table.

Verified with go firmware tools. Also commented out updating
microcode in the bootblock. When romstage runs, the CPUs indicate
their microcode is already loaded.

Change-Id: Iaccaa9c226ee24868a5f4c0ba79729015d15bbef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2712
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-03-27 01:25:12 +01:00
Stefan Reinauer dc7bc8e589 cbfstool: Fix cbfs_image.c
- The read-only structures are const now
- cosmetic fixes
  - put { on a new line for functions
  - move code after structures

Change-Id: Ib9131b80242b91bd5105feaebdf8306a844da1cc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2922
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-03-27 01:24:48 +01:00
Aaron Durbin 73982c3c68 xcompile: honor LINKER_SUFFIX variable
In commit e820e5cb3a titled
"Make xcompile support multiple architectures" the LINKER_SUFFIX
variable was introduced to bypass gold if the bfd linker was
available. However, the LINKER_SUFFIX wasn't honored when
the compiler evironment variables were set. Fix the original
intention.

Change-Id: I608f1e0cc3d0bea3ba1e51b167d88c66d266bceb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2879
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23 19:32:44 +01:00
Hung-Te Lin b02c873190 cbfstool: Fix initial empty space in image creation.
When calculating initial CBFS empty entry space, the size of header itself must
be not included (with the reserved space for entry name). This is a regression
of the old cbfstool size bug.

Before this fix, in build process we see:
 OBJCOPY    cbfs/fallback/romstage_null.bin
 W: CBFS image was created with old cbfstool with size bug.
    Fixing size in last entry...

And checking the output binary:
 cbfstool build/coreboot.pre1 print -v -v
 DEBUG: read_cbfs_image: build/coreboot.pre1 (262144 bytes)
 DEBUG: x86sig: 0xfffffd30, offset: 0x3fd30
 W: CBFS image was created with old cbfstool with size bug.
    Fixing size in last entry...
 DEBUG: Last entry has been changed from 0x3fd40 to 0x3fd00.
 coreboot.pre1: 256 kB, bootblksz 688, romsize 262144, offset 0x0 align: 64
 Name                           Offset     Type         Size
 (empty)                        0x0        null         261296
 DEBUG:  cbfs_file=0x0, offset=0x28, content_address=0x28+0x3fcb0

After this fix, no more alerts in build process.
Verified to build successfully on x86/qemu and arm/snow configurations.

Change-Id: I35c96f4c10a41bae671148a0e08988fa3bf6b7d3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2731
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22 00:21:41 +01:00
Hung-Te Lin e4ea2ca18d cbfstool locate: Implement alignment switch --align/-a
cbfstool usage change:
 "-a" for "cbfstool locate" can specify base address alignment.

To support putting a blob in aligned location (ex, microcode needs to be aligned
in 0x10), alignment (-a) is implemented into "locate" command.

Verified by manually testing a file (324 bytes) with alignment=0x10:
 cbfstool coreboot.rom locate -f test -n test -a 0x10
 # output: 0x71fdd0
 cbfstool coreboot.rom add -f test -n test -t raw -b 0x71fdd0
 cbfstool coreboot.rom print -v -v
 # output: test                           0x71fd80   raw          324
 # output:  cbfs_file=0x71fd80, offset=0x50, content_address=0x71fdd0+0x144

Also verified to be compatible with old behavior by building i386/axus/tc320
(with page limitation 0x40000):
 cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000
 # output: 0x44
 cbfstool coreboot.rom locate -f x.bin -n romstage -P 0x40000 -a 0x30
 # output: 0x60

Change-Id: I78b549fe6097ce5cb6162b09f064853827069637
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2824
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-03-20 05:47:32 +01:00
Hung-Te Lin e91983767c cbfstool locate: Rename -a align switch to -P for page size
cbfstool usage change:
   The "-a" parameter for "cbfstool locate" is switched to "-P/--page-size".

The "locate" command was used to find a place to store ELF stage image in one
memory page. Its argument "-a (alignment)" was actually specifying the page size
instead of doing memory address alignment. This can be confusing when people are
trying to put a blob in aligned location (ex, microcode needs to be aligned in
0x10), and see this:
  cbfstool coreboot.rom locate -f test.bin -n test -a 0x40000
  # output: 0x44, which does not look like aligned to 0x40000.

To prevent confusion, it's now switched to "-P/--page-size".

Verified by building i386/axus/tc320 (with page limitation 0x40000):
 cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000
 # output: 0x44

Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731
Reviewed-on: http://review.coreboot.org/2730
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-03-19 11:12:10 +01:00
Андрей Павлов ab9b71d54c superiotool: Add support for the IT8728F Super I/O
$ superiotool -d
superiotool r4.0-3712-gd549279
Found ITE IT8728F (id=0x8728, rev=0x1) at 0x2e
Register dump:
idx 02 07 20 21 22 23 24 2b  2e 2f
val 00 0a 87 28 01 00 00 40  00 00
def NA NA 87 28 01 00 00 MM  00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1
val 00 03 f0 06 02 00 00
def 00 03 f0 06 02 00 00
LDN 0x01 (COM1)
idx 30 60 61 70 f0 f1
val 01 03 f8 04 00 50
def 00 03 f8 04 00 50
LDN 0x02 (COM2)
idx 30 60 61 70 f0 f1
val 00 02 f8 03 00 50
def 00 02 f8 03 00 50
LDN 0x03 (Parallel port)
idx 30 60 61 62 63 70 74 f0
val 01 03 78 00 00 07 04 08
def 00 03 78 07 78 07 03 03
LDN 0x04 (Environment controller)
idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6 f9 fa fb
val 01 0a 30 0a 20 09 00 80  00 00 20 00 f0 48 00 00
def 00 02 90 02 30 09 00 00  00 00 00 MM MM MM MM MM
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 71 f0
val 01 00 60 00 64 01 02 08
def 01 00 60 00 64 01 02 48
LDN 0x06 (Mouse)
idx 30 70 71 f0
val 01 0c 02 00
def 00 0c 02 00
LDN 0x07 (GPIO)
idx 25 26 27 28 29 2a 2c 2d  60 61 62 63 64 65 70 71  72 73 74 b0 b1 b2 b3 b4  b8 b9 ba bb bc bd c0 c1  c2 c3 c4 c8 c9 ca cb cc  cd ce cf e0 e1 e2 e3 e4  e9 f0 f1 f2 f3 f4 f5 f6  f7 f8 f9 fa fb
val 00 f3 10 00 00 00 80 00  00 00 0a 00 00 00 00 00  20 00 00 00 00 00 00 00  20 00 00 00 00 00 01 00  00 40 00 01 00 00 00 00  00 00 00 00 00 00 00 00  21 10 42 00 00 00 00 1c  00 00 00 00 00
def 00 f3 00 00 00 00 03 00  00 00 00 00 00 00 00 00  20 38 00 00 00 00 00 00  20 00 00 00 00 00 01 00  00 40 00 01 00 00 40 00  00 00 00 00 00 00 00 00  MM 00 00 00 00 00 00 00  00 00 00 00 00
LDN 0x0a (Consumer IR)
idx 30 60 61 70 f0
val 00 03 10 0b 06
def 00 03 10 0b 06

Change-Id: Ifb45d28005d78b2a99d8552b59154d11bdf44f6f
Signed-off-by: Андрей Павлов <7134956@gmail.com>
Reviewed-on: http://review.coreboot.org/2775
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-17 23:20:38 +01:00
Ronald G. Minnich c2c97231e3 Show the device tree.
This is a bit of a hack but it's very handy. It compiles in your static.c
and then shows what coreboot would see when it is run. It uses your static.c
and functions pulled from src/device/device_util.c.
I've already used it to debug problems with the snow device tree.

I'm waiting someone to tell me this is already written :-)

Change-Id: Ia8c8a5d08d8757bec49eaf70473efa701bc56581
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2767
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-16 04:30:16 +01:00
Paul Menzel a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Patrick Georgi 12781422d5 nvramtool: reduce memory mapping
Instead of trying to map the first megabyte, only map what is
required to read the tables.

Change-Id: I9139dbc8fd1dd768bef7ab85c27cd4c18e2931b3
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/2485
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-22 16:04:03 +01:00
Patrick Georgi 11a7db3b57 romcc: Don't fail on function prototypes
Instead, ignore them. One is as non-standard as the other
and ignoring is more convenient since we don't need to
guard prototypes with #ifndef __ROMCC_ all the time.

Change-Id: I7be93a2ed0966ba1a86f0294132a204e6c8bf24f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2424
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19 11:01:05 +01:00
Hung-Te Lin 7b654a9702 cbfstool: Fix compile warnings caused by incorrect data types.
The "offset" in cbfs-mkpayload should be printed as type %lu
instead of %d as `gcc` rightfully warns about.

    gcc -g -Wall -D_7ZIP_ST -c -o /srv/filme/src/coreboot/util/cbfstool/cbfs-mkpayload.o cbfs-mkpayload.c
    cbfs-mkpayload.c: In function ‘parse_fv_to_payload’:
    cbfs-mkpayload.c:284:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]
    cbfs-mkpayload.c:296:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]

This warning was introduced in the following commit.

    commit 4610247ef1
    Author: Patrick Georgi <patrick@georgi-clan.de>
    Date:   Sat Feb 9 13:26:19 2013 +0100

        cbfstool: Handle alignment in UEFI payloads

        Reviewed-on: http://review.coreboot.org/2334

Change-Id: I50c26a314723d45fcc6ff9ae2f08266cb7969a12
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2440
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-02-18 12:28:43 +01:00
Paul Menzel 475d42a16c cbfstool: Add `-Werror` to make all warnings into errors
Ensure that no changes with warnings are committed. Although using
`-Werror` is debatable [1][2].

[1] http://blog.flameeyes.eu/2009/02/future-proof-your-code-dont-use-werror
[2] http://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html

Change-Id: I402f2d82dd4087d8a575b0a85305a02ef04bb537
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2441
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-18 12:10:44 +01:00
Stefan Reinauer 0aa37c488b sconfig: rename lapic_cluster -> cpu_cluster
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.

Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 07:07:20 +01:00
Stefan Reinauer 4aff4458f5 sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.

Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 02:00:10 +01:00
Hung-Te Lin ebae438bf2 crossgcc: Support hosts using non-GNU make as default make.
On hosts using non-GNU make as default make program (ex, FreeBSD's default is
BSD make and having GNU make as "gmake"), building acpica will fail. We should
use the correct path of make $(MAKE).

Verified to build on FreeBSD 9.0 with gcc 4.7 from ports. Note, the shipped gcc
in FreeBSD 9.0 is 4.2.1 and needs more patches to remove -Wbad-function-case and
-Wempty-body. That should be fixed in a future patch.

Change-Id: Iacbf5a05e84a8a53d9d3e783a10131de603282c9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-11 14:34:17 +01:00
Patrick Georgi 4610247ef1 cbfstool: Handle alignment in UEFI payloads
Tiano for X64 is much cleaner to start up when using higher alignments in
firmware volumes. These are implemented using padding files and sections
that cbfstool knew nothing about. Skip these.

Change-Id: Ibc433070ae6f822d00af2f187018ed8b358e2018
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2334
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09 20:58:22 +01:00
Hung-Te Lin 408aefd176 cbfstool: Fix crash on image without bootblock in end of ROM.
On platforms with CBFS data filling end of ROM image without bootblock in the
end (ex, ARM), calculation of "next valid entry" may exceed ROM image buffer in
memory and raise segmentation fault when we try to compare its magic value.

To fix this, always check if the entry address is inside ROM image buffer.

Verified to build and boot successfully on qemu/x86 and armv7/snow.

Change-Id: I117d6767a5403be636eea2b23be1dcf2e1c88839
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2330
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-09 06:30:10 +01:00
Zheng Bao 30b895f7e2 crossgcc: Save the script itself when cross build is over.
In case that the new toolchains don't work well, we can trace back
and reproduce the old tools by checking the xgcc folder. It is useful
when my team members need to get my old toolchains on their own host
machines.

Change-Id: I54e4bc6afcfbbf622165af6eae27bbb6efc2e8cc
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2247
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-06 19:25:43 +01:00
Hung-Te Lin c5ff6487e6 armv7: Prevent CBFS data overlapping bootblock.
For arm/snow, current bootblock is larger than previously assigned CBFS offset
and will fail to boot. To prevent this happening again in future, cbfstool now
checks if CBFS will overlap bootblock.

A sample error message:
	E: Bootblock (0x0+0x71d4) overlap CBFS data (0x5000)
	E: Failed to create build/coreboot.pre1.tmp.

arm/snow offset is also enlarged and moved to Kconfig variable.

Change-Id: I4556aef27ff716556040312ae8ccb78078abc82d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2295
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 10:53:19 +01:00
Stefan Reinauer e87641840f cbfstool: Add support for 64bit UEFI
Right now cbfstool only accepts firmware volumes with
a x86 SEC core and refuses an x86-64 SEC core because
some magic values and the extended PE header are
different. With this patch, both IA32/x64 images are
supported. (No check is done whether the mainboard
actually supports 64bit CPUs, so careful!)

This needs another patch to Tiano Core that switches
to long mode after jumping to the 64bit entry point.
Right now that code assumes we're already in 64bit code
and the machine crashes.

Change-Id: I1e55f1ce1a31682f182f58a9c791ad69b2a1c536
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2283
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-06 00:37:26 +01:00
Stefan Reinauer 543a682458 cbfstool: support parsing UEFI firmware volumes
This removes the hack implemented in http://review.coreboot.org/#/c/2280
(and should make using 64bit Tiano easier, but that's not yet supported)

Change-Id: Ie30129c4102dfbd41584177f39057b31f5a937fd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2281
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:43:23 +01:00
Hung-Te Lin c13e4bf3e1 cbfstool: Use cbfs_image API for "add-*" (add-payload, add-stage, ...) commands.
add-payload, add-stage, and add-flat-binary are now all using cbfs_image API.
To test:
	cbfstool coreboot.rom add-stage -f FILE -n fallback/romstage -b 0xXXXX
	cbfstool coreboot.rom add-payload -f FILE -n fallback/pyload
And compare with old cbfstool.

Verified to boot on ARM(snow) and X86(qemu-i386).

Change-Id: If65cb495c476ef6f9d90c778531f0c3caf178281
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2220
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:27:20 +01:00
Hung-Te Lin 5f3eb26d85 cbfstool: Use cbfs_image api for "add" command.
The "add" command is compatible with all legacy usage. Also, to support
platforms without top-aligned address, all address-type params (-b, -H, -l) can
now be ROM offset (address < 0x8000000) or x86 top-aligned address (address >
0x80000000).

Example:
	cbfstool coreboot.rom add -f config -n config -t raw -b 0x2000
	cbfstool coreboot.rom add -f stage -n newstage -b 0xffffd1c0

Verified boot-able on both ARM(snow) and x86(QEMU) system.

Change-Id: I485e4e88b5e269494a4b138e0a83f793ffc5a084
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2216
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:27:13 +01:00
Hung-Te Lin f56c73f1e1 cbfstool: Use cbfs_image API for "create" command.
Usage Changes: To support platforms with different memory layout, "create" takes
two extra optional parameters:

    "-b": base address (or offset) for bootblock. When omitted, put bootblock in
          end of ROM (x86  style).
    "-H": header offset. When omitted, put header right before bootblock,
          and update a top-aligned virtual address reference in end of ROM.

  Example: (can be found in ARM MAkefile):
    cbfstool coreboot.rom create -m armv7 -s 4096K -B bootblock.bin \
             -a 64 -b 0x0000 -H 0x2040 -o 0x5000

Verified to boot on ARM (Snow) and X86 (QEMU).

Change-Id: Ida2a9e32f9a459787b577db5e6581550d9d7017b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2214
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:27:08 +01:00
Hung-Te Lin 215d1d7c9b cbfstool: Use cbfs_image API for "locate" command.
To support platforms without top-aligned address mapping like ARM, "locate"
command now outputs platform independent ROM offset by default.  To retrieve x86
style top-aligned virtual address, add "-T".

To test:
	cbfstool coreboot.rom locate -f stage -n stage -a 0x100000 -T
	# Example output: 0xffffdc10

Change-Id: I474703c4197b36524b75407a91faab1194edc64d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2213
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:27:03 +01:00
Hung-Te Lin 49fcd75564 cbfstool: Fix incorrect CBFS free space by old cbfstool.
Old cbfstool may produce CBFS image with calculation error in size of last empty
entry, and then corrupts master header data when you really use every bit in
last entry. This fix will correct free space size when you load ROM images with
cbfs_image_from_file.

Change-Id: I2ada319728ef69ab9296ae446c77d37e05d05fce
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2211
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:26:58 +01:00
Hung-Te Lin c03d9b0c43 cbfstool: Use cbfs_image API for "remove" command.
To delete a component (file) from existing CBFS ROM image.

To test:
	cbfstool coreboot.rom remove -n fallback/romstage
	# and compare with old cbfstool output result.

Change-Id: If39ef9be0b34d8e3df77afb6c9f944e02f08bc4e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2208
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:26:53 +01:00
Hung-Te Lin 0f8af71f1a cbfstool: Use cbfs_image API for "extract" command.
Change the "extract" command to use cbfs_export_entry API. Nothing changed in
its usage.

To verify, run "cbfstool coreboot.rom extract -f blah -n blah" and check if the
raw type file is correctly extracted.

Change-Id: I1ed280d47a2224a9d1213709f6b459b403ce5055
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2207
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:25:20 +01:00
Hung-Te Lin 3bb035b095 cbfstool: Use cbfs_image API for "print" command.
Process CBFS ROM image by new cbfs_image API.
To verify, run "cbfstool coreboot.rom print -v" and compare with old cbfstool.

Change-Id: I3a5a9ef176596d825e6cdba28a8ad732f69f5600
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2206
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:25:13 +01:00
Hung-Te Lin eab2c81949 cbfstool: Add cbfs_image new CBFS image manipulation API.
Current cbfstool implementation is relying on global variables to pass processed
data, and the calculation of address is based on x86 architecture (ex, always
assuming 0x0000 as invalid address), not easy to be used on platforms without
top-aligned memory mapping. This CL is a first step to start a new cbfstool
without global variables, and to prevent assuming memory layout in x86 mode.

The first published APIs are for reading and writing existing CBFS ROM image
files (and to find file entries in a ROM file).

Read cbfs_image.h for detail usage of each API function.

Change-Id: I28c737c8f290e51332119188248ac9e28042024c
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2194
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:25:02 +01:00
Hung-Te Lin 3cfacbf196 cbfstool: Add buffer management API.
Many functions in cbfstool need to deal with a memory buffer - both location and
size. Right now it's made by different ways: for ROM image using global variable
(romsize, master_header); and in cbfs-* using return value for size and char**
to return memory location.

This may cause bugs like assuming incorrect return types, ex:
	uint32_t file_size = parse();	// which returns "-1" on error
	if (file_size <= 0) { ...
And the parse error will never be caught.

We can simplify this by introducing a buffer API, to change
	unsigned int do_something(char *input, size_t len, char **output, ...)
into
	int do_something(struct buffer *input, struct buffer *output, ...)

The buffer API will be used by further commits.

Change-Id: Iaddaeb109f08be6be84c6728d72c6a043b0e7a9f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2205
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:24:45 +01:00
David Hendricks dada1259a2 crossgcc: add armv7a-eabi to list of working toolchains
Change-Id: Ibf221db4ca60d802b460d56f5fcca95ff49fc542
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2273
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-04 16:44:26 +01:00
Hung-Te Lin 5be66730cf cbfstool: Update example file.
The syntax of cbfstool has been changed for a while (using getopt). Updated
EXAMPLE file to show the right way to test cbfstool.

Change-Id: I5cb41b76712d8c2403fffc9fdad83c61fb2af98c
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2215
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-04 11:12:15 +01:00
Hung-Te Lin 332795cc59 cbfstool: Make endian detection functions to work without prior setup.
The 'host_bigendian' variable (and functions relying on it like ntohl/htonl)
requires host detection by calling static which_endian() first -- which may be
easily forgotten by developers.  It's now a public function in common.c and
doesn't need initialization anymore.

Change-Id: I13dabd1ad15d2d6657137d29138e0878040cb205
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2199
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-01 06:50:17 +01:00
Hung-Te Lin 05dccae75d cbfstool: move flat-binary parsing to cbfs-mkpayload.
The ELF parsing and payload building in add-flat-binary command should be
isolated just like mkpayload and mkstage.

Since the add-flat-binary command creates a payload in the end , move payload
processing to cbfs-mkpayload.c.

To test:
   cbfstool coreboot.rom add-flat-binary -f u-boot.bin -n fallback/payload \
	-l 0x100000 -e 0x100020

To verify, get output from "cbfstool coreboot.rom print -v":
   fallback/payload               0x73ccc0   payload      124920
   INFO:     code  (no compression, offset: 0x38, load: 0x1110000, length:..)

Change-Id: Ia7bd2e6160507c0a1e8e20bc1d08397ce9826e0d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2197
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-01 06:06:41 +01:00
Hung-Te Lin 4d87d4e09b cbfstool: Add -v (verbose) output.
Add -v (verbose) to every command, and allow printing debug messages.

Revise logging and debugging functions (fprintf(stderr,...), dprintf...)
and verbose message printing with following macros:
	ERROR(xxx):	E: xxx
	WARN(xxx)	W: xxx
	LOG(xxx)	xxx
	INFO(...)	INFO: xxx  (only when runs with -v )
	DEBUG(...)	DEBUG: xxx (only when runs with more than one -v)

Example:
	cbfstool coreboot.rom print -v
	cbfstool coreboot.rom add -f file -n file -t raw -v -v

Normal output (especially for parsing) should use printf, not any of these
macros (see usage() and cbfs_locate(), cbfs_print_directory() for example).

Change-Id: I167617da1a6eea2b07075b0eb38e3c9d85ea75dc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2196
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-01 05:54:24 +01:00
Ronald G. Minnich 21d0fc0d37 Add a clean target to the run firmware (runfw) Makefile
It's just good hygiene.

Change-Id: Ie7d4557c1d0dcf7fc015852c4c9b2eae29c4acfc
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-30 21:22:04 +01:00
Hung-Te Lin 5a9f45c757 cbfstool: Prevent file name to be corrupted by basename().
Calling basename(3) may modify content. We should allocate another buffer to
prevent corrupting input buffer (full file path names).

Change-Id: Ib4827f887542596feef16e7829b00444220b9922
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2203
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-30 03:07:34 +01:00
Hung-Te Lin 657ea6a13d cbfstool: Change "locate" output to prefix "0x".
Currently "cbfstool locate" outputs a hex number without "0x" prefix.
This makes extra step (prefix 0x, and then generate another temp file) in build
process, and may be a problem when we want to allow changing its output format
(ex, using decimal). Adding the "0x" in cbfstool itself should be better.

Change-Id: I639bb8f192a756883c9c4b2d11af6bc166c7811d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2201
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29 06:08:31 +01:00
Hung-Te Lin 4505cebdad cbfstool: Remove unused header files.
cbfs-mk*.c does not work with real files / command line so header files with
file I/O and getopt can be removed.

Change-Id: I9d93152982fd4abdc98017c983dd240b81c965f5
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2200
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29 04:14:43 +01:00
Hung-Te Lin d173962c6e cbfstool: Store global variables into struct.
cbfstool.c uses lots of global variables for command line options and all named
as "rom*". This may be confusing when other global variables also start with
rom, ex:	int size = rom_size + romsize;
(rom_size is from command line and romsize is the size of last loaded ROM image).

If we pack all rom_* into a struct it may be more clear, ex:
	do_something(param.cbfs_name, param.size, &romsize);

Change-Id: I5a298f4d67e712f90e998bcb70f2a68b8c0db6ac
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2195
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-28 19:59:40 +01:00
Anton Kochkov dd678a2e16 msrtool: Decoding for most of Intel Core 2 MSRs
Added bits/bitfields descriptions and decoding values
into intel_core2_later.c file, which describe
MSRs for Intel processors, based on later Core 2
architecture.

Change-Id: If577c8ed944afe34f86944cc03a780fba6b3dbba
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1171
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-28 18:36:33 +01:00
Olivier Langlois 70f39871a9 inteltool: Add support for Atom N455 (0x106c0) in CPU MSRs dump
reference for Atom MSRs are from
Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3C: System Programming Guide, Part 3
Order Number 326019, January 2013, Table 35-4, 35-5

Has been successfully tested on the targeted cpu.

Change-Id: If94279caeab27121c63ec43c258dc962c167ad51
Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2192
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-25 20:09:24 +01:00
Paul Menzel 5e732b8bf0 util/runfw/googlesnow.c: Remove trailing whitespace
$ git stripspace < util/runfw/googlesnow.c > /tmp/bla
    $ mv /tmp/bla util/runfw/googlesnow.c

Introduced with original commit.

    commit b867281a07
    Author: Ronald G. Minnich <rminnich@gmail.com>
    Date:   Wed Jan 16 11:59:34 2013 -0600

        Utility to run the snow bios in user mode

Change-Id: I146c07a918ef99e8ae3c0dd72cf28fae22312e43
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2183
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-22 19:04:29 +01:00
Ronald G. Minnich b867281a07 Utility to run the snow bios in user mode
This program lets you test run a snow coreboot image in user mode
on a properly equipped arm system (usually an ARM chromebook).
This is a real time saver as you don't have to flash each time.
We've found and fixed some nasty bugs with this one.

Anyway, the instructions on how to use this are in the binary.

Change-Id: Ib555ef51fd7e930905a2ee5cbfda1cc6f068278e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2159
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-19 18:35:31 +01:00
Stefan Reinauer db5b893569 Add more information to the cbfstool print
Show what's in a stage or payload. This will let people better understand
what's in a stage or payload.

Change-Id: If6d9a877b4aedd5cece76774e41f0daadb20c008
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2176
Tested-by: build bot (Jenkins)
2013-01-19 02:19:14 +01:00
Stefan Reinauer 88c4939c1b make crossgcc: compile all required toolchains
The ARMv7 toolchain is now also needed for abuild (at least
if you want to be able to compile ARM images)

Change-Id: If1253203a2198f7dea632ba45540222ba3361932
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2147
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-17 01:56:53 +01:00
David Hendricks 0b23d47ffd armv7: Place reset vector + CBFS header + bootblock dynamically
This replaces hard-coded bootblock offsets using the new scheme.
The assembler will place the initial branch instruction after BL1,
skip 2 aligned chunks, and place the remaining bootblock code after.

It will also leave an anchor string, currently 0xdeadbeef which
cbfstool will find. Once found, cbfstool will place the master CBFS
header at the next aligned offset.

Here is how it looks:

             0x0000 |--------------|
                    |     BL1      |
             0x2000 |--------------|
                    |    branch    |
    0x2000 + align  |--------------|
                    |  CBFS header |
0x2000 + align * 2  |--------------|
                    |   bootblock  |
                    |--------------|

TODO: The option for alignment passed into cbfstool has always been
64. Can we set it to 16 instead?

Change-Id: Icbe817cbd8a37f11990aaf060aab77d2dc113cb1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2148
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17 01:06:43 +01:00
David Hendricks a12eaccc0b use a relative path for #line 3
The current path doesn't make much sense (unless you're Sven)
and may also incur a very long access penalty if /home happens
to be on a network mounted filesystem.

Change-Id: I8cfceb3cf237757ce9ea8f1953bce5a72691838a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2153
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-16 09:58:00 +01:00
Stefan Reinauer d37ab454d4 Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.

See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.

To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.

For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/

Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12 19:09:55 +01:00
David Hendricks 9ad1f56951 armv7: dynamically calculate the branch offset in cbfstool
This tidies up the ARMV7 case when creating cbfs:
- Calculate the offset using the size of the master header and offsets
  rather than using a magic constant.
- Re-order some assignments so things happen in a logical order.

Change-Id: Id9cdbc3389c8bb504fa99436c9771936cc4c1c23
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2125
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 18:01:14 +01:00
Stefan Reinauer c01990789f cbmem utility: Find actual CBMEM area
... without the need for a coreboot table entry for each of them.

Change-Id: I2917710fb9d00c4533d81331a362bf0c40a30353
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2117
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08 20:40:26 +01:00
Stefan Reinauer d7144dcd57 cbmem utility: unify debug output
... and indent it to make output more comprehensible.

Change-Id: If321f3233b31be14b2723175b781e5dd60dd72b6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2116
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08 20:25:21 +01:00
zbao 062730d7cb cbfstool: index is replaced by strchr.
From index(3):
CONFORMING TO 4.3BSD; marked as LEGACY in POSIX.1-2001. POSIX.1-2008
removes the specifications of index() and rindex(), recommending
strchr(3) and strrchr(3) instead.

Change-Id: I3899b9ca9196dbbf2d147a38dacd7e742a3873fe
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2112
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-08 04:00:30 +01:00
Stefan Reinauer 19f8756f00 cbmem utility: Add option to dump cbmem console
This adds an option to the cbmem utility to dump the cbmem console.
To keep the utility backwards compatible, specifying -c disables
printing of time stamps. To print both console and time stamps, run
the utility with -ct

Change-Id: Idd2dbf32c3c44f857c2f41e6c817c5ab13155d6f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2114
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2013-01-08 01:24:11 +01:00
Stefan Reinauer 1665bb3896 cbmem utility: drop obsolete python based implementation
The first version of the cbmem utility was written in python,
but it had issues with 64bit systems and other little hick ups.
Since the C version has much fewer dependencies (no python needed
on target system), and it works in all corner cases, drop the
python version.

Change-Id: Ida3d6c9bb46f6d826f45538e4ceaa4fc1e771ff5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2115
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-08 00:04:33 +01:00
Stefan Reinauer 9da7570b07 cbfstool: Fix warnings on OS X
Most hton and noth functions are already available
through the system headers we include on OS X, causing
the compiler to warn about duplicate definitions.

Change-Id: Id81852dfc028cf0c48155048c54d431436889c0e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2106
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-04 23:29:37 +01:00
Stefan Reinauer 05cbce672e cbmem utility: Use mmap instead of fseek/fread
The kernel on Ubuntu 12.04LTS does not allow to use
fseek/fread to read the coreboot table at the end of
memory but will instead abort cbmem with a "Bad Address"
error.

Whether that is a security feature (some variation of
CONFIG_STRICT_DEVMEM) or a kernel bug is not  yet clear,
however using mmap works nicely.

Change-Id: I796b4cd2096fcdcc65c1361ba990cd467f13877e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2097
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-01-04 06:37:59 +01:00
Hung-Te Lin 086842a13e Change "VERSION*" to more determined name "CBFS_HEADER_VERSION*".
The 'VERSION' in CBFS header file is confusing and may conflict when being used
in libpayload.

Change-Id: I24cce0cd73540e38d96f222df0a65414b16f6260
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2098
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-04 06:27:33 +01:00
David Hendricks 10c90d3126 update CFLAGS for armv7
This updates $CFLAGS used for armv7. Most of them were just added
to be consistent with what u-boot does. The important ones here
are -march=armv7-a and -mthumb (to allow 16-bit Thumb instructions).

I removed the hard float support because it got errors and
coreboot should never use floats anyway. We're still having trouble
with enums but I want to see how far it gets with this patch.

Also, put the flags in a form that makes diffs easier to read. It's
almost impossible otherwise.

Finally, move some flags to the architecture Makefile, and
rely on the fact that some are set for all architectures.

Depends-On: I6f730d017391f9ec4401cdfd34931c869df10a9e
Change-Id: Ia8a1ae22959933e06f7b996d1832cea40819f1ff
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2075
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-04 00:48:49 +01:00
David Hendricks 454856b274 add user-specified offset when creating armv7 cbfs image
The "offs" provided on the command-line was not taken into account
when creating an image for armv7...

Change-Id: I1781bd636f60c00581f3bd1d54506f0f50bb8ad0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2092
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03 06:45:25 +01:00
Stefan Reinauer 1e0e55615f cbmem utility: support command line options
The tool could print much more useful information than
just time stamps, for example the cbmem console on systems
that don't have a kernel patched to support /sys/firmware/log.

Hence, add command line option parsing to make adding such
features easier in the future.

Change-Id: Ib2b2584970f8a4e4187da803fcc5a95469f23a6a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2091
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-03 01:09:50 +01:00
David Hendricks ceb82da99f add a return type to test function used by xcompile
This fixes a minor bug that could cause testcc to fail unexpectedly.

Change-Id: Ib75d343104b6937682c05acf5232596aac83f105
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2068
Tested-by: build bot (Jenkins)
2012-12-21 20:18:31 +01:00
Zheng Bao a182cbdd62 cbfstool: Align the column of build hint message.
Change-Id: Ic217450411d7fa4e6c3a053be62d7c948dc7145e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2030
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-14 08:46:26 +01:00
Stefan Reinauer cf5aaaf1d2 cbfstool: Catch failing parse_elf_to_payload()
Otherwise cbfstool will segfault if you try to add an x86
payload to an ARM image.

Change-Id: Ie468005ce9325a4f17c4f206c59f48e39d9338df
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2028
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12 06:05:39 +01:00
Stefan Reinauer 1224626e3b Revert "armv7: use __cpu_to_le32 for endianness of reset vector instruction"
This reverts commit 67ce04ea9a

Change-Id: I2781c9275c03bcabf0211e1b6cd1aa8f13005ae0
Reviewed-on: http://review.coreboot.org/2014
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-09 00:00:30 +01:00
Patrick Georgi 198d23c119 crossgcc: Normalize library directories
Various of the build scripts used upstream can't cope with
multilib library paths (eg. lib64), so move things to a place
where they can find them, if such paths are used.

Change-Id: I0dd9bba9a9eadd92d8704157e868fb37c715ee91
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2013
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 08:26:06 +01:00
Stefan Reinauer 10099070ca abuild: Select correct cross compiler for ARMV7 architecture
Change-Id: Ia0dce25a4271299757654ba46baafe6a6673c6d2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2000
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2012-12-08 01:22:17 +01:00
Stefan Reinauer 16bd789a73 buildgcc: Clean up PATH handling
This puts our installed binaries first in the search path, which is what we
really want.

... and remove some dead code
Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I91725af6b0fc486bd943d8e25cdce8d3e2503b3c
Reviewed-on: http://review.coreboot.org/1998
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-08 00:45:09 +01:00
Stefan Reinauer a348d901c7 buildgcc: drop hack to build gcc trunk versions
The focus of the script is to create a supported cross toolchain,
and with GOLD and LTO being released features, we don't need this
anymore.

Change-Id: Ieb7752ce6e143d93414aba5887190f853cbd5a4b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1997
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-08 00:45:03 +01:00
Patrick Georgi 969cd931f8 buildgcc: Remove mingw32 hacks
After patching them to be more flexible, an even better approach was found:
With this change libgcc isn't built at all on mingw32 platforms, so the
system headers aren't necessary anymore.

Now x86_64-pc-mingw32 builds, too.

Change-Id: Ic1406588669d87aee1bcf40ff67af77f2a6ac283
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1985
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Raymond Danks <ray.danks@se-eng.com>
2012-12-07 23:44:47 +01:00
Stefan Reinauer 17b24d3fef abuild: produce valid junit files
If no valid cross compiler is found, the junit file produced
by abuild is invalid, missing the closing </testcase> tag.
This breaks proper reporting in Jenkins of our ARM board at
this moment.

Change-Id: I94bfc7f334d33ceeb53451a7c5125058c1f33bd4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1992
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2012-12-07 22:33:16 +01:00
David Hendricks 67ce04ea9a armv7: use __cpu_to_le32 for endianness of reset vector instruction
Change-Id: Ic8f35d7172f6afa933c24774177ed65e6dc579a0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1979
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-07 07:48:18 +01:00
Patrick Georgi fecd26f208 crossgcc: Generalize matching for the mingw case
With this change, i686-pc-mingw32 is acceptable, too.

Change-Id: I924f7ece84e77dc751e5e0318bac1ebc72d39d21
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1972
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-06 23:18:55 +01:00
Stefan Reinauer cb0895470e Fix xcompile (again)
After cherry-picking change 1679 it became apparent that there was a small
typo in my last xcompile change. With this patch applied, I can now compile
the first few files in the tree before GCC dies with

In file included from src/arch/armv7/lib/romstage_console.c:23:0:
src/include/uart.h:31:6: error: redundant redeclaration of 'uart_init' [-Werror=redundant-decls]

Now for some fun...

Change-Id: Idbb07f609e4a240238964cc16714639f5ef09914
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1970
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-06 04:48:51 +01:00
Stefan Reinauer e42133f33e Fix xcompile for ARMv7 and our cross toolchain
The naming of architectures is highly inconsistent between
the different components of the toolchain. In binutils, the
file architecture is elf32-littlearch. In GCC it's armv7a-eabi.
This patch adds support for different BFD / GCC names

Change-Id: Ib644f71e8d8b4964adec73eed23921d3838e8aa7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1969
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-06 02:35:07 +01:00
Stefan Reinauer 4266b92db0 crossgcc: Fix buildgcc on Mac OS X
Once again, the compiler we use on Mac OS X had trouble compiling GCC.
Switch to llvm-gcc because that one works with Xcode 4.5.2 and gcc 4.7.2.
Also drop the -W flags not known to Xcode from the iasl Makefile, and
drop the --remove-destination option from the copy, because that does not
exist on Darwin.

Change-Id: I9f978f65b5ae7edee2ecdcab337772e7a692bd9b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1967
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06 02:01:42 +01:00
Stefan Reinauer dab4238d10 crossgcc: Add support for building armv7a toolchain
!#%$@ autotools don't support all the platforms gcc and binutils
support. If you try to update to the latest autoconf, it will complain
that you have to use the older one. If I had a penny for every time
autotools broke portability...

Change-Id: I479b6c5f64f1def8dca889884e6a2b0e2ffc1fb8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1966
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-05 01:54:13 +01:00
Stefan Reinauer 8d7115560d Rename devices -> device
to match src/include/device

Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1960
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30 23:59:58 +01:00
Stefan Reinauer 0a9775941d cbfstool: Clean up messages
The output of cbfstool is a little inconsistent in some places.
This patch fixes it.

Change-Id: Ieb643cb769ebfa2a307bd286ae2c46f75ac5e1c1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1955
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30 21:32:02 +01:00
David Hendricks 90ca3b6bd7 Add multi-architecture support to cbfstool
This is an initial re-factoring of CBFS code to enable multiple
architectures. To achieve a clean solution, an additional field
describing the architecture has to be added to the master header.
Hence we also increase the version number in the master header.

Change-Id: Icda681673221f8c27efbc46f16c2c5682b16a265
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1944
Tested-by: build bot (Jenkins)
2012-11-30 00:42:31 +01:00
Zheng Bao 6d1fcd5e0b crossgcc: Only build iasl in acpica.
Other acpica's modules are not needed.

Change-Id: I16846caa922aded8db7c1d9e64c007fb2772ff98
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2012-11-29 12:10:28 +01:00
Kyösti Mälkki e773c92ef4 Make mainboard_ops and mainboard.c file optional
This provides weak empty declaration for mainboard_ops.
The struct chip_operations is not defined for __PRE_RAM__ so
the declaration is also moved upwards in the output.

Change-Id: I101f0b8b9f0a55fb51a7c6475d53cc588c84026d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1931
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29 10:25:13 +01:00
Patrick Georgi f33e395213 build system: Split linking into multiple steps
After collecting dependencies for ramstage, add an intermediate step
in which object files are linked per directory. The results are then
linked into the final binary.

This reduces the maximum command line length and might also help with
future use of LTO linking.

Also adapt the lint test for build dir handling, since printall
doesn't provide individual object files for ramstage anymore.

Change-Id: Ie40febd8c1eaf4609944eedeab46d870639e53df
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 22:02:02 +01:00
Patrick Georgi b6f765e7c8 Provide weak empty declarations of all chip_ops used on a board
sconfig creates empty defaults for all chip_ops, which can be overridden
by drivers simply by providing a concrete implementation.

Change-Id: Ib37515f0b0747bdbf4da780d28690a1e719944b2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1567
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 21:48:22 +01:00
Patrick Georgi 1a5301dd33 abuild: only rebuild boards if requested or after a broken build
That used to be the behaviour, and it's quite useful to incrementally
fix bugs across the tree.

Change-Id: I3e30cbdcf01631bc29f892054caa3babb0969beb
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1888
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 10:07:54 +01:00
Zheng Bao 536b53ea6d xcompile: Add missing XGCCPATH
XGCCPATH is missing in new xcompile.

Change-Id: I177f54189be445404a4a61419064d3c414b8a30c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1921
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27 09:22:10 +01:00
Ronald G. Minnich e820e5cb3a Make xcompile support multiple architectures
With this change the the xcompile script now creates environment variables
for more than one architecture.

Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Change-Id: I349a1fd1d865ef16979f1dfd6aeca12b1ee2eed6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1915
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-11-27 02:06:07 +01:00
Idwer Vollering 6b11c8be45 crossgcc: update to acpica-20121114
Update acpica to release 20121114 and
update patches/ to build with this version of acpica.
Correct the creation of crossgcc-build.log
Bump CROSSGCC_VERSION.

Change-Id: I269454ebc3c78b5852e4a67e55bb5642edad191d
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1861
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24 08:54:53 +01:00
Patrick Georgi 0a3f2393ae crossgcc: properly test for flex
This is no GNU tool, so testing for "GNU" in the version string
is bound to fail.
We now accept everything that returns success on "flex --version"
and then hope for the best.

I tested both cases

Change-Id: If325f613fde1648847b998b7e8e5782d0f22b484
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1884
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-22 08:08:48 +01:00
Kyösti Mälkki 1a2a6eebc5 Cleanup sconfig
Fix side-effects of name translation, treat original name as const.

Change-Id: Iae26be8cefe7db11eeb8e62fce6f3b8bc9c1f4ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/799
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-17 02:12:32 +01:00
Stefan Reinauer 17b77ab6aa buildgcc: Print error if flex is missing
flex is needed by acpica. This patch makes the build fail early
instead of after gcc has been compiled, if flex is not there.

Change-Id: Idfd71bdf704ab25de655f1a72c266c5220b15048
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1860
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16 18:08:06 +01:00
Zheng Bao f6659cac3b nvramtool: fsync for mingw.
Change-Id: Ifdec69ca46ba8cbd3eb154d8f4af4b3cafa8019d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1805
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-14 09:24:56 +01:00
Stefan Reinauer 632175802e cbfstool: Rework to use getopt style parameters
- Adding more and more optional and non-optional parameters
  bloated cbfstool and made the code hard to read with a lot
  of parsing in the actual cbfs handling functions. This change
  switches over to use getopt style options for everything but
  command and cbfs file name.
- This allows us to simplify the coreboot Makefiles a bit
- Also, add guards to include files
- Fix some 80+ character lines
- Add more detailed error reporting
- Free memory we're allocating

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ia9137942deb8d26bbb30068e6de72466afe9b0a7
Reviewed-on: http://review.coreboot.org/1800
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 18:38:03 +01:00
Stefan Reinauer 2e200cde9a cbfstool: Update LZMA encoder to LZMA SDK 9.12
This removes almost all C++ code (except the wrapper)

Change-Id: I0f84070e3b6dc57c98d49a53150a140479b3221f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1799
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 18:35:52 +01:00
Vadim Bendebury 7c6b6bb593 cbmem compilation needs to use the hardened toolchain
The appropriate compiler (provided by the build system) is used to
ensure proper toolchain options are used.

cbmem.c is being modified to suppress pointer to integer typecast
warnings.

Change-Id: Ibab2faacbd7bdfcf617ce9ea4296ebe7d7b64562
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1791
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 17:12:23 +01:00
Stefan Reinauer 4a17d29fe8 ifdtool: Dump more registers from FD
Only thing not decoded now are the PCH straps

ifdtool -d path/to/image.bin
File path/to/image.bin is 4096 bytes
Found Flash Descriptor signature at 0x00000010
FLMAP0:    0x02040003
  NR:      2
  FRBA:    0x40
  NC:      1
  FCBA:    0x30
FLMAP1:    0x12100206
  ISL:     0x12
  FPSBA:   0x100
  NM:      2
  FMBA:    0x60
FLMAP2:    0x00210120
  PSL:     0x2101
  FMSBA:   0x200
FLUMAP1:   0x000004df
  Intel ME VSCC Table Length (VTL):        4
  Intel ME VSCC Table Base Address (VTBA): 0x000df0

ME VSCC table:
  JID0:  0x001740ef
    SPI Componend Device ID 1:          0x17
    SPI Componend Device ID 0:          0x40
    SPI Componend Vendor ID:            0xef
  VSCC0: 0x20052005
    Lower Erase Opcode:                 0x20
    Lower Write Enable on Write Status: 0x50
    Lower Write Status Required:        No
    Lower Write Granularity:            64 bytes
    Lower Block / Sector Erase Size:    4KB
    Upper Erase Opcode:                 0x20
    Upper Write Enable on Write Status: 0x50
    Upper Write Status Required:        No
    Upper Write Granularity:            64 bytes
    Upper Block / Sector Erase Size:    4KB
  JID1:  0x001720c2
    SPI Componend Device ID 1:          0x17
    SPI Componend Device ID 0:          0x20
    SPI Componend Vendor ID:            0xc2
  VSCC1: 0x20052005
    Lower Erase Opcode:                 0x20
    Lower Write Enable on Write Status: 0x50
    Lower Write Status Required:        No
    Lower Write Granularity:            64 bytes
    Lower Block / Sector Erase Size:    4KB
    Upper Erase Opcode:                 0x20
    Upper Write Enable on Write Status: 0x50
    Upper Write Status Required:        No
    Upper Write Granularity:            64 bytes
    Upper Block / Sector Erase Size:    4KB

OEM Section:
00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

Found Region Section
FLREG0:    0x00000000
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1:    0x07ff0180
  Flash Region 1 (BIOS): 00180000 - 007fffff
FLREG2:    0x017f0001
  Flash Region 2 (Intel ME): 00001000 - 0017ffff
FLREG3:    0x00001fff
  Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
FLREG4:    0x00001fff
  Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)

Found Component Section
FLCOMP     0x64900024
  Dual Output Fast Read Support:       supported
  Read ID/Read Status Clock Frequency: 50MHz
  Write/Erase Clock Frequency:         50MHz
  Fast Read Clock Frequency:           50MHz
  Fast Read Support:                   supported
  Read Clock Frequency:                20MHz
  Component 2 Density:                 8MB
  Component 1 Density:                 8MB
FLILL      0x000060c7
  Invalid Instruction 3: 0x00
  Invalid Instruction 2: 0x00
  Invalid Instruction 1: 0x60
  Invalid Instruction 0: 0xc7
FLPB       0x00000000
  Flash Partition Boundary Address: 0x000000

Found PCH Strap Section
PCHSTRP0:  0x0820d602
PCHSTRP1:  0x0000010f
PCHSTRP2:  0x00560000
PCHSTRP3:  0x00000000
PCHSTRP4:  0x00c8e000
PCHSTRP5:  0x00000000
PCHSTRP6:  0x00000000
PCHSTRP7:  0xc0001ae0
PCHSTRP8:  0x00000000
PCHSTRP9:  0x30000580
PCHSTRP10: 0x00410044
PCHSTRP11: 0x99000097
PCHSTRP12: 0x00000000
PCHSTRP13: 0x00000000
PCHSTRP14: 0x00000000
PCHSTRP15: 0x0000033e
PCHSTRP16: 0x00000000
PCHSTRP17: 0x00000002

Found Master Section
FLMSTR1:   0x0a0b0000 (Host CPU/BIOS)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      disabled
  Host CPU/BIOS Region Write Access: enabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       disabled
  Host CPU/BIOS Region Read Access:  enabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000

FLMSTR2:   0x0c0d0000 (Intel ME)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      enabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       enabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000

FLMSTR3:   0x08080118 (GbE)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      disabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       disabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      disabled
  Requester ID:                      0x0118

Found Processor Strap Section
????:      0x00000000
????:      0xffffffff
????:      0xffffffff
????:      0xffffffff

Change-Id: I68a613df2fd80e097cdea46fbad104d7c73ac9ad
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1756
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-12 06:56:03 +01:00
Vadim Bendebury 6d18fd09c3 Utility to dump boot timing table
Coreboot and u-boot create a table of timestamps which allows to see
the boot process performance. The util/cbmem/cbmem.py script allows to
access the table after ChromeOS boots up and display its contents on
the console. The problem is that shipping images do not include Python
interpreter, so there is no way to access the table on a production
machine.

This change introduces a utility which is a Linux app displaying the
timestamp table. Conceivably the output of this utility might be
included in one of the ChromeOS :/system sections, so it was attempted
to write this procedure 'fail safe', namely reporting errors and not
continuing processing if something goes wrong.

Including of coreboot/src .h files will allow to keep the firmware
timestamp implementation and this utility in sync in the future.

Test:
    . build the utility (run 'make' while in chroot in  util/cbmem)
    . copy `cbmem' and 'cbmem.py' to the target
    . run both utilities (limiting cbmem.py output to 25 lines or so)
    . observe that the generated tables are identical (modulo rounding
      up of int division, resulting in 1 ns discrepancies in some
      cases)

      localhost var # ./cbmem
      18 entries total:

         1:62,080
         2:64,569 (2,489)
         3:82,520 (17,951)
         4:82,695 (174)
         8:84,384 (1,688)
         9:131,731 (47,347)
        10:131,821 (89)
        30:131,849 (27)
        40:132,618 (769)
        50:134,594 (1,975)
        60:134,729 (134)
        70:363,440 (228,710)
        75:363,453 (13)
        80:368,165 (4,711)
        90:370,018 (1,852)
        99:488,217 (118,199)
      1000:491,324 (3,107)
      1100:760,475 (269,150)

      localhost var # ./cbmem.py | head -25

      time base 4249800, total entries 18
      1:62,080
      2:64,569  (2,489)
      3:82,520  (17,951)
      4:82,695  (174)
      8:84,384  (1,688)
      9:131,731  (47,347)
      10:131,821  (89)
      30:131,849  (27)
      40:132,618  (769)
      50:134,594  (1,975)
      60:134,729  (134)
      70:363,440  (228,710)
      75:363,453  (13)
      80:368,165  (4,711)
      90:370,018  (1,852)
      99:488,217  (118,199)
      1000:491,324  (3,107)
      1100:760,475  (269,150)

Change-Id: I013e594d4afe323106d88e7938dd40b17760621c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12 03:35:20 +01:00
Stefan Reinauer cb6fd30155 cbfstool: Remove unused cmd_t
Change-Id: Ib1c05828258b9dc7107920ae6cb25bc92ffa86d1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1795
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12 03:26:08 +01:00
Stefan Reinauer 20848ee288 cbfstool: add add-flat-binary command to add raw executables
Example:
cbfstool image-link.bin add-flat-binary u-boot.bin fallback/payload \
	0x100000 0x100020
will add u-boot.bin as fallback/payload with a load address of 0x100000
and an entry-point of 0x10002.

Change-Id: I6cd04a65eee9f66162f822e168b0e96dbf75a2a7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12 03:25:50 +01:00
Stefan Reinauer 3c53d33c78 ifdtool: Add locking/unlocking and dumping of access permissions
ifdtool will now dump access permissions of system comonents to
certain IFD sections:

Found Master Section
FLMSTR1:   0xffff0000 (Host CPU/BIOS)
  Platform Data Region Write Access: enabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      enabled
  Host CPU/BIOS Region Write Access: enabled
  Flash Descriptor Write Access:     enabled
  Platform Data Region Read Access:  enabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       enabled
  Host CPU/BIOS Region Read Access:  enabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000

FLMSTR2:   0x0c0d0000 (Intel ME)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      enabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       enabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000

FLMSTR3:   0x08080118 (GbE)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      disabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       disabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      disabled
  Requester ID:                      0x0118

Also, ifdtool -u /path/to/image will unlock the host's
access to the firmware descriptor and ME region.
ifdtool -l /path/to/image will lock down the host's
access to the firmware descriptor and ME region.

Change-Id: I3e081b80a9bcb398772416f143b794bf307b1c36
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1755
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-11-09 18:59:42 +01:00
Stefan Reinauer 7a12a32670 Fix abuild output in Jenkins
Ignore the harmless broken pipe messages from "yes"

Building amd/pistachio; i386: ok, using i386-elf-gcc
Using payload /srv/jenkins/payloads/seabios/bios.bin.elf
  Creating config file... (blobs, ccache) yes: standard output: Broken pipe
yes: write error
ok;  Compiling image on 4 cpus in parallel .. ok. (took 10s)

Change-Id: Ic53e246aac3ab6d7ea7a006a8dfac1c3f85797bc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1813
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09 07:05:18 +01:00
Stefan Reinauer 5e93b37310 Fix Segmentation Fault in ifdtool
If a section is bigger than the FD file it is injected into, and the FD
lies about the size of the FD file, ifdtool would crash because reading
in the section writes beyound the FD file in memory.

Change-Id: Idcfac2b1e2b5907fad34799e44a8abfd89190fcc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1754
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09 02:07:08 +01:00
Vadim Bendebury d0b860aada Add utility for parsing/modifying DTD array
Detailed timing descriptor (DTD) is an 18 byte array describing video
mode (screen resolution, display properties, etc.) in Intel Option
ROM. Option ROM can support multiple video modes, specific mode is
picked by the BIOS through the appropriate Option ROM callback
function.

The new utility allows to interpret the 18 byte hex DTD dump, and/or
modify certain values, and generate a new DTD.

To parse the DTD contents just pass the 18 bytes to the utility in the
command line. To modify the existing contents and generate a new dump
precede the 18 bytes with '-m' and follow prompts.

Change-Id: Ib00bdaf42c350b98b5a48d08e6bb347b5ec25a8b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08 20:21:19 +01:00
Vadim Bendebury 00ba25decb Get more informative output from cbmem.py
This is a cosmetic change which formats timestamp information
retrieved by cbmem.py.

Instead of printing timestamps in a single line, print them one per
line and add time (in us) elapsed since the previous timestamp.

     time base 4149594, total entries 18
     1:56,928
     2:58,851  (1,923)
     3:175,230  (116,378)
     4:175,340  (109)
     8:177,199  (1,859)
     9:214,368  (37,168)
     10:214,450  (81)
     30:214,462  (11)
     40:215,205  (743)
     50:217,180  (1,974)
     60:217,312  (132)
     70:436,984  (219,671)
     75:436,993  (8)
     80:441,424  (4,431)
     90:442,487  (1,062)
     99:553,777  (111,289)
     1000:556,513  (2,736)
     1100:824,621  (268,107)

Change-Id: I0d25cafe766c10377017697e6b206276e1a92992
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1716
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08 19:39:06 +01:00
Vadim Bendebury f27d36c361 Fix cbmem to work on 64 bit platforms
For some reason which I fail to understand, specifying endiannes using
'@' (which means 'native' and should be the same as '<' on x86
platforms) causes cbmem.py to crash the machine on 64 bit systems.

What happens is that the addresses read from various table headers'
struct representations do not make sense, when bogus address gets
passed to get_phys_mem, the crash happens while that function is
executed.

dlaurie@ found out that replacing "@" with "<" in fact fixes the
issue. After some investigation I am just submitting this fix without
much understanding of the root cause.

Change-Id: Iaba9bc72a3f6b1d0407a5f1e3b459ccf5063969d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1715
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08 19:38:59 +01:00
Stefan Reinauer a90bd527d9 cbfstool: add offset parameter to create command
CBFS allows coreboot rom images that are only partially covered
by the filesystem itself. The intention of this feature was to
allow EC / ME / IMC firmware to be inserted easily at the beginning
of the image. However, this was never implemented in cbfstool.

This patch implements an additional parameter for cbfstool.

If you call cbfstool like this:
cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000
it will now create an 8M image with CBFS covering the last 1M of
that image.

Test:
     cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000
     creates an 8M image that is 7M of 0xff and 1M of CBFS.

Change-Id: I5c016b4bf32433f160b43f4df2dd768276f4c70b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1708
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08 19:38:26 +01:00
Stefan Reinauer 746d174347 cbfstool: respect dependencies when building locally
cbfstool was not looking at any dependencies when building
by running make in util/cbfstool. By fixing this it's not
required to make clean every time you edit a file in there.

Change-Id: I544fd54d4b9dd3b277996c21ade56dc086b84800
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1707
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2012-11-07 18:29:18 +01:00
Kyösti Mälkki a93c3fe7f0 Drop redundant CHIP_NAME in mainboard.c
Compose the name from Kconfig strings instead.

As the field is for debug print use only, a minor change in the output
should do no harm. The strings no longer include word "Mainboard".

Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1635
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06 21:59:21 +01:00
Idwer Vollering 336db54a00 crossgcc: build expat and python in silence
Don't let expat and/or python show the compile process on stdout.
Instead direct this output to crossgcc-build.log.

Fix the logfile path for python.

Change-Id: I431dabf6955d7eef3e54c96d0fb11b92d1cee96d
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1667
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02 20:08:01 +01:00
Nico Huber aa5eae629f inteltool: Add output of 64bit registers in PMBASE
Output values of 64bit registers and fix settings for GPE0_EN for
ICH9/10.

Change-Id: I8ca6b32500331707670972b38466345f581844cd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27 02:54:23 +02:00
Idwer Vollering 573d37da02 crossgcc: update to Python 2.7.3
Change-Id: I9db10e8c7dcd693cc4ab935c587da02dd7eb2bc5
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1621
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-27 02:32:11 +02:00
Idwer Vollering 296a015b8a crossgcc: update to expat 2.1.0
Change-Id: Id0b736d402b33138e27b18c74e5ed8ffab0bcccb
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/1620
Tested-by: build bot (Jenkins)
2012-10-27 02:31:58 +02:00
Idwer Vollering cd02793dff crossgcc: update mingw w32api's download URL
Correct the download URL of mingw's w32api.

Change-Id: I98fb43c121399c23f6693ade5cd3b42bc9463724
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1619
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-26 13:03:16 +02:00
Zheng Bao 04ceed6a0f buildgcc: redirect error output to /dev/null
Change-Id: I7cd63248eb8abb711cecce41e3f8a282b34aa126
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1548
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-26 12:51:15 +02:00
Idwer Vollering 908b043da0 crossgcc: update to mingwrt 3.20-2
This patch updates crossgcc to download and compile mingwrt 3.20-2

Change-Id: Ic5ed2df4c3643e469a62c51643d3fc756eb3e615
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1617
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-10-26 01:58:52 +02:00
Idwer Vollering 655a65c139 crossgcc: update to binutils 2.23
This patch updates crossgcc to download and compile binutils 2.23

Change-Id: I75a24ce6fb9f6ac7ae53671314c410b9b0d80aa8
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1615
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 09:24:26 +02:00
Idwer Vollering 7962fc7684 crossgcc: update to MPC 1.0.1
This patch updates crossgcc to download and compile MPC 1.0.1

Change-Id: I7a2a21afc8c26e4fb7b6553c7fd98cc054d01570
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1614
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 09:23:21 +02:00
Idwer Vollering 27efb4cd3f crossgcc: update to MPFR 3.1.1
This patch updates crossgcc to download and compile MPFR 3.1.1

Change-Id: I6c479db5d6d632dcc2201c3771b43e2b663877e1
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1613
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 09:21:51 +02:00
Idwer Vollering fedb63a988 crossgcc: update to GDB 7.5
This patch updates crossgcc to download and build GDB 7.5

Change-Id: I38fc3591396f072ead399b22f516ec765480ea40
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1612
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 09:20:04 +02:00
Idwer Vollering 1cfee0bc10 crossgcc: update to gcc 4.7.2
Update crossgcc to use gcc 4.7.2.
This requires a minor change to util/crossgcc/buildgcc as well.

Tested on hardware with asus/p2b and lenovo/x60.

Change-Id: Ia3921844670ca99741e5715def14dd969f305ab7
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1609
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 06:27:39 +02:00
Idwer Vollering cbd631284d crossgcc: fix compilation of acpica
Compilation of acpica-20120420 is broken (and old, but I'll take care
of that in a future patch),
let's fix that ("Building IASL 20120420 ... failed").

Change-Id: If5fd5cd93d748f78b7c059323f9f810666e32cc7
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/1607
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-25 06:27:17 +02:00
Zheng Bao def50b061d kconfig: Some terms or curses libraries treat backspace as 0x08
Change-Id: Ie4e4a2f0d68643a8f46d24ee7bd1b953e9fe14a5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1605
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-23 05:05:53 +02:00
Zheng Bao 545167252d build: build coreboot on mingw.
regex, pdcurses, wsock(for itohl) are seperated libraries. mmap and unmmap are
ported from git.

Issues:
1. The length of command line is limited. That makes the Thather can not be built
  because too many obj.o need to be built.

Change-Id: I1d60ec5c7720c1e712e246c4cd12e4b718fed05f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-22 21:49:54 +02:00
Zheng Bao c31cdd8662 cbfstool: Add -mno-ms-bitfields on (mingw)
The default gcc on mingw will process the __attribute__ ((packed)) in
a different way other than non-win system.

Change-Id: Iac9f4476c922472d0b447f1c3ef60e8e13bd902f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1603
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-22 21:49:46 +02:00
Stefan Tauner fba86bfaa8 inteltool: improve the libpci test in the Makefile
Use the verbatim variable method to define and export test code and
the actual libpci test from flashrom. This improves readability and
will work with stricter compiler (settings).

Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1575
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-19 19:32:24 +02:00
Stefan Tauner 1a00cf0632 inteltool: add support for 946GZ and 946PL
Change-Id: Ied0ff16c16d8c2f04b55fe6b0a6ee38966d3c424
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1576
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-19 10:27:53 +02:00
Stefan Tauner 04c06005eb inteltool: new definitions and cleanup
- Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[].
 - Refine some names and macros.
 - Clean up some whitespace errors.

 - Add IDs and names of 5, 6 and 7 Series southbridges and the three
   latest Core CPU families with integrated memory controllers but do
   not implement any pretty printing routines for them yet.

   The first generation Core family is already supported, although it
   was wrongly named after the PCH and used the wrong ID. Also, the BAR
   values have been mangled to 32b instead of 64b. Both errors have been
   fixed and most basic support for the other two generations was added.

Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1574
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-19 09:57:51 +02:00
Stefan Tauner f450b8619e inteltool: remove bashism from Makefile
&> is a bashism to redirect both outward streams (stdout and stderr), but
with other shells this introduces a race condition with the rm command
after it, because the compiler execution is done in the background/
in parallel. Found and tested with dash.

Change-Id: I08516494828c9f7af168f954f2df027372657867
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1573
Tested-by: build bot (Jenkins)
Reviewed-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-14 22:22:59 +02:00
Zheng Bao 36156ffa1e crossgcc: Allow the non-gnu tar and patch work on XxxBSD
For BSD, patch and tar are not default GNU. Add a work around
to let the non-gun patch and tar work.

Change-Id: I0a9d0bb0e535aa5e0dde146db330c3c8d7b4d8cb
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-14 20:15:46 +02:00
Patrick Georgi c31e3ac258 abuild: allow building with no payload
Change-Id: I167f0bb57bb40f0426182c0abe868bdad58eb120
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1563
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-14 20:10:15 +02:00
Kyösti Mälkki aada2e127b Every chip must have chip_operations
Forcing this rule, chip_ops can be added in the static devicetree
regardless of the existence of the chip.h files.

Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1472
Tested-by: build bot (Jenkins)
2012-10-08 13:24:31 +02:00
Zheng Bao 9b757dccdc lint: Get absolute path in compare_output
The classes in $(top)/Makefile uses $(abspath) to get the path.
The $(abspath) can not resolve symlink. If the coreboot is located
in a symlink directory, the run_printall produces the absolute
path while the $PWD just produces the path with symlink. Use
`pwd -P` to get the abs path.

Change-Id: Icf6b364d030c14a9c78991767b17dafc701baf3c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1551
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-05 22:06:04 +02:00
Zheng Bao 684b8ab309 lint: Stop searching when one GNUmake is found
After make 3.81 is copied to /usr/local/bin, the old make 3.80, which
doesn't work for coreboot, will replace $MAKE with gnumake. That is not
we want.

Change-Id: I87fbe95c70228a22f2c233ff071df29639b63726
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1550
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-04 11:02:02 +02:00
Andriy Gapon 89397fc342 superiotool: Fix for FreeBSD
Makefile still used SVNDEF on FreeBSD.

Change-Id: I45c7fbc66c33e82a2146ef7df87b63bc7edea4cd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1554
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-03 09:26:59 +02:00
Zheng Bao b13e94c2c6 nvramtool: uname in NetBSD doesnt take "-o"
see the Netbsd manual:
http://netbsd.gw.com/cgi-bin/man-cgi?uname++NetBSD-current
Error output needs to be redirected.

Change-Id: I1853a0162e14be0ee9d7971466499af6c72b2427
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1545
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-28 14:50:02 +02:00
Zheng Bao 82c06bd2d5 nvramtool: Require no hw access for integrated Makefile
The Makefile.inc is integraged into coreboot Makefile. It doesn't
need to access to HW like cmos. It doesn't include cmos-hw-unix.c,
which is only for individual tools running seperatedly.

Change-Id: Ib00b5c3da63acb4120cb23eb7d661c5bc75d7c86
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1544
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-28 14:49:21 +02:00
Zheng Bao 533bca80ed lint: Add template for mktemp to meet BSD requirements
Change-Id: I86cecf6aee1fcb682cb32bd0f03e014fd1afe594
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1549
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-28 14:46:37 +02:00
Patrick Georgi 80d2526c72 abuild: abort if payload.sh failed
With this chance it becomes practical to have payload.sh build/update
the payload, and abort abuild if something bad happened.

Change-Id: Iee25de2e8b62153c477b8e5d32e097b59797523c
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1536
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-09-25 16:08:53 +02:00
Patrick Georgi 5c63761c37 nvramtool: Read/write binary data as binary
Only relevant on windows (and nvramtool currently fails there), but
it doesn't hurt.

Change-Id: I5d6420c1f9dc49cf3af31e75088e51a90f729e01
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1535
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-09-25 16:08:23 +02:00
Zheng Bao 5b209c0718 crossgcc: Change the term color back (trivial)
Change-Id: I6a7852eef32a3440c9d29e45420cb21d2db8c404
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-20 09:25:46 +02:00
Zheng Bao 615304c667 lint: Dont highlight the matching text in grep
Sometimes we like to make grep auto-highlight the match text by
setting the GREP_OPTIONS. This will make the compare_output
in lint-002 catch the difference between 2 strings which text are
same but color are different. Override the GREP_OPTIONS.

Change-Id: Ia257214fe5149e084e8eac3fb551a494eaa46ae6
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1526
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-17 10:37:21 +02:00
Patrick Georgi b3a18acb56 Isolate Kconfig host compiler options
This reverts commit 645f2dd5d9.

Instead of adding a special case to nvramtool to avoid it
picking up Kconfig's regex.h, have the host compiler only
consider util/kconfig for includes (ie. -Iutil/kconfig)
for kconfig related object files.

Change-Id: Ie4f97ce38cb3e911f6e6c1e5b6f86f6998d93f69
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1509
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-09-14 07:33:07 +02:00
Rudolf Marek 73ab60a9d4 Fix ramstage location in trace scripts
The ramstage location has been changed. Reflect this in the script.

Change-Id: I76c9b38a8ffe2188e94146e845d23536625c0979
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/1504
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-13 10:11:53 +02:00
Zheng Bao 645f2dd5d9 nvramtool: Set build flags for FreeBSD
Set HOSTCFLAGS as nil to make the nvramtool include the regex.h
in system. Otherwise it will include the regex.h in kconfig, which
will cause building error in FreeBSD.

Change-Id: I95292e23e1716da1260842be9597119a4e26c8ed
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1500
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
2012-09-11 10:29:19 +02:00
Zheng Bao 534e61c4e6 nvramtool: Remove the building warning on older gcc
Some older gcc requires the default entry in switch, otherwise
build warning "enumeration value not handled in switch" will come
up.

Change-Id: Ic8ea9960e4aca599e0ea62ec345122c9df57e766
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1501
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-11 08:32:30 +02:00
Stefan Tauner e54995a116 superiotool: Add support for Fintek F81865F/F-I register dump.
Datasheet: http://www.fintek.com.tw/files/productfiles/F81865_V028P.pdf

The code was done by Juha Tuomala <Juha.Tuomala@iki.fi> but he refused
to sign it off, or commit it for review. I'll commit it anyway with my sign-off
because it does not exceed threshold of originality for any copyright.

Change-Id: Id86267f5add539b99229f20bbe339bfb5eb20f8b
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1496
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-09-06 19:51:05 +02:00
Zheng Bao a5de94128b gitconfig: Match the Change-Id line more exactly
Change-Id: I5ac267770bc5b43dd1435e75ab0fcbde0d88b664
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1487
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
2012-08-27 15:41:33 +02:00
zbao 79b0574698 crossgcc: Update GDB patch version to 7.4.1
libgen.h dont have to be included.

Change-Id: I46a6a23a310b20784de956a577f1ab3c7931e34d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1470
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-23 07:02:55 +02:00
Kyösti Mälkki fee73df07a Auto-declare chip_operations
The name is derived directly from the device path.

Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-22 05:06:41 +02:00
zbao 2efabba468 buildgcc: Remove the warning options unsupported by cygwin
My cygwin hostcc doesn't support
-Wempty-body -Waddress -Wmissing-field-initializers

Change-Id: I879e05f3bd396b36b327f204252e820552b6e12e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1426
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-15 08:09:58 +02:00
zbao 844e01357b buildgcc: Update the toolchain patches version
acpica 20120420, acpica-unix-20110922_no_unused_variables.patch is not
used anymore.
binutils 2.22.

Change-Id: I58459bd2eba2ad752fc033e51ee0892e2e069a02
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1424
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-14 15:44:20 +02:00
Stefan Reinauer a675d49408 Fix SMBIOS generation
Dropping mainboard's chip.h broke execution of the mainboard's enable
function and the addition of mainboard specific smbios tables.

The former was fixed by Kyosti in http://review.coreboot.org/1374
This patch fixes the breakage in static.c and also backs out a small
portion of Kyosti's patch (because it's not needed anymore)

Change-Id: I6fdea9cbb8c6041663bd36f68f1cae4b435c1f9b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1421
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-08 11:34:57 +02:00
Stefan Reinauer 57879c9bd1 Make the device tree available in the rom stage
We thought about two ways to do this change. The way we decided to try
was to
1. drop all ops from devices in romstage
2. constify all devices in romstage (make them read-only) so we can
   compile static.c into romstage
3. the device tree "devices" can be used to read configuration from
   the device tree (and nothing else, really)
4. the device tree devices are accessed through struct device * in
   romstage only. device_t stays the typedef to int in romstage
5. Use the same static.c file in ramstage and romstage

We declare structs as follows:
ROMSTAGE_CONST struct bus dev_root_links[];
ROMSTAGE_CONST is const in romstage and empty in ramstage; This
forces all of the device tree into the text area.

So a struct looks like this:
static ROMSTAGE_CONST struct device _dev21 = {
 #ifndef __PRE_RAM__
        .ops = 0,
 #endif
        .bus = &_dev7_links[0],
        .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
        .enabled = 0,
        .on_mainboard = 1,
        .subsystem_vendor = 0x1ae0,
        .subsystem_device = 0xc000,
        .link_list = NULL,
        .sibling = &_dev22,
 #ifndef __PRE_RAM__
        .chip_ops = &southbridge_intel_bd82x6x_ops,
 #endif
        .chip_info = &southbridge_intel_bd82x6x_info_10,
        .next=&_dev22
};

Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1398
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-04 18:05:39 +02:00
Stefan Reinauer 188e3c2ff0 Drop mainboard chip.h
mainboard_config never worked right, at least not since we've had sconfig.
Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that
tried to use it anyways.

Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1359
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26 22:57:35 +02:00
Stefan Reinauer a9f670a760 ifdtool: Use perror for file write errors
The "Error while writing." error messages did not output a new line
which made the output look weird. With this patch, it should look like
this:

$ ifdtool -x 3rdparty/mainboard/google/parrot/descriptor.bin
File 3rdparty/mainboard/google/parrot/descriptor.bin is 4096 bytes
Found Flash Descriptor signature at 0x00000010
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
Flash Region 1 (BIOS): 00200000 - 007fffff
Error while writing: Bad address
Flash Region 2 (Intel ME): 00001000 - 001fffff
Error while writing: Bad address
Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)

Change-Id: I784ff72d0673f167dbf0bd10921406abd685ce72
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1299
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-07-24 10:13:33 +02:00
Anton Kochkov 59b36f1026 msrtool: Factor out cpuid() from target probe functions into main()
Almost all probe functions called cpuid(). Those calls are replaced
by a single cpuid() call in main() and a new parameter to the target
probe functions with the cpuid() result.

The vendor_t and struct cpuid_t definitions are moved closer to the
top of msrtool.h and the vendor_t enum is reformatted to simplify
addition of further values.

Change-Id: Icd615636207499cfa46b8b99bf819ef8ca2d97c0
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/1259
Tested-by: build bot (Jenkins)
2012-07-21 17:35:46 +02:00
Anton Kochkov c7fc4422a0 inteltool: Add support for H65 Express chipset
Added few MCH and DMI registers for H65E.
Description of them can be found at
"2nd Generation Intel Core Processors
Family datasheet"

Change-Id: If4fee35bb5a09b04ea0684be9cbd3c1e9084b934
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1258
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-21 16:06:41 +02:00
Patrick Georgi 116327ee06 sconfig: typo fix
eliminate printf format warning.

Change-Id: I51f75a259d28c5de788f57c3d720b76ca638e330
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1248
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-20 13:11:46 +02:00
Mathias Krause 41c229c029 cbfstool: signed vs. unsigned fixes
Use the right data types to fix compiler warnings.

Change-Id: Id23739421ba9e4a35599355fac9a17300ae4bda9
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/1236
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-07-18 00:15:35 +02:00
Mathias Krause 5c581c4d6c cbfstool: provide a prototype for remove_file_from_cbfs
To complement commit e1bb49e (Add a "remove" command to cbfstool) and
fix a compiler warning provide a prototype for remove_file_from_cbfs.

Change-Id: Ied8eac956de5fed3f9d82ce1e911ee1fec52db15
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/1235
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-07-18 00:15:27 +02:00
Mathias Krause d2567c8d92 cbfstool: make endian detection code more robust
Accessing the memory of a char array through a uint32_t pointer breaks
strict-aliasing rules as it dereferences memory with lower alignment
requirements than the type of the pointer requires. It's no problem on
x86 as the architecture is able to handle unaligned memory access but
other architectures are not.

Fix this by doing the test the other way around -- accessing the first
byte of a uint32_t variable though a uint8_t pointer.

Change-Id: Id340b406597014232741c98a4fd0b7c159f164c2
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/1234
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-07-18 00:15:15 +02:00
Patrick Georgi 2b108a4368 sconfig: fix up shipped code
The lex compile wasn't current (or something) and so INTA wasn't lexed
properly.

Change-Id: I5a760430788792f54c4e1e0d419b8dd525079d15
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1226
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-13 20:27:28 +02:00
Christian Gmeiner 42b808e889 msrtool: add support for cs5536 LPC_SERIRQ (0x5140004e)
This register is helpful for porting new mainboards based on
cs5536 southbridge.

Change-Id: Iff3adc2c2fbc672c8541096756f95b3322f6ab19
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1211
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13 08:40:14 +02:00
Sven Schnelle 0fa50a1990 MPTAPLE: generate from devicetree.cb
This patch adds support for autogenerating the MPTABLE from
devicetree.cb. This is done by a write_smp_table() declared
weak in mpspec.c. If the mainboard doesn't provide it's own
function, this generic implementation is called.

Syntax in devicetree.cb:

ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN>

The ioapic_irq directive can be used in pci and pci_domain
devices. If there's no directive, the autogen code traverses
the tree back to the pci_domain and stops at the first device
which such a directive, and use that information to generate the
entry according to PCI IRQ routing rules.

Change-Id: I4df5b198e8430f939d477c14c798414e398a2027
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1138
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13 08:38:13 +02:00
Guenter Roeck 21856eec59 superiotool: Dump data registers for Nuvoton chips
Add support to dump all data registers for Nuvoton chips (NCT6775F, NCT6776F,
and NCT6779D). Register contents will be dumped if the -e option is provided on
the command line.

Change-Id: I2b425b48c1f28a10ff3c1ca1d7f21c501eff74ad
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-on: http://review.coreboot.org/1150
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12 08:13:21 +02:00
Guenter Roeck a89da0969e superiotool: Add support for function to dump superio chip data registers
Add new function dump_data() to dump a bank of superio data registers.

Change-Id: I13a58d87c14d319cfcdea1ec1d54c2b110d90f9f
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-on: http://review.coreboot.org/1149
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12 08:13:13 +02:00
Guenter Roeck 975ffc2e0f superiotool: Add support for NCT6775F(A/B) and NCT6779D
Change-Id: I66667fcb58f6885460021f4a2024d6ba56b95f11
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-on: http://review.coreboot.org/1148
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12 08:10:28 +02:00
Anton Kochkov 54c07a675b msrtool: Add Intel Nehalem CPUs support
Added Intel processors based on Nehalem
architecture support, with decoding MSRs.

Change-Id: I576d5eac2542c0b62852bf05e42bc98b134c7eae
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-10 00:57:35 +02:00
Anton Kochkov ffbbecc9ee msrtool: Fix Intel CPUs detection
Added vendor check in sys.c file and fixed models checking
in intel targets files.

Change-Id: I1ce52bbce431dea79e903d6bc7a12e5b9ad061be
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1169
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-10 00:56:49 +02:00
Raymond Danks e1e6a91ce0 mkelfimage: pkgdata directory created but never used
Remove superfluous pkg* definitions and installation of a target
directory directory that is never used.

Change-Id: I2addf3f316230cdd428def5889fd3beb7c40f422
Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
Reviewed-on: http://review.coreboot.org/1195
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-09 22:18:37 +02:00