Commit Graph

26603 Commits

Author SHA1 Message Date
Marcello Sylvester Bauer 9d3b1b206c Linuxboot: remove initramfs path entry
Remove Linuxboot initramfs path entry in Kconfig.
Custom initramfs can and should be used with 'Linux payload'.

Change-Id: I648fb2e0383d20b0e4d50e416af637ea07d1efb4
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-05 20:57:38 +00:00
Marcello Sylvester Bauer 28e0cb4b23 Linuxboot: check go version
Check if the installed Golang version is >= 1.9.

Change-Id: I9fd74fa8dc5e906e8b54ff5afaf69609fe957960
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29445
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 20:56:50 +00:00
Shelley Chen 715cb40963 mb/google/poppy/variants/nami: Enable FP MCU
Some variants of nami will have a fingerprint MCU.

BUG=b:118503113
BRANCH=Nami
TEST=None (build and boot, but no hw yet)

Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05 09:16:41 +00:00
Jonathan Neuschäfer 0f14df46aa nb/intel/x4x/raminit: Add missing space
TEST=Make the printk reachable, check with
     `strings build/cbfs/fallback/romstage.elf | grep lowest`
     that this patch changes "MHzas" to "MHz as".

Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/29346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-05 09:16:07 +00:00
Jonathan Neuschäfer 40a1966400 mb/asus/p5qc: Fix spelling of Marvell
Marvell is the chip company, Marvel makes comic books.

Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/29347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-05 09:15:12 +00:00
Richard Spiegel 9f25e9d480 soc/amd/stoneyridge: Get rid of void pointer math
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.

BUG=b:118484178
TEST=Build and boot grunt.

Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-05 09:14:31 +00:00
Lijian Zhao 7ca21c1024 mb/google/sarien: Enable WWAN detection
WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF#
set to high more than 10 ms, so force RESET#(GPP_D21) to low at
bootblock stage to match the sequence.

BUG=N/A
TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB
devices through lsusb.

Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-05 09:13:59 +00:00
Huayang Duan 6c36d151a8 mediatek/mt8183: Add DDR driver of software impedance part
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
     patches.

Change-Id: I42a33ffb66ffa2f938f85484ffc3a0d3788816b3
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/28837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-11-05 09:13:20 +00:00
Frans Hendriks 392d699570 src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage
soc_rtc_init() is executed in ramstage
The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC
init from ramstage to romstage.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/29397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-05 09:06:55 +00:00
Lijian Zhao fe701ee398 soc/intel/cannonlake: Enable ISH from device
PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.

BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.

Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-11-05 09:06:49 +00:00
David Wu f41cb17fe2 mb/google/fizz: Remove variant_cros_gpios from variant
This change removes the function defintions from variant
so that the weak definition in baseboard can be used.
Refer to CL:813944.

BUG=none
BRANCH=master
TEST=Build and boot on DUT

Change-Id: I561414fcc94e3c812bb88730df9b94e332c61781
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05 09:06:12 +00:00
David Wu 4fe4355377 mb/google/fizz/variants/karma: Update GPIO GPP_D9
Update GPP_D9 to fix audio jack can't detect issue.

BUG=b:118393646
BRANCH=master
TEST=Verify audio jack can auto detect.

Change-Id: I87d24ed294c1ddc59bbd6ba9194c76d1f66413f3
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05 09:06:06 +00:00
Elyes HAOUAS 1a5f1c89d7 cpu/amd: Use common AMD's MSR
This Phase #2 follows the CL done on Phase #1 (Change-Id: I0236e0960cd)

Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29369
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 09:05:51 +00:00
Elyes HAOUAS d35c7fe1bf amd/mtrr: Fix IORR MTRR
IORR MTRR definitions renamed to avoid collision
between <cpu/amd/mtrr.h> and <AGESA.h>.

Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29352
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 09:05:33 +00:00
Enrico Granata c4ba0f4cbd mb/google/octopus/var/bobba: Define GPIO_134 as EC_SYNC_IRQ
Use GPIO_134 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.

BRANCH=none
BUG=crbug:896347, b:118443377
CQ-DEPEND=CL:1298699
TEST=verify sensor events coming in on a reworked board
     with companion EC and kernel patches

Change-Id: I41333cabe97bc8b0d59e19d84366f2ea2a59e026
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/29278
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 09:05:24 +00:00
Lijian Zhao ae4eee17dd soc/intel/cannonlake: Remove depreciated UPD selection
Several FSP silicon init UPD have been moved to memory init stage, modify
the coreboot accordingly. The UPDs below are affected:
    SkipMpInit
    VtdBaseAddress
    VtdDisable
    X2ApicOptOut

BUG=N/A
TEST=Build pass with FSP revision 7.0.47.50.

Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29260
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 09:04:32 +00:00
Xiang Wang 22e0c560bb riscv: add support for supervisor binary interface (SBI)
SBI is runtime service for OS. For an introduction, please refer to
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md

Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-11-05 09:04:01 +00:00
Xiang Wang 26f725efc2 riscv: add support to block smp in each stage
Each stage performs some basic initialization (stack, HLS etc) and then
call smp_pause to enter the single-threaded state. The main work of each
stage is executed in a single-threaded state, and the multi-threaded
state is restored by call smp_resume while booting the next stage.

Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-11-05 09:03:50 +00:00
Xiang Wang 7c9540ea1d riscv: add support smp_pause / smp_resume
See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.

Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-11-05 09:03:40 +00:00
Nick Vaccaro c85f9c5897 mb/google/poppy/variant/nocturne: add Nanya memory option
Add option for Nanya NT6CL256T32CM-H1 part.

Add comments to indicate total memory size for convenience.

BUG=b:118624505
BRANCH=master
TEST=none

Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05 09:03:11 +00:00
Elyes HAOUAS 3b6624b88e src: Remove unneeded include <arch/ioapic.h>
Change-Id: Ic08b191ee4dbcc56eb482601aa268394545936ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29292
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 09:01:42 +00:00
Elyes HAOUAS 1156b35a23 mainboard: Remove unneeded include <console/console.h>
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29285
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 09:01:13 +00:00
Elyes HAOUAS 19f5ba81be amd: Fix non-local header treated as local
Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29103
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 09:00:26 +00:00
Elyes HAOUAS 54f942499b sb/intel/lynxpoint: Remove irrelevant conditional statement
After a {break,return}, "else" is generally not needed.

Change-Id: I6145424ef8ffe6854c18c1d885f579d37853a70c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29267
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 08:57:57 +00:00
Elyes HAOUAS 2a1c4302d1 nb/intel/i945: Remove irrelevant conditional statement
After a {break,return}, "else" is generally not needed.

Change-Id: Id55af179f63316f7218e93978628cbe05e94e0aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-05 08:57:29 +00:00
Elyes HAOUAS 07065edd5e src/mainboard: Remove irrelevant conditional statement
Using a conditional statement to return 0 or 1 depending on a logic
value is unnecessarily complex.

Change-Id: I449ce2b71b72374de5ec4986f9cc9f91a67856ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29265
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 08:56:59 +00:00
Marcello Sylvester Bauer 407f512cfe Linuxboot: gitignore build directory
Add the Linuxboot build directory to .gitignore.

Change-Id: Ic11311e2de544a334043a55eda42643d9df3374d
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-05 08:55:11 +00:00
Aamir Bohra c7267631e2 soc/intel/icelake: Add PID based on Icelake EDS
Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05 04:18:13 +00:00
Angel Pons 5c568e00a5 src/mb/asus/p5qc: Fix some mistakes
There are some small mistakes in these recently-added mainboards:

 - board_info.txt: Lists board socket incorrectly.
 - cmos.default:   Loglevel was decreased some time ago.
 - devicetree.cb:  Spelling mistake.
 - Kconfig:        Mainboard name does not have a hyphen.

Change-Id: I08d9b06e79683acd3994b84647bce401ed6741e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-04 13:26:12 +00:00
Tristan Shieh 42adb29853 google/kukui: Add board id support
Get board id from AUXIN4 and RAM code from AUXIN3.

BUG=b:80501386
BRANCH=none
TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0.
     AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1.

Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-02 19:57:55 +00:00
Po Xu 96631f941d mediatek/mt8183: Add AUXADC driver
We plan to get board id and RAM code from AUXADC on Kukui. Add AUXADC
driver to support it.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I121a6a0240f9c517c0cbc07e0c18b09167849ff1
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/29061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-02 19:57:47 +00:00
Duncan Laurie 7a70b664c4 mb/google/sarien: Enable Wilco EC
The Sarien mainboard uses the newly added Wilco EC.

- enable CONFIG_EC_GOOGLE_WILCO
- add the device and host command ranges to the devicetree
- have the mainboard SMI handlers call the EC handlers
- add EC and SuperIO devices to the ACPI DSDT
- call the early init hook for serial setup

Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-02 16:10:07 +00:00
Duncan Laurie 931a579a2e mb/google/sarien: Add Arcada variant
Add a variant of the Sarien board called Arcada.  This is currently
very similar to Sarien with differences in PCIe, USB, and GPIO usage.

Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29410
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02 16:07:22 +00:00
Duncan Laurie 558602ff40 mb/google/sarien: Add new mainboard
Sarien is a new board using Intel Whiskey Lake SOC.  It also uses
the newly added Wilco EC, enabled in a separate commit.

Sarien is not a true reference board, it is just one variant of
a very similar design.  For that reason it is not considered the
baseboard but rather a standalone variant.

Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-02 16:07:13 +00:00
Duncan Laurie db48f7ea48 ec/google/wilco: Add wake pin configuration
Add a way for the mainboard to provide a wake pin that the EC
will use to wake the system.  This defines a _PRW object.

Change-Id: I94954104bbb8226683c37abc8c0465fe3c62a693
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29408
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02 16:07:01 +00:00
Duncan Laurie f95b4a708e soc/intel: Enable GPIO functions in verstage
Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.

Change-Id: Icd4344c4d66dbe21fda9dc27e61a836c1dd9be07
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29407
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02 16:06:53 +00:00
Marcello Sylvester Bauer 51f2f2eba1 LinuxBoot: use curl
Download the linux kernel tarball with curl.
Curl is already a dependency for coreboot.

Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-02 14:58:56 +00:00
Marcello Sylvester Bauer 78d29bff72 LinuxBoot/X86_64: Enable 8250 uart drivers
Enable 8250 uart drivers on default defconfig.

- makes it easier to debug. (qemu -nographic)
- Kernel size increases only by 20kB.

Change-Id: I8309ecf7afd74b3c4021effedcac47350b442173
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-02 14:58:05 +00:00
Marcello Sylvester Bauer 159656b661 LinuxBoot: fix custom defconfig override
The default ARCH defconfig should not override a custom defconfig.

Change-Id: I9de24497ef6296029c66a94124bc11a0bb4d0107
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-02 14:57:50 +00:00
Tristan Corrick d385624ee6 nb/intel/haswell: Consolidate memory controller PCI driver structs
Since the `PCI_DEVICE_ID_HSW_*` constants are no longer used, remove
them.

Change-Id: I84f1f069faa6a4165cf289f2e6c40889a49cad1d
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-02 09:13:23 +00:00
Ren Kuo d48a3a3b7f mb/google/poppy/variants/nami: Enable radium touchscreen support
Enable the radium touchscreen support

BUG=b:117960394
BRANCH=master
TEST=
1. emerge-nami coreboot chromeos-bootimage
2. boot up on ekko DUT to check touchscreen device by evtest
   /dev/input/event3:	Raydium Touchscreen

Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02 03:22:50 +00:00
Aamir Bohra 23012a0dff soc/intel/icelake: Allow coreboot to reserve stack for fsp
Change-Id: I5f2d9548b8e2c7b1d154b7bad126ec7b1052231a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2018-11-02 03:20:50 +00:00
Aamir Bohra 49e0510d57 mainboard/intel/icelake_rvp: Add ICL flash layout to support IFWI 1.6
Modify flash layout to match ICL-IFWI layout for early SoC PO support

Flash Reg 0: Descriptor [0x0 - 0xFFF]
Flash Reg 1: BIOS [0x400000 - 0xFFFFFF]
Flash Reg 2: IFWI (consist of ME primary & secondary partition and PMC FW)
                  [0x81000 - 0x3FFFFF]
Flash Reg 8: EC (applicable for Intel RVP with internal EC support)
                  [0x1000 - 0x80FFF]

Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29316
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02 03:20:39 +00:00
Tristan Corrick 167a512d84 sb/intel/common: Create a common implementation of `acpi_fill_madt()`
The function `acpi_fill_madt()` is identical among all the Lynx Point
boards and sb/intel/bd82x6x, so share a common function between them.

Earlier Intel platforms have similar implementations of this function.
The common implementation might only need minor alterations to support
them.

Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No
issues arose from this patch.

Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01 22:26:04 +00:00
Tristan Corrick 98fb1bfa90 sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors
If the file `southbridge/intel/lynxpoint/nvs.h` is included in a file
that does not already include <stdint.h>, compilation errors result.

Adding the necessary <stdint.h> inclusions fixes compilation for an
ASRock H81M-HDS.

Change-Id: Id0d14705282cc959146e00dd47754ee8a2e8e825
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01 22:24:24 +00:00
Tristan Corrick 32664fd323 sb/intel/lynxpoint: Add a common platform.asl file
The platform.asl file is copied from sb/intel/bd82x6x, and also matches
the contents deleted from each mainboard's platform.asl.

Tested on an ASRock H81M-HDS and a Google Peppy board (variant of
Slippy). No issues arose from this patch.

Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01 22:24:03 +00:00
Tristan Corrick 1a73eb08e7 nb/intel/haswell/gma: Support boards that have DDI E connected
On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to
initialise the display when lanes are not configured to be shared
between DDI A and DDI E.

Intel's reference manual [1] states that the decision to share lanes
between DDI A and DDI E is "based on board configuration". Hence, add a
new field to the devicetree that boards can set. All existing Haswell
boards have this unset, thus taking a value of 0, so there is no change
to existing behaviour.

[1]: Intel Open Source Graphics Programmer's Reference Manual (PRM)
     Volume 2c: Command Reference: Registers (Haswell)
     https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013-intel-core-processor-family

Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29385
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01 22:23:52 +00:00
Tristan Corrick fdf907e440 cpu/intel/haswell: Only change the slow ramp rate for ULT CPUs
On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow
ramp rate during `initialize_vr_config()` results in the following
exception, causing the system to hang.

	CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
	Code: 0 eflags: 00010006 cr2: 00000000
	eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
	edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90

So, only change this setting for Haswell ULT CPUs, as suggested by the
BIOS Writer's guide.

Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01 22:23:21 +00:00
Tristan Corrick ba8ead817d cpu/intel/haswell: Allow use of TSC for the monotonic timer
When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS
with a Pentium G3258, the following exception is generated, causing the
system to hang.

	CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
	Code: 0 eflags: 00010006 cr2: 00000000
	eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
	edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90

The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located
at 0x637. This MSR only exists on Haswell-ULT CPUs.

So, allow boards to use the TSC monotonic timer instead. They can do
this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig.

Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01 22:22:57 +00:00
Tristan Corrick 655ef61937 sb/intel/lynxpoint: Provide a function for mainboard super I/O config
The super I/O setup needs to be done after the LPC is enabled. For
Lynx Point, configuring the super I/O in `mainboard_romstage_entry()`
is too early to get a serial console output. To remedy this, add a
function `mainboard_config_superio()` that will be called at the
appropriate time, and can be overridden by mainboard code.

Change-Id: Iaf4188a17533c636e7b0c7efa220bc6a25876dda
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01 22:22:43 +00:00